4 * Stefan Roese, DENX Software Engineering, sr@denx.de.
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
27 #include <asm/immap_85xx.h>
28 #include <asm/processor.h>
35 unsigned long refresh;
36 #endif /* CONFIG_TQM8548 */
39 typedef struct sdram_conf_s sdram_conf_t;
42 #ifdef CONFIG_TQM8548_AG
43 sdram_conf_t ddr_cs_conf[] = {
44 {(1024 << 20), 0x80044202, 0x0002D000}, /* 1024MB, 14x10(4) */
45 { (512 << 20), 0x80044102, 0x0001A000}, /* 512MB, 13x10(4) */
46 { (256 << 20), 0x80040102, 0x00014000}, /* 256MB, 13x10(4) */
47 { (128 << 20), 0x80040101, 0x0000C000}, /* 128MB, 13x9(4) */
49 #else /* !CONFIG_TQM8548_AG */
50 sdram_conf_t ddr_cs_conf[] = {
51 {(512 << 20), 0x80044102, 0x0001A000}, /* 512MB, 13x10(4) */
52 {(256 << 20), 0x80040102, 0x00014000}, /* 256MB, 13x10(4) */
53 {(128 << 20), 0x80040101, 0x0000C000}, /* 128MB, 13x9(4) */
55 #endif /* CONFIG_TQM8548_AG */
56 #else /* !CONFIG_TQM8548 */
57 sdram_conf_t ddr_cs_conf[] = {
58 {(512 << 20), 0x80000202}, /* 512MB, 14x10(4) */
59 {(256 << 20), 0x80000102}, /* 256MB, 13x10(4) */
60 {(128 << 20), 0x80000101}, /* 128MB, 13x9(4) */
61 {( 64 << 20), 0x80000001}, /* 64MB, 12x9(4) */
63 #endif /* CONFIG_TQM8548 */
65 #define N_DDR_CS_CONF (sizeof(ddr_cs_conf) / sizeof(ddr_cs_conf[0]))
67 int cas_latency (void);
68 static phys_size_t sdram_setup(int);
71 * Autodetect onboard DDR SDRAM on 85xx platforms
73 * NOTE: Some of the hardcoded values are hardware dependant,
74 * so this should be extended for other future boards
77 phys_size_t fixed_sdram(void)
80 phys_size_t dram_size = 0;
83 dram_size = sdram_setup(casl);
84 if ((dram_size == 0) && (casl != CONFIG_DDR_DEFAULT_CL)) {
86 * Try again with default CAS latency
88 printf("Problem with CAS lantency, using default CL %d/10!\n",
89 CONFIG_DDR_DEFAULT_CL);
90 dram_size = sdram_setup(CONFIG_DDR_DEFAULT_CL);
96 static phys_size_t sdram_setup(int casl)
99 volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
100 #ifdef CONFIG_TQM8548
101 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
102 #if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE)
103 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
105 #else /* !CONFIG_TQM8548 */
106 unsigned long cfg_ddr_timing1;
107 unsigned long cfg_ddr_mode;
108 #endif /* CONFIG_TQM8548 */
111 * Disable memory controller.
116 #ifdef CONFIG_TQM8548
117 /* Timing and refresh settings for DDR2-533 and below */
119 ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24;
120 ddr->cs0_config = ddr_cs_conf[0].reg;
121 ddr->timing_cfg_3 = 0x00020000;
123 /* TIMING CFG 1, 533MHz
125 * ACTTOPRE: 12 Clocks
128 * REFREC: EXT_REFREC:REFREC 53 Clocks
133 ddr->timing_cfg_1 = 0x4C47D432;
135 /* TIMING CFG 2, 533MHz
139 * RD_TO_PRE: 2 Clocks
140 * WR_DATA_DELAY: 1/2 Clock
142 * FOUR_ACT: 14 Clocks
144 ddr->timing_cfg_2 = 0x331848CE;
146 /* DDR SDRAM Mode, 533MHz
147 * MRS: Extended Mode Register
148 * OUT: Outputs enabled
153 * Posted CAS: 3 Clocks
154 * ODS: reduced strength
161 * CAS latency: 4 Clocks
165 ddr->sdram_mode = 0x439E0642;
167 /* DDR SDRAM Interval, 533MHz
168 * REFINT: 1040 Clocks
171 ddr->sdram_interval = (1040 << 16) | 0x100;
174 * Workaround for erratum DDR19 according to MPC8548 Device Errata
175 * document, Rev. 1: DDR IO receiver must be set to an acceptable
176 * bias point by modifying a hidden register.
178 if (SVR_REV (get_svr ()) < 0x21)
179 gur->ddrioovcr = 0x90000000; /* enable, VSEL 1.8V */
182 * FRC_SR: normal mode
183 * SR_IE: no self-refresh interrupt
184 * DLL_RST_DIS: don't care, leave at reset value
185 * DQS_CFG: differential DQS signals
186 * ODT_CFG: assert ODT to internal IOs only during reads to DRAM
187 * LVWx_CFG: don't care, leave at reset value
188 * NUM_PR: 1 refresh will be issued at a time
189 * DM_CFG: don't care, leave at reset value
190 * D_INIT: no data initialization
192 ddr->sdram_cfg_2 = 0x04401000;
195 * MRS: Extended Mode Register 2
197 ddr->sdram_mode_2 = 0x8000C000;
199 /* DDR SDRAM CLK CNTL
200 * CLK_ADJUST: 1/2 Clock 0x02000000
201 * CLK_ADJUST: 5/8 Clock 0x02800000
203 ddr->sdram_clk_cntl = 0x02800000;
205 /* wait for clock stabilization */
206 asm ("sync;isync;msync");
209 #if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE)
211 * Workaround for erratum DDR20 according to MPC8548 Device Errata
212 * document, Rev. 1: "CKE signal may not function correctly after
213 * assertion of HRESET"
216 /* 1. Configure DDR register as is done in normal DDR configuration.
217 * Do not set DDR_SDRAM_CFG[MEM_EN].
219 * 2. Set reserved bit EEBACR[3] at offset 0x1000
221 ecm->eebacr |= 0x10000000;
224 * 3. Before DDR_SDRAM_CFG[MEM_EN] is set, write DDR_SDRAM_CFG_2[D_INIT]
227 * FRC_SR: normal mode
228 * SR_IE: no self-refresh interrupt
229 * DLL_RST_DIS: don't care, leave at reset value
230 * DQS_CFG: differential DQS signals
231 * ODT_CFG: assert ODT to internal IOs only during reads to DRAM
232 * LVWx_CFG: don't care, leave at reset value
233 * NUM_PR: 1 refresh will be issued at a time
234 * DM_CFG: don't care, leave at reset value
235 * D_INIT: enable data initialization
237 ddr->sdram_cfg_2 |= 0x00000010;
240 * 4. Before DDR_SDRAM_CFG[MEM_EN] set, write D3[21] to disable data
243 ddr->debug_3 |= 0x00000400;
246 * 5. Wait 200 micro-seconds
251 * 6. Set DDR_SDRAM_CFG[MEM_EN]
253 * BTW, initialize DDR_SDRAM_CFG:
255 * SREN: don't care, leave at reset value
256 * ECC_EN: no error report
257 * RD_EN: no registered DIMMs
259 * DYN_PWR: no power management
260 * 32_BE: don't care, leave at reset value
262 * NCAP: don't care, leave at reset value
264 * BA_INTLV_CTL: no interleaving
265 * x32_EN: x16 organization
266 * PCHB8: MA[10] for auto-precharge
267 * HSE: half strength for single and 2-layer stacks
268 * (full strength for 3- and 4-layer stacks not
271 * BI: automatic initialization
273 ddr->sdram_cfg = 0x83000008;
276 * 7. Poll DDR_SDRAM_CFG_2[D_INIT] until it is cleared by hardware
278 asm ("sync;isync;msync");
279 while (ddr->sdram_cfg_2 & 0x00000010)
283 * 8. Clear D3[21] to re-enable data training
285 ddr->debug_3 &= ~0x00000400;
288 * 9. Set D2(21) to force data training to run
290 ddr->debug_2 |= 0x00000400;
293 * 10. Poll on D2[21] until it is cleared by hardware
295 asm ("sync;isync;msync");
296 while (ddr->debug_2 & 0x00000400)
300 * 11. Clear reserved bit EEBACR[3] at offset 0x1000
302 ecm->eebacr &= ~0x10000000;
304 #else /* !(CONFIG_TQM8548_AG || CONFIG_TQM8548_BE) */
306 /* DDR SDRAM CLK CNTL
308 * SREN: don't care, leave at reset value
309 * ECC_EN: no error report
310 * RD_EN: no register DIMMs
312 * DYN_PWR: no power management
313 * 32_BE: don't care, leave at reset value
315 * NCAP: don't care, leave at reset value
317 * BA_INTLV_CTL: no interleaving
318 * x32_EN: x16 organization
319 * PCHB8: MA[10] for auto-precharge
320 * HSE: half strength for single and 2-layer stacks
321 * (full strength for 3- and 4-layer stacks no yet considered)
323 * BI: automatic initialization
325 ddr->sdram_cfg = 0x83000008;
327 #endif /* CONFIG_TQM8548_AG || CONFIG_TQM8548_BE */
329 asm ("sync; isync; msync");
331 #else /* !CONFIG_TQM8548 */
334 cfg_ddr_timing1 = 0x47405331 | (3 << 16);
335 cfg_ddr_mode = 0x40020002 | (2 << 4);
339 cfg_ddr_timing1 = 0x47405331 | (4 << 16);
340 cfg_ddr_mode = 0x40020002 | (6 << 4);
345 cfg_ddr_timing1 = 0x47405331 | (5 << 16);
346 cfg_ddr_mode = 0x40020002 | (3 << 4);
350 ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24;
351 ddr->cs0_config = ddr_cs_conf[0].reg;
352 ddr->timing_cfg_1 = cfg_ddr_timing1;
353 ddr->timing_cfg_2 = 0x00000800; /* P9-45,may need tuning */
354 ddr->sdram_mode = cfg_ddr_mode;
355 ddr->sdram_interval = 0x05160100; /* autocharge,no open page */
356 ddr->err_disable = 0x0000000D;
358 asm ("sync; isync; msync");
361 ddr->sdram_cfg = 0xc2000000; /* unbuffered,no DYN_PWR */
362 asm ("sync; isync; msync");
364 #endif /* CONFIG_TQM8548 */
366 for (i = 0; i < N_DDR_CS_CONF; i++) {
367 ddr->cs0_config = ddr_cs_conf[i].reg;
369 if (get_ram_size (0, ddr_cs_conf[i].size) ==
370 ddr_cs_conf[i].size) {
372 * size detected -> set Chip Select Bounds Register
374 ddr->cs0_bnds = (ddr_cs_conf[i].size - 1) >> 24;
380 #ifdef CONFIG_TQM8548
381 if (i < N_DDR_CS_CONF) {
382 /* Adjust refresh rate for DDR2 */
384 ddr->timing_cfg_3 = ddr_cs_conf[i].refresh & 0x00070000;
386 ddr->timing_cfg_1 = (ddr->timing_cfg_1 & 0xFFFF0FFF) |
387 (ddr_cs_conf[i].refresh & 0x0000F000);
389 return ddr_cs_conf[i].size;
391 #endif /* CONFIG_TQM8548 */
393 /* return size if detected, else return 0 */
394 return (i < N_DDR_CS_CONF) ? ddr_cs_conf[i].size : 0;
397 #if defined(CONFIG_SYS_DRAM_TEST)
400 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
401 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
404 printf ("SDRAM test phase 1:\n");
405 for (p = pstart; p < pend; p++)
408 for (p = pstart; p < pend; p++) {
409 if (*p != 0xaaaaaaaa) {
410 printf ("SDRAM test fails at: %08x\n", (uint) p);
415 printf ("SDRAM test phase 2:\n");
416 for (p = pstart; p < pend; p++)
419 for (p = pstart; p < pend; p++) {
420 if (*p != 0x55555555) {
421 printf ("SDRAM test fails at: %08x\n", (uint) p);
426 printf ("SDRAM test passed.\n");