2 * (C) Copyright 2000-2008
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
15 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
19 extern flash_info_t flash_info[]; /* FLASH chips info */
21 DECLARE_GLOBAL_DATA_PTR;
23 static long int dram_size (long int, long int *, long int);
25 #define _NOT_USED_ 0xFFFFFFFF
27 /* UPM initialization table for SDRAM: 40, 50, 66 MHz CLKOUT @ CAS latency 2, tWR=2 */
28 const uint sdram_table[] =
31 * Single Read. (Offset 0 in UPMA RAM)
33 0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00,
34 0x1FF5FC47, /* last */
36 * SDRAM Initialization (offset 5 in UPMA RAM)
38 * This is no UPM entry point. The following definition uses
39 * the remaining space to establish an initialization
40 * sequence, which is executed by a RUN command.
43 0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
45 * Burst Read. (Offset 8 in UPMA RAM)
47 0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00,
48 0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
49 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
50 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
52 * Single Write. (Offset 18 in UPMA RAM)
54 0x1F0DFC04, 0xEEABBC00, 0x11B77C04, 0xEFFAFC44,
55 0x1FF5FC47, /* last */
56 _NOT_USED_, _NOT_USED_, _NOT_USED_,
58 * Burst Write. (Offset 20 in UPMA RAM)
60 0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
61 0xF0AFFC00, 0xF0AFFC04, 0xE1BAFC44, 0x1FF5FC47, /* last */
62 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
63 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
65 * Refresh (Offset 30 in UPMA RAM)
67 0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
68 0xFFFFFC84, 0xFFFFFC07, /* last */
69 _NOT_USED_, _NOT_USED_,
70 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
72 * Exception. (Offset 3c in UPMA RAM)
74 0xFFFFFC07, /* last */
75 _NOT_USED_, _NOT_USED_, _NOT_USED_,
78 /* ------------------------------------------------------------------------- */
82 * Check Board Identity:
84 * Test TQ ID string (TQM8xx...)
85 * If present, check for "L" type (no second DRAM bank),
86 * otherwise "L" type is assumed as default.
88 * Set board_type to 'L' for "L" type, 'M' for "M" type, 0 else.
95 int l = getenv_f("serial#", buf, sizeof(buf));
99 if (l < 0 || strncmp(buf, "TQM8", 4)) {
100 puts ("### No HW ID - assuming TQM8xxL\n");
104 if ((buf[6] == 'L')) { /* a TQM8xxL type */
105 gd->board_type = 'L';
108 if ((buf[6] == 'M')) { /* a TQM8xxM type */
109 gd->board_type = 'M';
112 if ((buf[6] == 'D')) { /* a TQM885D type */
113 gd->board_type = 'D';
116 for (i = 0; i < l; ++i) {
127 /* ------------------------------------------------------------------------- */
131 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
132 volatile memctl8xx_t *memctl = &immap->im_memctl;
133 long int size8, size9, size10;
134 long int size_b0 = 0;
135 long int size_b1 = 0;
136 int board_type = gd->board_type;
138 upmconfig (UPMA, (uint *) sdram_table,
139 sizeof (sdram_table) / sizeof (uint));
142 * Preliminary prescaler for refresh (depends on number of
143 * banks): This value is selected for four cycles every 62.4 us
144 * with two SDRAM banks or four cycles every 31.2 us with one
145 * bank. It will be adjusted after memory sizing.
147 memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
150 * The following value is used as an address (i.e. opcode) for
151 * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
152 * the port size is 32bit the SDRAM does NOT "see" the lower two
153 * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
156 * | | | | +- Burst Length = 4
157 * | | | +----- Burst Type = Sequential
158 * | | +------- CAS Latency = 2
159 * | +----------- Operating Mode = Standard
160 * +-------------- Write Burst Mode = Programmed Burst Length
162 memctl->memc_mar = 0x00000088;
165 * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
166 * preliminary addresses - these have to be modified after the
167 * SDRAM size has been determined.
169 memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
170 memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
172 #ifndef CONFIG_CAN_DRIVER
173 if ((board_type != 'L') &&
174 (board_type != 'M') &&
175 (board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */
176 memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
177 memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
179 #endif /* CONFIG_CAN_DRIVER */
181 memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
185 /* perform SDRAM initializsation sequence */
187 memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
189 memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */
192 #ifndef CONFIG_CAN_DRIVER
193 if ((board_type != 'L') &&
194 (board_type != 'M') &&
195 (board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */
196 memctl->memc_mcr = 0x80006105; /* SDRAM bank 1 */
198 memctl->memc_mcr = 0x80006230; /* SDRAM bank 1 - execute twice */
201 #endif /* CONFIG_CAN_DRIVER */
203 memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
208 * Check Bank 0 Memory Size for re-configuration
212 size8 = dram_size (CONFIG_SYS_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
213 debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size8 >> 20);
220 size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
221 debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size9 >> 20);
225 #if defined(CONFIG_SYS_MAMR_10COL)
229 size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
230 debug ("SDRAM Bank 0 in 10 column mode: %ld MB\n", size10 >> 20);
233 #endif /* CONFIG_SYS_MAMR_10COL */
235 if ((size8 < size10) && (size9 < size10)) {
237 } else if ((size8 < size9) && (size10 < size9)) {
239 memctl->memc_mamr = CONFIG_SYS_MAMR_9COL;
243 memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
246 debug ("SDRAM Bank 0: %ld MB\n", size_b0 >> 20);
248 #ifndef CONFIG_CAN_DRIVER
249 if ((board_type != 'L') &&
250 (board_type != 'M') &&
251 (board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */
253 * Check Bank 1 Memory Size
254 * use current column settings
255 * [9 column SDRAM may also be used in 8 column mode,
256 * but then only half the real size will be used.]
258 size_b1 = dram_size (memctl->memc_mamr, (long int *)SDRAM_BASE3_PRELIM,
260 debug ("SDRAM Bank 1: %ld MB\n", size_b1 >> 20);
264 #endif /* CONFIG_CAN_DRIVER */
269 * Adjust refresh rate depending on SDRAM type, both banks
270 * For types > 128 MBit leave it at the current (fast) rate
272 if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
273 /* reduce to 15.6 us (62.4 us / quad) */
274 memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
279 * Final mapping: map bigger bank first
281 if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */
283 memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
284 memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
288 * Position Bank 0 immediately above Bank 1
290 memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
291 memctl->memc_br2 = ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
301 memctl->memc_br2 = 0;
303 /* adjust refresh rate depending on SDRAM type, one bank */
304 reg = memctl->memc_mptpr;
305 reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
306 memctl->memc_mptpr = reg;
309 } else { /* SDRAM Bank 0 is bigger - map first */
311 memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
313 (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
317 * Position Bank 1 immediately above Bank 0
320 ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
322 ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
327 #ifndef CONFIG_CAN_DRIVER
333 memctl->memc_br3 = 0;
334 #endif /* CONFIG_CAN_DRIVER */
336 /* adjust refresh rate depending on SDRAM type, one bank */
337 reg = memctl->memc_mptpr;
338 reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
339 memctl->memc_mptpr = reg;
345 #ifdef CONFIG_CAN_DRIVER
346 /* UPM initialization for CAN @ CLKOUT <= 66 MHz */
348 /* Initialize OR3 / BR3 */
349 memctl->memc_or3 = CONFIG_SYS_OR3_CAN;
350 memctl->memc_br3 = CONFIG_SYS_BR3_CAN;
352 /* Initialize MBMR */
353 memctl->memc_mbmr = MBMR_GPL_B4DIS; /* GPL_B4 ouput line Disable */
355 /* Initialize UPMB for CAN: single read */
356 memctl->memc_mdr = 0xFFFFCC04;
357 memctl->memc_mcr = 0x0100 | UPMB;
359 memctl->memc_mdr = 0x0FFFD004;
360 memctl->memc_mcr = 0x0101 | UPMB;
362 memctl->memc_mdr = 0x0FFFC000;
363 memctl->memc_mcr = 0x0102 | UPMB;
365 memctl->memc_mdr = 0x3FFFC004;
366 memctl->memc_mcr = 0x0103 | UPMB;
368 memctl->memc_mdr = 0xFFFFDC07;
369 memctl->memc_mcr = 0x0104 | UPMB;
371 /* Initialize UPMB for CAN: single write */
372 memctl->memc_mdr = 0xFFFCCC04;
373 memctl->memc_mcr = 0x0118 | UPMB;
375 memctl->memc_mdr = 0xCFFCDC04;
376 memctl->memc_mcr = 0x0119 | UPMB;
378 memctl->memc_mdr = 0x3FFCC000;
379 memctl->memc_mcr = 0x011A | UPMB;
381 memctl->memc_mdr = 0xFFFCC004;
382 memctl->memc_mcr = 0x011B | UPMB;
384 memctl->memc_mdr = 0xFFFDC405;
385 memctl->memc_mcr = 0x011C | UPMB;
386 #endif /* CONFIG_CAN_DRIVER */
388 #ifdef CONFIG_ISP1362_USB
389 /* Initialize OR5 / BR5 */
390 memctl->memc_or5 = CONFIG_SYS_OR5_ISP1362;
391 memctl->memc_br5 = CONFIG_SYS_BR5_ISP1362;
392 #endif /* CONFIG_ISP1362_USB */
393 gd->ram_size = size_b0 + size_b1;
398 /* ------------------------------------------------------------------------- */
401 * Check memory range for valid RAM. A simple memory test determines
402 * the actually available RAM size between addresses `base' and
403 * `base + maxsize'. Some (not all) hardware errors are detected:
404 * - short between address lines
405 * - short between data lines
408 static long int dram_size (long int mamr_value, long int *base, long int maxsize)
410 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
411 volatile memctl8xx_t *memctl = &immap->im_memctl;
413 memctl->memc_mamr = mamr_value;
415 return (get_ram_size(base, maxsize));
418 /* ------------------------------------------------------------------------- */
420 #ifdef CONFIG_MISC_INIT_R
421 extern void load_sernum_ethaddr(void);
422 int misc_init_r (void)
424 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
425 volatile memctl8xx_t *memctl = &immap->im_memctl;
427 load_sernum_ethaddr();
429 #ifdef CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ
430 int scy, trlx, flash_or_timing, clk_diff;
432 scy = (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4;
433 if (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) {
441 * We assume that each 10MHz of bus clock require 1-clk SCY
444 clk_diff = (gd->bus_clk / 1000000) - 50;
447 * We need proper rounding here. This is what the "+5" and "-5"
451 scy += (clk_diff + 5) / 10;
453 scy += (clk_diff - 5) / 10;
456 * For bus frequencies above 50MHz, we want to use relaxed timing
459 if (gd->bus_clk >= 50000000)
472 flash_or_timing = (scy << 4) | trlx |
473 (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & ~(OR_TRLX | OR_SCY_MSK));
476 flash_or_timing | (-flash_info[0].size & OR_AM_MSK);
479 CONFIG_SYS_OR_TIMING_FLASH | (-flash_info[0].size & OR_AM_MSK);
481 memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
483 debug ("## BR0: 0x%08x OR0: 0x%08x\n",
484 memctl->memc_br0, memctl->memc_or0);
486 if (flash_info[1].size) {
487 #ifdef CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ
488 memctl->memc_or1 = flash_or_timing |
489 (-flash_info[1].size & 0xFFFF8000);
491 memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH |
492 (-flash_info[1].size & 0xFFFF8000);
495 ((CONFIG_SYS_FLASH_BASE +
497 size) & BR_BA_MSK) | BR_MS_GPCM | BR_V;
499 debug ("## BR1: 0x%08x OR1: 0x%08x\n",
500 memctl->memc_br1, memctl->memc_or1);
502 memctl->memc_br1 = 0; /* invalidate bank */
504 debug ("## DISABLE BR1: 0x%08x OR1: 0x%08x\n",
505 memctl->memc_br1, memctl->memc_or1);
508 # ifdef CONFIG_IDE_LED
509 /* Configure PA15 as output port */
510 immap->im_ioport.iop_padir |= 0x0001;
511 immap->im_ioport.iop_paodr |= 0x0001;
512 immap->im_ioport.iop_papar &= ~0x0001;
513 immap->im_ioport.iop_padat &= ~0x0001; /* turn it off */
518 #endif /* CONFIG_MISC_INIT_R */
521 # ifdef CONFIG_IDE_LED
522 void ide_led (uchar led, uchar status)
524 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
526 /* We have one led for both pcmcia slots */
527 if (status) { /* led on */
528 immap->im_ioport.iop_padat |= 0x0001;
530 immap->im_ioport.iop_padat &= ~0x0001;
535 #ifdef CONFIG_LCD_INFO
538 #include <timestamp.h>
540 void lcd_show_board_info(void)
544 lcd_printf ("%s (%s - %s)\n", U_BOOT_VERSION, U_BOOT_DATE, U_BOOT_TIME);
545 lcd_printf ("(C) 2008 DENX Software Engineering GmbH\n");
546 lcd_printf (" Wolfgang DENK, wd@denx.de\n");
547 #ifdef CONFIG_LCD_INFO_BELOW_LOGO
548 lcd_printf ("MPC823 CPU at %s MHz\n",
549 strmhz(temp, gd->cpu_clk));
550 lcd_printf (" %ld MB RAM, %ld MB Flash\n",
552 gd->bd->bi_flashsize >> 20 );
554 /* leave one blank line */
555 lcd_printf ("\nMPC823 CPU at %s MHz, %ld MB RAM, %ld MB Flash\n",
556 strmhz(temp, gd->cpu_clk),
558 gd->bd->bi_flashsize >> 20 );
559 #endif /* CONFIG_LCD_INFO_BELOW_LOGO */
561 #endif /* CONFIG_LCD_INFO */
564 * Device Tree Support
566 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
567 int fdt_set_node_and_value (void *blob,
576 nodeoffset = fdt_path_offset (blob, nodename);
577 if (nodeoffset >= 0) {
578 ret = fdt_setprop (blob, nodeoffset, regname, var,
581 printf("ft_blob_update(): "
582 "cannot set %s/%s property; err: %s\n",
583 nodename, regname, fdt_strerror (ret));
586 printf("ft_blob_update(): "
587 "cannot find %s node err:%s\n",
588 nodename, fdt_strerror (nodeoffset));
593 int fdt_del_node_name (void *blob, char *nodename)
598 nodeoffset = fdt_path_offset (blob, nodename);
599 if (nodeoffset >= 0) {
600 ret = fdt_del_node (blob, nodeoffset);
602 printf("%s: cannot delete %s; err: %s\n",
603 __func__, nodename, fdt_strerror (ret));
606 printf("%s: cannot find %s node err:%s\n",
607 __func__, nodename, fdt_strerror (nodeoffset));
612 int fdt_del_prop_name (void *blob, char *nodename, char *propname)
617 nodeoffset = fdt_path_offset (blob, nodename);
618 if (nodeoffset >= 0) {
619 ret = fdt_delprop (blob, nodeoffset, propname);
621 printf("%s: cannot delete %s %s; err: %s\n",
622 __func__, nodename, propname,
626 printf("%s: cannot find %s node err:%s\n",
627 __func__, nodename, fdt_strerror (nodeoffset));
633 * update "brg" property in the blob
635 void ft_blob_update (void *blob, bd_t *bd)
641 brg_data = cpu_to_be32(bd->bi_busfreq);
642 fdt_set_node_and_value(blob,
643 "/soc/cpm", "brg-frequency",
644 &brg_data, sizeof(brg_data));
647 if (eth_getenv_enetaddr("ethaddr", enetaddr)) {
648 fdt_set_node_and_value(blob,
649 "ethernet0", "local-mac-address",
650 enetaddr, sizeof(u8) * 6);
653 if (hwconfig_arg_cmp("fec", "off")) {
654 /* no FEC on this plattform, delete DTS nodes */
655 fdt_del_node_name (blob, "ethernet1");
656 fdt_del_node_name (blob, "mdio1");
657 /* also the aliases entries */
658 fdt_del_prop_name (blob, "/aliases", "ethernet1");
659 fdt_del_prop_name (blob, "/aliases", "mdio1");
661 /* adjust local-mac-address for FEC ethernet */
662 if (eth_getenv_enetaddr("eth1addr", enetaddr)) {
663 fdt_set_node_and_value(blob,
664 "ethernet1", "local-mac-address",
665 enetaddr, sizeof(u8) * 6);
670 int ft_board_setup(void *blob, bd_t *bd)
672 ft_cpu_setup(blob, bd);
673 ft_blob_update(blob, bd);
677 #endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */