3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
9 * Yoo. Jonghoon, IPone, yooth@ipone.co.kr
10 * U-Boot port on RPXlite board
12 * DRAM related UPMA register values are modified.
13 * See RPXLite engineering note : 50MHz/60ns - UPM RAM WORDS
19 /* ------------------------------------------------------------------------- */
21 static long int dram_size (void);
23 /* ------------------------------------------------------------------------- */
25 #define MBYTE (1024*1024)
26 #define DRAM_DELAY 0x00000379 /* DRAM delay count */
27 #define _NOT_USED_ 0xFFFFCC25
29 const uint sdram_table[] =
31 /* single read. (offset 0 in upm RAM) */
32 0x1F07D004, 0xEEAEE004, 0x11ADD004, 0xEFBBA000,
33 0x1FF75447, 0x1FF77C34, 0xEFEABC34, 0x1FB57C35,
35 /* burst read. (Offset 8 in upm RAM) */
36 0x1F07D004, 0xEEAEE004, 0x00ADC004, 0x00AFC000,
37 0x00AFC000, 0x01AFC000, 0x0FBB8000, 0x1FF75447,
38 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
39 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
41 /* single write. (Offset 0x18 in upm RAM) */
42 0x1F27D004, 0xEEAEA000, 0x01B90004, 0x1FF75447,
43 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
45 /* burst write. (Offset 0x20 in upm RAM) */
46 0x1F07D004, 0xEEAEA000, 0x00AD4000, 0x00AFC000,
47 0x00AFC000, 0x01BB8004, 0x1FF75447, 0xFFFFFFFF,
48 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
49 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
51 /* Refresh cycle, offset 0x30 */
52 0x1FF5DC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
53 0xFFFFFC84, 0xFFFFFC07, 0xFFFFFFFF, 0xFFFFFFFF,
54 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
56 /* Exception, 0ffset 0x3C */
57 0x7FFFFC07, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
59 /* ------------------------------------------------------------------------- */
63 * Check Board Identity:
71 printf("Marel V37\n") ;
75 /* ------------------------------------------------------------------------- */
77 phys_size_t initdram (int board_type)
79 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
80 volatile memctl8xx_t *memctl = &immap->im_memctl;
82 volatile int delay_cnt;
85 ramsize = dram_size();
87 /* Refresh clock prescalar */
88 memctl->memc_mptpr = 0x400 ;
90 if( ramsize == 32*MBYTE )
95 memctl->memc_mbmr = temp;
97 upmconfig(UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
99 /* Map controller banks 2 to the SDRAM bank */
100 memctl->memc_or2 = 0xA00 | (0 - ramsize);
101 memctl->memc_br2 = 0xC1;
103 memctl->memc_mbmr = temp | 0x08;
104 memctl->memc_mcr = 0x80804130;
107 while( delay_cnt++ < DRAM_DELAY )
110 /* Run MRS command in location 5-8 of UPMB */
112 memctl->memc_mbmr = temp | 0x04;
113 memctl->memc_mar = 0x88;
115 memctl->memc_mcr = 0x80804105;
118 while( delay_cnt++ < DRAM_DELAY )
121 #ifdef CONFIG_CAN_DRIVER
122 /* Initialize OR3 / BR3 */
123 memctl->memc_or3 = CONFIG_SYS_OR3_CAN;
124 memctl->memc_br3 = CONFIG_SYS_BR3_CAN;
126 /* Initialize MBMR */
127 memctl->memc_mamr = MAMR_GPL_A4DIS; /* GPL_A4 ouput line Disable */
129 /* Initialize UPMB for CAN: single read */
130 memctl->memc_mdr = 0xFFFFC004;
131 memctl->memc_mcr = 0x0100 | UPMA;
133 memctl->memc_mdr = 0x0FFFD004;
134 memctl->memc_mcr = 0x0101 | UPMA;
136 memctl->memc_mdr = 0x0FFFC000;
137 memctl->memc_mcr = 0x0102 | UPMA;
139 memctl->memc_mdr = 0x3FFFC004;
140 memctl->memc_mcr = 0x0103 | UPMA;
142 memctl->memc_mdr = 0xFFFFDC05;
143 memctl->memc_mcr = 0x0104 | UPMA;
145 /* Initialize UPMB for CAN: single write */
146 memctl->memc_mdr = 0xFFFCC004;
147 memctl->memc_mcr = 0x0118 | UPMA;
149 memctl->memc_mdr = 0xCFFCD004;
150 memctl->memc_mcr = 0x0119 | UPMA;
152 memctl->memc_mdr = 0x0FFCC000;
153 memctl->memc_mcr = 0x011A | UPMA;
155 memctl->memc_mdr = 0x7FFCC004;
156 memctl->memc_mcr = 0x011B | UPMA;
158 memctl->memc_mdr = 0xFFFDCC05;
159 memctl->memc_mcr = 0x011C | UPMA;
160 #endif /* CONFIG_CAN_DRIVER */
162 return (dram_size());
165 /* ------------------------------------------------------------------------- */
168 * Find size of RAM from configuration pins.
169 * The input pins that contain the memory size are also the debug port
170 * pins. Normally they are configured as debug port pins. To be able
171 * to read the memory configuration, we must deactivate the debug port
172 * and enable the pcmcia input pins. Then return the register to
176 static long int dram_size ()
178 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
179 volatile sysconf8xx_t *siu = &immap->im_siu_conf;
180 volatile pcmconf8xx_t *pcm = &immap->im_pcmcia;
181 long int i, memory=1;
182 unsigned long siu_mcr;
184 siu_mcr = siu->sc_siumcr;
185 siu->sc_siumcr = siu_mcr & 0xFF9FFFFF;
186 for(i=0; i<10; i++) i = i;
188 memory = (pcm->pcmc_pipr>>12) & 0x3;
190 siu->sc_siumcr = siu_mcr;