git.sur5r.net Git - u-boot/blob - board/xilinx/zynq/board.c

   1 /*
   2  * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <fdtdec.h>
   9 #include <fpga.h>
  10 #include <mmc.h>
  11 #include <zynqpl.h>
  12 #include <asm/arch/hardware.h>
  13 #include <asm/arch/sys_proto.h>
  14
  15 DECLARE_GLOBAL_DATA_PTR;
  16
  17 #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
  18     (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
  19 static xilinx_desc fpga;
  20
  21 /* It can be done differently */
  22 static xilinx_desc fpga007s = XILINX_XC7Z007S_DESC(0x7);
  23 static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
  24 static xilinx_desc fpga012s = XILINX_XC7Z012S_DESC(0x12);
  25 static xilinx_desc fpga014s = XILINX_XC7Z014S_DESC(0x14);
  26 static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
  27 static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
  28 static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
  29 static xilinx_desc fpga035 = XILINX_XC7Z035_DESC(0x35);
  30 static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
  31 static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
  32 #endif
  33
  34 int board_init(void)
  35 {
  36 #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
  37     (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
  38         u32 idcode;
  39
  40         idcode = zynq_slcr_get_idcode();
  41
  42         switch (idcode) {
  43         case XILINX_ZYNQ_7007S:
  44                 fpga = fpga007s;
  45                 break;
  46         case XILINX_ZYNQ_7010:
  47                 fpga = fpga010;
  48                 break;
  49         case XILINX_ZYNQ_7012S:
  50                 fpga = fpga012s;
  51                 break;
  52         case XILINX_ZYNQ_7014S:
  53                 fpga = fpga014s;
  54                 break;
  55         case XILINX_ZYNQ_7015:
  56                 fpga = fpga015;
  57                 break;
  58         case XILINX_ZYNQ_7020:
  59                 fpga = fpga020;
  60                 break;
  61         case XILINX_ZYNQ_7030:
  62                 fpga = fpga030;
  63                 break;
  64         case XILINX_ZYNQ_7035:
  65                 fpga = fpga035;
  66                 break;
  67         case XILINX_ZYNQ_7045:
  68                 fpga = fpga045;
  69                 break;
  70         case XILINX_ZYNQ_7100:
  71                 fpga = fpga100;
  72                 break;
  73         }
  74 #endif
  75
  76 #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
  77     (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
  78         fpga_init();
  79         fpga_add(fpga_xilinx, &fpga);
  80 #endif
  81
  82         return 0;
  83 }
  84
  85 int board_late_init(void)
  86 {
  87         switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
  88         case ZYNQ_BM_NOR:
  89                 setenv("modeboot", "norboot");
  90                 break;
  91         case ZYNQ_BM_SD:
  92                 setenv("modeboot", "sdboot");
  93                 break;
  94         case ZYNQ_BM_JTAG:
  95                 setenv("modeboot", "jtagboot");
  96                 break;
  97         default:
  98                 setenv("modeboot", "");
  99                 break;
 100         }
 101
 102         return 0;
 103 }
 104
 105 #ifdef CONFIG_DISPLAY_BOARDINFO
 106 int checkboard(void)
 107 {
 108         puts("Board: Xilinx Zynq\n");
 109         return 0;
 110 }
 111 #endif
 112
 113 int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
 114 {
 115 #if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
 116     defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET)
 117         if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
 118                         CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
 119                         ethaddr, 6))
 120                 printf("I2C EEPROM MAC address read failed\n");
 121 #endif
 122
 123         return 0;
 124 }
 125
 126 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
 127 /*
 128  * fdt_get_reg - Fill buffer by information from DT
 129  */
 130 static phys_size_t fdt_get_reg(const void *fdt, int nodeoffset, void *buf,
 131                                const u32 *cell, int n)
 132 {
 133         int i = 0, b, banks;
 134         int parent_offset = fdt_parent_offset(fdt, nodeoffset);
 135         int address_cells = fdt_address_cells(fdt, parent_offset);
 136         int size_cells = fdt_size_cells(fdt, parent_offset);
 137         char *p = buf;
 138         u64 val;
 139         u64 vals;
 140
 141         debug("%s: addr_cells=%x, size_cell=%x, buf=%p, cell=%p\n",
 142               __func__, address_cells, size_cells, buf, cell);
 143
 144         /* Check memory bank setup */
 145         banks = n % (address_cells + size_cells);
 146         if (banks)
 147                 panic("Incorrect memory setup cells=%d, ac=%d, sc=%d\n",
 148                       n, address_cells, size_cells);
 149
 150         banks = n / (address_cells + size_cells);
 151
 152         for (b = 0; b < banks; b++) {
 153                 debug("%s: Bank #%d:\n", __func__, b);
 154                 if (address_cells == 2) {
 155                         val = cell[i + 1];
 156                         val <<= 32;
 157                         val |= cell[i];
 158                         val = fdt64_to_cpu(val);
 159                         debug("%s: addr64=%llx, ptr=%p, cell=%p\n",
 160                               __func__, val, p, &cell[i]);
 161                         *(phys_addr_t *)p = val;
 162                 } else {
 163                         debug("%s: addr32=%x, ptr=%p\n",
 164                               __func__, fdt32_to_cpu(cell[i]), p);
 165                         *(phys_addr_t *)p = fdt32_to_cpu(cell[i]);
 166                 }
 167                 p += sizeof(phys_addr_t);
 168                 i += address_cells;
 169
 170                 debug("%s: pa=%p, i=%x, size=%zu\n", __func__, p, i,
 171                       sizeof(phys_addr_t));
 172
 173                 if (size_cells == 2) {
 174                         vals = cell[i + 1];
 175                         vals <<= 32;
 176                         vals |= cell[i];
 177                         vals = fdt64_to_cpu(vals);
 178
 179                         debug("%s: size64=%llx, ptr=%p, cell=%p\n",
 180                               __func__, vals, p, &cell[i]);
 181                         *(phys_size_t *)p = vals;
 182                 } else {
 183                         debug("%s: size32=%x, ptr=%p\n",
 184                               __func__, fdt32_to_cpu(cell[i]), p);
 185                         *(phys_size_t *)p = fdt32_to_cpu(cell[i]);
 186                 }
 187                 p += sizeof(phys_size_t);
 188                 i += size_cells;
 189
 190                 debug("%s: ps=%p, i=%x, size=%zu\n",
 191                       __func__, p, i, sizeof(phys_size_t));
 192         }
 193
 194         /* Return the first address size */
 195         return *(phys_size_t *)((char *)buf + sizeof(phys_addr_t));
 196 }
 197
 198 #define FDT_REG_SIZE  sizeof(u32)
 199 /* Temp location for sharing data for storing */
 200 /* Up to 64-bit address + 64-bit size */
 201 static u8 tmp[CONFIG_NR_DRAM_BANKS * 16];
 202
 203 void dram_init_banksize(void)
 204 {
 205         int bank;
 206
 207         memcpy(&gd->bd->bi_dram[0], &tmp, sizeof(tmp));
 208
 209         for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
 210                 debug("Bank #%d: start %llx\n", bank,
 211                       (unsigned long long)gd->bd->bi_dram[bank].start);
 212                 debug("Bank #%d: size %llx\n", bank,
 213                       (unsigned long long)gd->bd->bi_dram[bank].size);
 214         }
 215 }
 216
 217 int dram_init(void)
 218 {
 219         int node, len;
 220         const void *blob = gd->fdt_blob;
 221         const u32 *cell;
 222
 223         memset(&tmp, 0, sizeof(tmp));
 224
 225         /* find or create "/memory" node. */
 226         node = fdt_subnode_offset(blob, 0, "memory");
 227         if (node < 0) {
 228                 printf("%s: Can't get memory node\n", __func__);
 229                 return node;
 230         }
 231
 232         /* Get pointer to cells and lenght of it */
 233         cell = fdt_getprop(blob, node, "reg", &len);
 234         if (!cell) {
 235                 printf("%s: Can't get reg property\n", __func__);
 236                 return -1;
 237         }
 238
 239         gd->ram_size = fdt_get_reg(blob, node, &tmp, cell, len / FDT_REG_SIZE);
 240
 241         debug("%s: Initial DRAM size %llx\n", __func__, (u64)gd->ram_size);
 242
 243         zynq_ddrc_init();
 244
 245         return 0;
 246 }
 247 #else
 248 int dram_init(void)
 249 {
 250         gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
 251
 252         zynq_ddrc_init();
 253
 254         return 0;
 255 }
 256 #endif