2 * (C) Copyright 2014 - 2015 Xilinx, Inc.
3 * Michal Simek <michal.simek@xilinx.com>
5 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/hardware.h>
13 #include <asm/arch/sys_proto.h>
16 DECLARE_GLOBAL_DATA_PTR;
23 int board_early_init_r(void)
27 val = readl(&crlapb_base->timestamp_ref_ctrl);
28 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
29 writel(val, &crlapb_base->timestamp_ref_ctrl);
31 /* Program freq register in System counter and enable system counter */
32 writel(gd->cpu_clk, &iou_scntr->base_frequency_id_register);
33 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG |
34 ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
35 &iou_scntr->counter_control_register);
42 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
52 void reset_cpu(ulong addr)
56 #ifdef CONFIG_SCSI_AHCI_PLAT
59 ahci_init((void __iomem *)ZYNQMP_SATA_BASEADDR);
64 int board_eth_init(bd_t *bis)
68 #if defined(CONFIG_ZYNQ_GEM)
69 # if defined(CONFIG_ZYNQ_GEM0)
70 ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0,
71 CONFIG_ZYNQ_GEM_PHY_ADDR0, 0);
73 # if defined(CONFIG_ZYNQ_GEM1)
74 ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1,
75 CONFIG_ZYNQ_GEM_PHY_ADDR1, 0);
77 # if defined(CONFIG_ZYNQ_GEM2)
78 ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR2,
79 CONFIG_ZYNQ_GEM_PHY_ADDR2, 0);
81 # if defined(CONFIG_ZYNQ_GEM3)
82 ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR3,
83 CONFIG_ZYNQ_GEM_PHY_ADDR3, 0);
90 int board_mmc_init(bd_t *bd)
94 u32 ver = zynqmp_get_silicon_version();
96 if (ver != ZYNQMP_CSU_VERSION_VELOCE) {
97 #if defined(CONFIG_ZYNQ_SDHCI)
98 # if defined(CONFIG_ZYNQ_SDHCI0)
99 ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0);
101 # if defined(CONFIG_ZYNQ_SDHCI1)
102 ret |= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1);
111 int board_late_init(void)
116 reg = readl(&crlapb_base->boot_mode);
117 bootmode = reg & BOOT_MODES_MASK;
122 setenv("modeboot", "sdboot");
125 printf("Invalid Boot Mode:0x%x\n", bootmode);