3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
7 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
8 * Alex Zuepke <azu@sysgo.de>
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
37 /* read co-processor 15, register #1 (control register) */
38 static unsigned long read_p15_c1(void)
43 "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n"
47 /* printf("p15/c1 is = %08lx\n", value); */
51 /* write to co-processor 15, register #1 (control register) */
52 static void write_p15_c1(unsigned long value)
54 /* printf("write %08lx to p15/c1\n", value); */
56 "mcr p15, 0, %0, c1, c0, 0 @ write it back\n"
64 static void cp_delay (void)
68 /* copro seems to need some delay between reading and writing */
69 for (i = 0; i < 100; i++);
72 /* See also ARM Ref. Man. */
73 #define C1_MMU (1<<0) /* mmu off/on */
74 #define C1_ALIGN (1<<1) /* alignment faults off/on */
75 #define C1_IDC (1<<2) /* icache and/or dcache off/on */
76 #define C1_WRITE_BUFFER (1<<3) /* write buffer off/on */
77 #define C1_BIG_ENDIAN (1<<7) /* big endian off/on */
78 #define C1_SYS_PROT (1<<8) /* system protection */
79 #define C1_ROM_PROT (1<<9) /* ROM protection */
80 #define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */
85 * setup up stacks if necessary
88 DECLARE_GLOBAL_DATA_PTR;
90 IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
91 FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
96 int cleanup_before_linux (void)
99 * this function is called just before we call linux
100 * it prepares the processor for linux
102 * we turn off caches etc ...
103 * and we set the CPU-speed to 73 MHz - see start.S for details
108 disable_interrupts ();
112 /* turn off I-cache */
113 asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
115 asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
118 asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
120 #ifdef CONFIG_ARM7_REVD
121 /* go to high speed */
122 IO_SYSCON3 = (IO_SYSCON3 & ~CLKCTL) | CLKCTL_73;
127 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
129 extern void reset_cpu (ulong addr);
131 disable_interrupts ();
137 void icache_enable (void)
141 reg = read_p15_c1 ();
143 write_p15_c1 (reg | C1_IDC);
146 void icache_disable (void)
150 reg = read_p15_c1 ();
152 write_p15_c1 (reg & ~C1_IDC);
155 int icache_status (void)
157 return (read_p15_c1 () & C1_IDC) != 0;
160 void dcache_enable (void)
164 reg = read_p15_c1 ();
166 write_p15_c1 (reg | C1_IDC);
169 void dcache_disable (void)
173 reg = read_p15_c1 ();
175 write_p15_c1 (reg & ~C1_IDC);
178 int dcache_status (void)
180 return (read_p15_c1 () & C1_IDC) != 0;