3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
7 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
8 * Alex Zuepke <azu@sysgo.de>
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #include <asm/proc-armv/ptrace.h>
34 #include <asm/arch/netarm_registers.h>
37 extern void reset_cpu(ulong addr);
40 /* we always count down the max. */
41 #define TIMER_LOAD_VAL 0xffff
42 /* macro to read the 16 bit timer */
43 #define READ_TIMER (IO_TC1D & 0xffff)
45 #define IRQEN (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_INTR_ENABLE))
46 #define TM2CTRL (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_CONTROL))
47 #define TM2STAT (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_STATUS))
48 #define TIMER_LOAD_VAL NETARM_GEN_TSTAT_CTC_MASK
49 #define READ_TIMER (TM2STAT & NETARM_GEN_TSTAT_CTC_MASK)
53 /* enable IRQ/FIQ interrupts */
54 void enable_interrupts (void)
57 __asm__ __volatile__("mrs %0, cpsr\n"
67 * disable IRQ/FIQ interrupts
68 * returns true if interrupts had been enabled before we disabled them
70 int disable_interrupts (void)
72 unsigned long old,temp;
73 __asm__ __volatile__("mrs %0, cpsr\n"
76 : "=r" (old), "=r" (temp)
79 return (old & 0x80) == 0;
82 void enable_interrupts (void)
86 int disable_interrupts (void)
95 panic ("Resetting CPU ...\n");
99 void show_regs (struct pt_regs *regs)
102 const char *processor_modes[] =
103 { "USER_26", "FIQ_26", "IRQ_26", "SVC_26", "UK4_26", "UK5_26",
105 "UK8_26", "UK9_26", "UK10_26", "UK11_26", "UK12_26", "UK13_26",
106 "UK14_26", "UK15_26",
107 "USER_32", "FIQ_32", "IRQ_32", "SVC_32", "UK4_32", "UK5_32",
109 "UK8_32", "UK9_32", "UK10_32", "UND_32", "UK12_32", "UK13_32",
113 flags = condition_codes (regs);
115 printf ("pc : [<%08lx>] lr : [<%08lx>]\n"
116 "sp : %08lx ip : %08lx fp : %08lx\n",
117 instruction_pointer (regs),
118 regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
119 printf ("r10: %08lx r9 : %08lx r8 : %08lx\n",
120 regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
121 printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n",
122 regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
123 printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n",
124 regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
125 printf ("Flags: %c%c%c%c",
126 flags & CC_N_BIT ? 'N' : 'n',
127 flags & CC_Z_BIT ? 'Z' : 'z',
128 flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v');
129 printf (" IRQs %s FIQs %s Mode %s%s\n",
130 interrupts_enabled (regs) ? "on" : "off",
131 fast_interrupts_enabled (regs) ? "on" : "off",
132 processor_modes[processor_mode (regs)],
133 thumb_mode (regs) ? " (T)" : "");
136 void do_undefined_instruction (struct pt_regs *pt_regs)
138 printf ("undefined instruction\n");
143 void do_software_interrupt (struct pt_regs *pt_regs)
145 printf ("software interrupt\n");
150 void do_prefetch_abort (struct pt_regs *pt_regs)
152 printf ("prefetch abort\n");
157 void do_data_abort (struct pt_regs *pt_regs)
159 printf ("data abort\n");
164 void do_not_used (struct pt_regs *pt_regs)
166 printf ("not used\n");
171 void do_fiq (struct pt_regs *pt_regs)
173 printf ("fast interrupt request\n");
178 void do_irq (struct pt_regs *pt_regs)
180 printf ("interrupt request\n");
185 static ulong timestamp;
186 static ulong lastdec;
188 int interrupt_init (void)
191 /* disable all interrupts */
194 /* operate timer 2 in non-prescale mode */
195 TM2CTRL = ( NETARM_GEN_TIMER_SET_HZ(CFG_HZ) |
196 NETARM_GEN_TCTL_ENABLE |
197 NETARM_GEN_TCTL_INIT_COUNT(TIMER_LOAD_VAL));
199 /* set timer 2 counter */
200 lastdec = TIMER_LOAD_VAL;
202 /* disable all interrupts */
205 /* operate timer 1 in prescale mode */
206 IO_SYSCON1 |= SYSCON1_TC1M;
208 /* select 2kHz clock source for timer 1 */
209 IO_SYSCON1 &= ~SYSCON1_TC1S;
211 /* set timer 1 counter */
212 lastdec = IO_TC1D = TIMER_LOAD_VAL;
220 * timer without interrupts
223 void reset_timer (void)
225 reset_timer_masked ();
228 ulong get_timer (ulong base)
230 return get_timer_masked () - base;
233 void set_timer (ulong t)
238 void udelay (unsigned long usec)
246 tmo += get_timer (0);
248 while (get_timer_masked () < tmo)
252 void reset_timer_masked (void)
255 lastdec = READ_TIMER;
259 ulong get_timer_masked (void)
261 ulong now = READ_TIMER;
263 if (lastdec >= now) {
265 timestamp += lastdec - now;
267 /* we have an overflow ... */
268 timestamp += lastdec + TIMER_LOAD_VAL - now;
275 void udelay_masked (unsigned long usec)
283 reset_timer_masked ();
285 while (get_timer_masked () < tmo)