2 * armboot - Startup Code for ARM720 CPU-core
4 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
5 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 *************************************************************************
34 * Jump vector table as in table 3.1 in [1]
36 *************************************************************************
42 ldr pc, _undefined_instruction
43 ldr pc, _software_interrupt
44 ldr pc, _prefetch_abort
50 _undefined_instruction: .word undefined_instruction
51 _software_interrupt: .word software_interrupt
52 _prefetch_abort: .word prefetch_abort
53 _data_abort: .word data_abort
54 _not_used: .word not_used
58 .balignl 16,0xdeadbeef
62 *************************************************************************
64 * Startup Code (reset vector)
66 * do important init only if we don't start from memory!
67 * relocate armboot to ram
69 * jump to second stage
71 *************************************************************************
82 * Note: _armboot_end_data and _armboot_end are defined
83 * by the (board-dependent) linker script.
84 * _armboot_end_data is the first usable FLASH address after armboot
86 .globl _armboot_end_data
88 .word armboot_end_data
94 * _armboot_real_end is the first usable RAM address behind armboot
95 * and the various stacks
97 .globl _armboot_real_end
101 #ifdef CONFIG_USE_IRQ
102 /* IRQ stack memory (calculated at run-time) */
103 .globl IRQ_STACK_START
107 /* IRQ stack memory (calculated at run-time) */
108 .globl FIQ_STACK_START
115 * the actual reset code
120 * set the cpu to SVC32 mode
128 * we do sys-critical inits only at reboot,
129 * not when booting from ram!
131 #ifdef CONFIG_INIT_CRITICAL
137 * relocate armboot to RAM
139 adr r0, _start /* r0 <- current position of code */
140 ldr r2, _armboot_start
142 sub r2, r3, r2 /* r2 <- size of armboot */
143 ldr r1, _TEXT_BASE /* r1 <- destination address */
144 add r2, r0, r2 /* r2 <- source end address */
147 * r0 = source address
148 * r1 = target address
149 * r2 = source end address
157 /* set up the stack */
159 add r0, r0, #CONFIG_STACKSIZE
160 sub sp, r0, #12 /* leave 3 words for abort-stack */
162 ldr pc, _start_armboot
164 _start_armboot: .word start_armboot
168 *************************************************************************
170 * CPU_init_critical registers
172 * setup important registers
173 * setup memory timing
175 *************************************************************************
179 /* Interupt-Controller base addresses */
180 INTMR1: .word 0x80000280 @ 32 bit size
181 INTMR2: .word 0x80001280 @ 16 bit size
182 INTMR3: .word 0x80002280 @ 8 bit size
185 SYSCON1: .word 0x80000100
186 SYSCON2: .word 0x80001100
187 SYSCON3: .word 0x80002200
189 #define CLKCTL 0x6 /* mask */
190 #define CLKCTL_18 0x0 /* 18.432 MHz */
191 #define CLKCTL_36 0x2 /* 36.864 MHz */
192 #define CLKCTL_49 0x4 /* 49.152 MHz */
193 #define CLKCTL_73 0x6 /* 73.728 MHz */
197 * mask all IRQs by clearing all bits in the INTMRs
208 * flush v4 I/D caches
211 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
212 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
215 * disable MMU stuff and caches
218 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
219 bic r0, r0, #0x0000008f @ clear bits 7, 3:0 (B--- WCAM)
220 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
223 #ifdef CONFIG_ARM7_REVD
224 /* set clock speed */
225 /* !!! we run @ 36 MHz due to a hardware flaw in Rev. D processors */
226 /* !!! not doing DRAM refresh properly! */
230 orr r1, r1, #CLKCTL_36
235 * before relocating, we have to setup RAM timing
236 * because memory timing is board-dependend, you will
237 * find a memsetup.S in your board directory.
247 *************************************************************************
251 *************************************************************************
257 #define S_FRAME_SIZE 72
279 #define MODE_SVC 0x13
283 * use bad_save_user_regs for abort/prefetch/undef/swi ...
284 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
287 .macro bad_save_user_regs
288 sub sp, sp, #S_FRAME_SIZE
289 stmia sp, {r0 - r12} @ Calling r0-r12
293 add r2, r2, #CONFIG_STACKSIZE
295 ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
296 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
300 stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r
304 .macro irq_save_user_regs
305 sub sp, sp, #S_FRAME_SIZE
306 stmia sp, {r0 - r12} @ Calling r0-r12
308 stmdb r8, {sp, lr}^ @ Calling SP, LR
309 str lr, [r8, #0] @ Save calling PC
311 str r6, [r8, #4] @ Save CPSR
312 str r0, [r8, #8] @ Save OLD_R0
316 .macro irq_restore_user_regs
317 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
319 ldr lr, [sp, #S_PC] @ Get PC
320 add sp, sp, #S_FRAME_SIZE
321 subs pc, lr, #4 @ return & move spsr_svc into cpsr
325 ldr r13, _armboot_end @ setup our mode stack
326 add r13, r13, #CONFIG_STACKSIZE @ resides at top of normal stack
329 str lr, [r13] @ save caller lr / spsr
333 mov r13, #MODE_SVC @ prepare SVC-Mode
339 .macro get_irq_stack @ setup IRQ stack
340 ldr sp, IRQ_STACK_START
343 .macro get_fiq_stack @ setup FIQ stack
344 ldr sp, FIQ_STACK_START
351 undefined_instruction:
354 bl do_undefined_instruction
360 bl do_software_interrupt
380 #ifdef CONFIG_USE_IRQ
387 irq_restore_user_regs
392 /* someone ought to write a more effiction fiq_save_user_regs */
395 irq_restore_user_regs
417 mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
418 mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
419 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
420 bic ip, ip, #0x000f @ ............wcam
421 bic ip, ip, #0x2100 @ ..v....s........
422 mcr p15, 0, ip, c1, c0, 0 @ ctrl register