3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
7 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
8 * Alex Zuepke <azu@sysgo.de>
11 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
13 * See file CREDITS for list of people who contributed to this
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #if defined(CONFIG_S3C2400) || \
34 defined(CONFIG_S3C2410) || \
39 #if defined(CONFIG_S3C2400)
41 #elif defined(CONFIG_S3C2410)
45 int timer_load_val = 0;
46 static ulong timer_clk;
48 /* macro to read the 16 bit timer */
49 static inline ulong READ_TIMER(void)
51 struct s3c24x0_timers *timers = s3c24x0_get_base_timers();
53 return readl(&timers->TCNTO4) & 0xffff;
56 static ulong timestamp;
61 struct s3c24x0_timers *timers = s3c24x0_get_base_timers();
64 /* use PWM Timer 4 because it has no output */
65 /* prescaler for Timer 4 is 16 */
66 writel(0x0f00, &timers->TCFG0);
67 if (timer_load_val == 0) {
69 * for 10 ms clock period @ PCLK with 4 bit divider = 1/2
70 * (default) and prescaler = 16. Should be 10390
71 * @33.25MHz and 15625 @ 50 MHz
73 timer_load_val = get_PCLK() / (2 * 16 * 100);
74 timer_clk = get_PCLK() / (2 * 16);
76 /* load value for 10 ms timeout */
77 lastdec = timer_load_val;
78 writel(timer_load_val, &timers->TCNTB4);
79 /* auto load, manual update of Timer 4 */
80 tmr = (readl(&timers->TCON) & ~0x0700000) | 0x0600000;
81 writel(tmr, &timers->TCON);
82 /* auto load, start Timer 4 */
83 tmr = (tmr & ~0x0700000) | 0x0500000;
84 writel(tmr, &timers->TCON);
91 * timer without interrupts
94 void reset_timer(void)
99 ulong get_timer(ulong base)
101 return get_timer_masked() - base;
104 void set_timer(ulong t)
109 void udelay(unsigned long usec)
112 ulong start = get_ticks();
115 tmo *= (timer_load_val * 100);
118 while ((ulong) (get_ticks() - start) < tmo)
122 void reset_timer_masked(void)
125 lastdec = READ_TIMER();
129 ulong get_timer_masked(void)
131 ulong tmr = get_ticks();
133 return tmr / (timer_clk / CONFIG_SYS_HZ);
136 void udelay_masked(unsigned long usec)
144 tmo *= (timer_load_val * 100);
147 tmo = usec * (timer_load_val * 100);
148 tmo /= (1000 * 1000);
151 endtime = get_ticks() + tmo;
154 ulong now = get_ticks();
155 diff = endtime - now;
160 * This function is derived from PowerPC code (read timebase as long long).
161 * On ARM it just returns the timer value.
163 unsigned long long get_ticks(void)
165 ulong now = READ_TIMER();
167 if (lastdec >= now) {
169 timestamp += lastdec - now;
171 /* we have an overflow ... */
172 timestamp += lastdec + timer_load_val - now;
180 * This function is derived from PowerPC code (timebase clock frequency).
181 * On ARM it returns the number of timer ticks per second.
183 ulong get_tbclk(void)
187 #if defined(CONFIG_SMDK2400) || defined(CONFIG_TRAB)
188 tbclk = timer_load_val * 100;
189 #elif defined(CONFIG_SBC2410X) || \
190 defined(CONFIG_SMDK2410) || \
191 defined(CONFIG_VCMA9)
192 tbclk = CONFIG_SYS_HZ;
194 # error "tbclk not configured"
201 * reset the cpu by setting up the watchdog timer and let him time out
203 void reset_cpu(ulong ignored)
205 struct s3c24x0_watchdog *watchdog;
208 extern void disable_vfd(void);
213 watchdog = s3c24x0_get_base_watchdog();
215 /* Disable watchdog */
216 writel(0x0000, &watchdog->WTCON);
218 /* Initialize watchdog timer count register */
219 writel(0x0001, &watchdog->WTCNT);
221 /* Enable watchdog timer; assert reset at timer timeout */
222 writel(0x0021, &watchdog->WTCON);
225 /* loop forever and wait for reset to happen */;
230 #endif /* defined(CONFIG_S3C2400) ||
231 defined (CONFIG_S3C2410) ||
232 defined (CONFIG_TRAB) */