3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
7 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
8 * Alex Zuepke <azu@sysgo.de>
11 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
13 * See file CREDITS for list of people who contributed to this
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB)
35 #if defined(CONFIG_S3C2400)
37 #elif defined(CONFIG_S3C2410)
41 int timer_load_val = 0;
42 static ulong timer_clk;
44 /* macro to read the 16 bit timer */
45 static inline ulong READ_TIMER(void)
47 S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS();
49 return (timers->TCNTO4 & 0xffff);
52 static ulong timestamp;
57 S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS();
59 /* use PWM Timer 4 because it has no output */
60 /* prescaler for Timer 4 is 16 */
61 timers->TCFG0 = 0x0f00;
62 if (timer_load_val == 0)
65 * for 10 ms clock period @ PCLK with 4 bit divider = 1/2
66 * (default) and prescaler = 16. Should be 10390
67 * @33.25MHz and 15625 @ 50 MHz
69 timer_load_val = get_PCLK()/(2 * 16 * 100);
70 timer_clk = get_PCLK() / (2 * 16);
72 /* load value for 10 ms timeout */
73 lastdec = timers->TCNTB4 = timer_load_val;
74 /* auto load, manual update of Timer 4 */
75 timers->TCON = (timers->TCON & ~0x0700000) | 0x600000;
76 /* auto load, start Timer 4 */
77 timers->TCON = (timers->TCON & ~0x0700000) | 0x500000;
84 * timer without interrupts
87 void reset_timer (void)
89 reset_timer_masked ();
92 ulong get_timer (ulong base)
94 return get_timer_masked () - base;
97 void set_timer (ulong t)
102 void udelay (unsigned long usec)
105 ulong start = get_ticks();
108 tmo *= (timer_load_val * 100);
111 while ((ulong) (get_ticks() - start) < tmo)
115 void reset_timer_masked (void)
118 lastdec = READ_TIMER();
122 ulong get_timer_masked (void)
124 ulong tmr = get_ticks();
126 return tmr / (timer_clk / CONFIG_SYS_HZ);
129 void udelay_masked (unsigned long usec)
137 tmo *= (timer_load_val * 100);
140 tmo = usec * (timer_load_val * 100);
144 endtime = get_ticks() + tmo;
147 ulong now = get_ticks();
148 diff = endtime - now;
153 * This function is derived from PowerPC code (read timebase as long long).
154 * On ARM it just returns the timer value.
156 unsigned long long get_ticks(void)
158 ulong now = READ_TIMER();
160 if (lastdec >= now) {
162 timestamp += lastdec - now;
164 /* we have an overflow ... */
165 timestamp += lastdec + timer_load_val - now;
173 * This function is derived from PowerPC code (timebase clock frequency).
174 * On ARM it returns the number of timer ticks per second.
176 ulong get_tbclk (void)
180 #if defined(CONFIG_SMDK2400) || defined(CONFIG_TRAB)
181 tbclk = timer_load_val * 100;
182 #elif defined(CONFIG_SBC2410X) || \
183 defined(CONFIG_SMDK2410) || \
184 defined(CONFIG_VCMA9)
185 tbclk = CONFIG_SYS_HZ;
187 # error "tbclk not configured"
194 * reset the cpu by setting up the watchdog timer and let him time out
196 void reset_cpu (ulong ignored)
198 volatile S3C24X0_WATCHDOG * watchdog;
201 extern void disable_vfd (void);
206 watchdog = S3C24X0_GetBase_WATCHDOG();
208 /* Disable watchdog */
209 watchdog->WTCON = 0x0000;
211 /* Initialize watchdog timer count register */
212 watchdog->WTCNT = 0x0001;
214 /* Enable watchdog timer; assert reset at timer timeout */
215 watchdog->WTCON = 0x0021;
217 while(1); /* loop forever and wait for reset to happen */
222 #endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */