2 * armboot - Startup Code for ARM920 CPU-core
4 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
5 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
6 * Copyright (c) 2002 Gary Jennejohn <gj@denx.de>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 *************************************************************************
36 * Jump vector table as in table 3.1 in [1]
38 *************************************************************************
44 ldr pc, _undefined_instruction
45 ldr pc, _software_interrupt
46 ldr pc, _prefetch_abort
52 _undefined_instruction: .word undefined_instruction
53 _software_interrupt: .word software_interrupt
54 _prefetch_abort: .word prefetch_abort
55 _data_abort: .word data_abort
56 _not_used: .word not_used
60 .balignl 16,0xdeadbeef
64 *************************************************************************
66 * Startup Code (reset vector)
68 * do important init only if we don't start from memory!
69 * relocate armboot to ram
71 * jump to second stage
73 *************************************************************************
77 * CFG_MEM_END is in the board dependent config-file (configs/config_BOARD.h)
87 * Note: _armboot_end_data and _armboot_end are defined
88 * by the (board-dependent) linker script.
89 * _armboot_end_data is the first usable FLASH address after armboot
91 .globl _armboot_end_data
93 .word armboot_end_data
99 * _armboot_real_end is the first usable RAM address behind armboot
100 * and the various stacks
102 .globl _armboot_real_end
106 #ifdef CONFIG_USE_IRQ
107 /* IRQ stack memory (calculated at run-time) */
108 .globl IRQ_STACK_START
112 /* IRQ stack memory (calculated at run-time) */
113 .globl FIQ_STACK_START
120 * the actual reset code
125 * set the cpu to SVC32 mode
132 /* turn off the watchdog */
133 #if defined(CONFIG_S3C2400)
134 #define pWTCON 0x15300000
135 /* Interupt-Controller base addresses */
136 #define INTMSK 0x14400008
137 /* clock divisor register */
138 #define CLKDIVN 0x14800014
139 #elif defined(CONFIG_S3C2410)
140 #define pWTCON 0x53000000
141 /* Interupt-Controller base addresses */
142 #define INTMSK 0x4A000008
143 #define INTSUBMSK 0x4A00001C
144 /* clock divisor register */
145 #define CLKDIVN 0x4C000014
153 * mask all IRQs by setting all bits in the INTMR - default
158 #if defined(CONFIG_S3C2410)
164 /* FCLK:HCLK:PCLK = 1:2:4 */
165 /* default FCLK is 120 MHz ! */
171 * we do sys-critical inits only at reboot,
172 * not when booting from ram!
174 #ifdef CONFIG_INIT_CRITICAL
180 * relocate armboot to RAM
182 adr r0, _start /* r0 <- current position of code */
183 ldr r2, _armboot_start
185 sub r2, r3, r2 /* r2 <- size of armboot */
186 ldr r1, _TEXT_BASE /* r1 <- destination address */
187 add r2, r0, r2 /* r2 <- source end address */
190 * r0 = source address
191 * r1 = target address
192 * r2 = source end address
201 /* try doing this stuff after the relocation */
207 * mask all IRQs by setting all bits in the INTMR - default
213 /* FCLK:HCLK:PCLK = 1:2:4 */
214 /* default FCLK is 120 MHz ! */
218 /* END stuff after relocation */
221 /* set up the stack */
223 add r0, r0, #CONFIG_STACKSIZE
224 sub sp, r0, #12 /* leave 3 words for abort-stack */
226 ldr pc, _start_armboot
228 _start_armboot: .word start_armboot
232 *************************************************************************
234 * CPU_init_critical registers
236 * setup important registers
237 * setup memory timing
239 *************************************************************************
245 * flush v4 I/D caches
248 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
249 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
252 * disable MMU stuff and caches
254 mrc p15, 0, r0, c1, c0, 0
255 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
256 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
257 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
258 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
259 mcr p15, 0, r0, c1, c0, 0
263 * before relocating, we have to setup RAM timing
264 * because memory timing is board-dependend, you will
265 * find a memsetup.S in your board directory.
277 *************************************************************************
281 *************************************************************************
287 #define S_FRAME_SIZE 72
309 #define MODE_SVC 0x13
313 * use bad_save_user_regs for abort/prefetch/undef/swi ...
314 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
317 .macro bad_save_user_regs
318 sub sp, sp, #S_FRAME_SIZE
319 stmia sp, {r0 - r12} @ Calling r0-r12
323 add r2, r2, #CONFIG_STACKSIZE
325 ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
326 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
330 stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r
334 .macro irq_save_user_regs
335 sub sp, sp, #S_FRAME_SIZE
336 stmia sp, {r0 - r12} @ Calling r0-r12
338 stmdb r8, {sp, lr}^ @ Calling SP, LR
339 str lr, [r8, #0] @ Save calling PC
341 str r6, [r8, #4] @ Save CPSR
342 str r0, [r8, #8] @ Save OLD_R0
346 .macro irq_restore_user_regs
347 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
349 ldr lr, [sp, #S_PC] @ Get PC
350 add sp, sp, #S_FRAME_SIZE
351 subs pc, lr, #4 @ return & move spsr_svc into cpsr
355 ldr r13, _armboot_end @ setup our mode stack
356 add r13, r13, #CONFIG_STACKSIZE @ resides at top of normal stack
359 str lr, [r13] @ save caller lr / spsr
363 mov r13, #MODE_SVC @ prepare SVC-Mode
370 .macro get_irq_stack @ setup IRQ stack
371 ldr sp, IRQ_STACK_START
374 .macro get_fiq_stack @ setup FIQ stack
375 ldr sp, FIQ_STACK_START
382 undefined_instruction:
385 bl do_undefined_instruction
391 bl do_software_interrupt
411 #ifdef CONFIG_USE_IRQ
418 irq_restore_user_regs
423 /* someone ought to write a more effiction fiq_save_user_regs */
426 irq_restore_user_regs
447 #ifdef CONFIG_S3C2400
448 bl disable_interrupts
454 /* Disable watchdog */
457 /* Initialize watchdog timer count register */
460 /* Enable watchdog timer; assert reset at timer timeout */
469 #else /* ! CONFIG_S3C2400 */
471 mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
472 mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
473 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
474 bic ip, ip, #0x000f @ ............wcam
475 bic ip, ip, #0x2100 @ ..v....s........
476 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
478 #endif /* CONFIG_S3C2400 */