2 * (C) Copyright 2009 DENX Software Engineering
3 * Author: John Rigby <jrigby@gmail.com>
5 * Based on mx27/generic.c:
6 * Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org>
7 * Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/arch/imx-regs.h>
30 #include <asm/arch/imx25-pinmux.h>
32 #include <asm/arch/mxcmmc.h>
36 * get the system pll clock in Hz
38 * mfi + mfn / (mfd +1)
39 * f = 2 * f_ref * --------------------
42 static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
44 unsigned int mfi = (pll >> CCM_PLL_MFI_SHIFT)
46 unsigned int mfn = (pll >> CCM_PLL_MFN_SHIFT)
48 unsigned int mfd = (pll >> CCM_PLL_MFD_SHIFT)
50 unsigned int pd = (pll >> CCM_PLL_PD_SHIFT)
53 mfi = mfi <= 5 ? 5 : mfi;
55 return lldiv(2 * (u64)f_ref * (mfi * (mfd + 1) + mfn),
56 (mfd + 1) * (pd + 1));
59 static ulong imx_get_mpllclk(void)
61 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
62 ulong fref = 24000000;
64 return imx_decode_pll(readl(&ccm->mpctl), fref);
67 ulong imx_get_armclk(void)
69 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
70 ulong cctl = readl(&ccm->cctl);
71 ulong fref = imx_get_mpllclk();
74 if (cctl & CCM_CCTL_ARM_SRC)
75 fref = lldiv((fref * 3), 4);
77 div = ((cctl >> CCM_CCTL_ARM_DIV_SHIFT)
78 & CCM_CCTL_ARM_DIV_MASK) + 1;
80 return lldiv(fref, div);
83 ulong imx_get_ahbclk(void)
85 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
86 ulong cctl = readl(&ccm->cctl);
87 ulong fref = imx_get_armclk();
90 div = ((cctl >> CCM_CCTL_AHB_DIV_SHIFT)
91 & CCM_CCTL_AHB_DIV_MASK) + 1;
93 return lldiv(fref, div);
96 ulong imx_get_perclk(int clk)
98 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
99 ulong fref = imx_get_ahbclk();
102 div = readl(&ccm->pcdr[CCM_PERCLK_REG(clk)]);
103 div = ((div >> CCM_PERCLK_SHIFT(clk)) & CCM_PERCLK_MASK) + 1;
105 return lldiv(fref, div);
108 #if defined(CONFIG_DISPLAY_CPUINFO)
109 int print_cpuinfo (void)
113 printf("CPU: Freescale i.MX25 at %s MHz\n\n",
114 strmhz(buf, imx_get_mpllclk()));
119 int cpu_eth_init(bd_t *bis)
121 #if defined(CONFIG_FEC_MXC)
122 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
125 val = readl(&ccm->cgr0);
127 writel(val, &ccm->cgr0);
128 return fecmxc_initialize(bis);
135 * Initializes on-chip MMC controllers.
136 * to override, implement board_mmc_init()
138 int cpu_mmc_init(bd_t *bis)
140 #ifdef CONFIG_MXC_MMC
141 return mxc_mmc_init(bis);
147 #ifdef CONFIG_MXC_UART
148 void mx25_uart_init_pins(void)
150 struct iomuxc_mux_ctl *muxctl;
151 struct iomuxc_pad_ctl *padctl;
156 muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
157 padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
158 muxmode0 = MX25_PIN_MUX_MODE(0);
160 * set up input pins with hysteresis and 100K pull-ups
162 inpadctl = MX25_PIN_PAD_CTL_HYS
163 | MX25_PIN_PAD_CTL_PKE
164 | MX25_PIN_PAD_CTL_PUE
165 | MX25_PIN_PAD_CTL_100K_PU;
168 * set up output pins with 100K pull-downs
169 * FIXME: need to revisit this
170 * PUE is ignored if PKE is not set
171 * so the right value here is likely
172 * 0x0 for no pull up/down
174 * 0xc0 for 100k pull down
176 outpadctl = MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD;
180 writel(muxmode0, &muxctl->pad_uart1_rxd);
181 writel(inpadctl, &padctl->pad_uart1_rxd);
184 writel(muxmode0, &muxctl->pad_uart1_txd);
185 writel(outpadctl, &padctl->pad_uart1_txd);
188 writel(muxmode0, &muxctl->pad_uart1_rts);
189 writel(outpadctl, &padctl->pad_uart1_rts);
192 writel(muxmode0, &muxctl->pad_uart1_cts);
193 writel(inpadctl, &padctl->pad_uart1_cts);
195 #endif /* CONFIG_MXC_UART */
197 #ifdef CONFIG_FEC_MXC
198 void mx25_fec_init_pins(void)
200 struct iomuxc_mux_ctl *muxctl;
201 struct iomuxc_pad_ctl *padctl;
207 muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
208 padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
209 muxmode0 = MX25_PIN_MUX_MODE(0);
210 inpadctl_100kpd = MX25_PIN_PAD_CTL_HYS
211 | MX25_PIN_PAD_CTL_PKE
212 | MX25_PIN_PAD_CTL_PUE
213 | MX25_PIN_PAD_CTL_100K_PD;
214 inpadctl_22kpu = MX25_PIN_PAD_CTL_HYS
215 | MX25_PIN_PAD_CTL_PKE
216 | MX25_PIN_PAD_CTL_PUE
217 | MX25_PIN_PAD_CTL_22K_PU;
219 * set up output pins with 100K pull-downs
220 * FIXME: need to revisit this
221 * PUE is ignored if PKE is not set
222 * so the right value here is likely
225 * 0xc0 for 100k pull down
227 outpadctl = MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD;
230 writel(muxmode0, &muxctl->pad_fec_tx_clk);
231 writel(inpadctl_100kpd, &padctl->pad_fec_tx_clk); // 0x1c0
234 writel(muxmode0, &muxctl->pad_fec_rx_dv);
235 writel(inpadctl_100kpd, &padctl->pad_fec_rx_dv); // 0xc0
238 writel(muxmode0, &muxctl->pad_fec_rdata0);
239 writel(inpadctl_100kpd, &padctl->pad_fec_rdata0); // 0xc0
242 writel(muxmode0, &muxctl->pad_fec_tdata0);
243 writel(outpadctl, &padctl->pad_fec_tdata0); // 0x40
246 writel(muxmode0, &muxctl->pad_fec_tx_en);
247 writel(outpadctl, &padctl->pad_fec_tx_en); // 0x40
250 writel(muxmode0, &muxctl->pad_fec_mdc);
251 writel(outpadctl, &padctl->pad_fec_mdc); // 0x40
254 writel(muxmode0, &muxctl->pad_fec_mdio);
255 writel(inpadctl_22kpu, &padctl->pad_fec_mdio); // 0x1f0
258 writel(muxmode0, &muxctl->pad_fec_rdata1);
259 writel(inpadctl_100kpd, &padctl->pad_fec_rdata1); // 0xc0
262 writel(muxmode0, &muxctl->pad_fec_tdata1);
263 writel(outpadctl, &padctl->pad_fec_tdata1); // 0x40
266 #endif /* CONFIG_FEC_MXC */