2 * Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org>
3 * Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/arch/imx-regs.h>
27 * get the system pll clock in Hz
29 * mfi + mfn / (mfd +1)
30 * f = 2 * f_ref * --------------------
33 unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
35 unsigned int mfi = (pll >> 10) & 0xf;
36 unsigned int mfn = pll & 0x3ff;
37 unsigned int mfd = (pll >> 16) & 0x3ff;
38 unsigned int pd = (pll >> 26) & 0xf;
40 mfi = mfi <= 5 ? 5 : mfi;
42 return lldiv(2 * (u64)f_ref * (mfi * (mfd + 1) + mfn),
43 (mfd + 1) * (pd + 1));
46 static ulong clk_in_32k(void)
48 return 1024 * CONFIG_MX27_CLK32;
51 static ulong clk_in_26m(void)
53 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
55 if (readl(&pll->cscr) & CSCR_OSC26M_DIV1P5) {
57 return 26000000 * 2 / 3;
63 ulong imx_get_mpllclk(void)
65 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
66 ulong cscr = readl(&pll->cscr);
69 if (cscr & CSCR_MCU_SEL)
74 return imx_decode_pll(readl(&pll->mpctl0), fref);
77 ulong imx_get_armclk(void)
79 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
80 ulong cscr = readl(&pll->cscr);
81 ulong fref = imx_get_mpllclk();
84 if (!(cscr & CSCR_ARM_SRC_MPLL))
85 fref = lldiv((fref * 2), 3);
87 div = ((cscr >> 12) & 0x3) + 1;
89 return lldiv(fref, div);
92 ulong imx_get_ahbclk(void)
94 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
95 ulong cscr = readl(&pll->cscr);
96 ulong fref = imx_get_mpllclk();
99 div = ((cscr >> 8) & 0x3) + 1;
101 return lldiv(fref * 2, 3 * div);
104 ulong imx_get_spllclk(void)
106 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
107 ulong cscr = readl(&pll->cscr);
110 if (cscr & CSCR_SP_SEL)
115 return imx_decode_pll(readl(&pll->spctl0), fref);
118 static ulong imx_decode_perclk(ulong div)
120 return lldiv((imx_get_mpllclk() * 2), (div * 3));
123 ulong imx_get_perclk1(void)
125 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
127 return imx_decode_perclk((readl(&pll->pcdr1) & 0x3f) + 1);
130 ulong imx_get_perclk2(void)
132 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
134 return imx_decode_perclk(((readl(&pll->pcdr1) >> 8) & 0x3f) + 1);
137 ulong imx_get_perclk3(void)
139 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
141 return imx_decode_perclk(((readl(&pll->pcdr1) >> 16) & 0x3f) + 1);
144 ulong imx_get_perclk4(void)
146 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
148 return imx_decode_perclk(((readl(&pll->pcdr1) >> 24) & 0x3f) + 1);
151 #if defined(CONFIG_DISPLAY_CPUINFO)
152 int print_cpuinfo (void)
156 printf("CPU: Freescale i.MX27 at %s MHz\n\n",
157 strmhz(buf, imx_get_mpllclk()));
162 void imx_gpio_mode(int gpio_mode)
164 struct gpio_regs *regs = (struct gpio_regs *)IMX_GPIO_BASE;
165 unsigned int pin = gpio_mode & GPIO_PIN_MASK;
166 unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
167 unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT;
168 unsigned int aout = (gpio_mode & GPIO_AOUT_MASK) >> GPIO_AOUT_SHIFT;
169 unsigned int bout = (gpio_mode & GPIO_BOUT_MASK) >> GPIO_BOUT_SHIFT;
173 if (gpio_mode & GPIO_PUEN) {
174 writel(readl(®s->port[port].puen) | (1 << pin),
175 ®s->port[port].puen);
177 writel(readl(®s->port[port].puen) & ~(1 << pin),
178 ®s->port[port].puen);
182 if (gpio_mode & GPIO_OUT) {
183 writel(readl(®s->port[port].ddir) | 1 << pin,
184 ®s->port[port].ddir);
186 writel(readl(®s->port[port].ddir) & ~(1 << pin),
187 ®s->port[port].ddir);
190 /* Primary / alternate function */
191 if (gpio_mode & GPIO_AF) {
192 writel(readl(®s->port[port].gpr) | (1 << pin),
193 ®s->port[port].gpr);
195 writel(readl(®s->port[port].gpr) & ~(1 << pin),
196 ®s->port[port].gpr);
200 if (!(gpio_mode & (GPIO_PF | GPIO_AF))) {
201 writel(readl(®s->port[port].gius) | (1 << pin),
202 ®s->port[port].gius);
204 writel(readl(®s->port[port].gius) & ~(1 << pin),
205 ®s->port[port].gius);
208 /* Output / input configuration */
210 tmp = readl(®s->port[port].ocr1);
211 tmp &= ~(3 << (pin * 2));
212 tmp |= (ocr << (pin * 2));
213 writel(tmp, ®s->port[port].ocr1);
215 writel(readl(®s->port[port].iconfa1) & ~(3 << (pin * 2)),
216 ®s->port[port].iconfa1);
217 writel(readl(®s->port[port].iconfa1) | aout << (pin * 2),
218 ®s->port[port].iconfa1);
219 writel(readl(®s->port[port].iconfb1) & ~(3 << (pin * 2)),
220 ®s->port[port].iconfb1);
221 writel(readl(®s->port[port].iconfb1) | bout << (pin * 2),
222 ®s->port[port].iconfb1);
226 tmp = readl(®s->port[port].ocr2);
227 tmp &= ~(3 << (pin * 2));
228 tmp |= (ocr << (pin * 2));
229 writel(tmp, ®s->port[port].ocr2);
231 writel(readl(®s->port[port].iconfa2) & ~(3 << (pin * 2)),
232 ®s->port[port].iconfa2);
233 writel(readl(®s->port[port].iconfa2) | aout << (pin * 2),
234 ®s->port[port].iconfa2);
235 writel(readl(®s->port[port].iconfb2) & ~(3 << (pin * 2)),
236 ®s->port[port].iconfb2);
237 writel(readl(®s->port[port].iconfb2) | bout << (pin * 2),
238 ®s->port[port].iconfb2);