3 * Texas Instruments, <www.ti.com>
6 * Manikandan Pillai <mani.pillai@ti.com>
8 * Derived from Beagle Board and OMAP3 SDP code by
9 * Richard Woodruff <r-woodruff2@ti.com>
10 * Syed Mohammed Khasim <khasim@ti.com>
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/arch/clocks.h>
31 #include <asm/arch/clocks_omap3.h>
32 #include <asm/arch/mem.h>
33 #include <asm/arch/sys_proto.h>
34 #include <environment.h>
37 /******************************************************************************
38 * get_sys_clk_speed() - determine reference oscillator speed
39 * based on known 32kHz clock and gptimer.
40 *****************************************************************************/
41 u32 get_osc_clk_speed(void)
43 u32 start, cstart, cend, cdiff, val;
44 prcm_t *prcm_base = (prcm_t *)PRCM_BASE;
45 prm_t *prm_base = (prm_t *)PRM_BASE;
46 gptimer_t *gpt1_base = (gptimer_t *)OMAP34XX_GPT1;
47 s32ktimer_t *s32k_base = (s32ktimer_t *)SYNC_32KTIMER_BASE;
49 val = readl(&prm_base->clksrc_ctrl);
51 /* If SYS_CLK is being divided by 2, remove for now */
52 val = (val & (~SYSCLKDIV_2)) | SYSCLKDIV_1;
53 writel(val, &prm_base->clksrc_ctrl);
56 val = readl(&prcm_base->clksel_wkup) | CLKSEL_GPT1;
58 /* select sys_clk for GPT1 */
59 writel(val, &prcm_base->clksel_wkup);
61 /* Enable I and F Clocks for GPT1 */
62 val = readl(&prcm_base->iclken_wkup) | EN_GPT1 | EN_32KSYNC;
63 writel(val, &prcm_base->iclken_wkup);
64 val = readl(&prcm_base->fclken_wkup) | EN_GPT1;
65 writel(val, &prcm_base->fclken_wkup);
67 writel(0, &gpt1_base->tldr); /* start counting at 0 */
68 writel(GPT_EN, &gpt1_base->tclr); /* enable clock */
70 /* enable 32kHz source, determine sys_clk via gauging */
72 /* start time in 20 cycles */
73 start = 20 + readl(&s32k_base->s32k_cr);
75 /* dead loop till start time */
76 while (readl(&s32k_base->s32k_cr) < start);
78 /* get start sys_clk count */
79 cstart = readl(&gpt1_base->tcrr);
81 /* wait for 40 cycles */
82 while (readl(&s32k_base->s32k_cr) < (start + 20)) ;
83 cend = readl(&gpt1_base->tcrr); /* get end sys_clk count */
84 cdiff = cend - cstart; /* get elapsed ticks */
86 /* based on number of ticks assign speed */
89 else if (cdiff > 15200)
91 else if (cdiff > 13000)
93 else if (cdiff > 9000)
95 else if (cdiff > 7600)
101 /******************************************************************************
102 * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on
103 * input oscillator clock frequency.
104 *****************************************************************************/
105 void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel)
126 /******************************************************************************
127 * prcm_init() - inits clocks for PRCM as defined in clocks.h
128 * called from SRAM, or Flash (using temp SRAM stack).
129 *****************************************************************************/
132 void (*f_lock_pll) (u32, u32, u32, u32);
133 int xip_safe, p0, p1, p2, p3;
134 u32 osc_clk = 0, sys_clkin_sel;
135 u32 clk_index, sil_index;
136 prm_t *prm_base = (prm_t *)PRM_BASE;
137 prcm_t *prcm_base = (prcm_t *)PRCM_BASE;
138 dpll_param *dpll_param_p;
140 f_lock_pll = (void *) ((u32) &_end_vect - (u32) &_start +
143 xip_safe = is_running_in_sram();
146 * Gauge the input clock speed and find out the sys_clkin_sel
147 * value corresponding to the input clock.
149 osc_clk = get_osc_clk_speed();
150 get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
152 /* set input crystal speed */
153 sr32(&prm_base->clksel, 0, 3, sys_clkin_sel);
155 /* If the input clock is greater than 19.2M always divide/2 */
156 if (sys_clkin_sel > 2) {
157 /* input clock divider */
158 sr32(&prm_base->clksrc_ctrl, 6, 2, 2);
159 clk_index = sys_clkin_sel / 2;
161 /* input clock divider */
162 sr32(&prm_base->clksrc_ctrl, 6, 2, 1);
163 clk_index = sys_clkin_sel;
167 * The DPLL tables are defined according to sysclk value and
168 * silicon revision. The clk_index value will be used to get
169 * the values for that input sysclk from the DPLL param table
170 * and sil_index will get the values for that SysClk for the
171 * appropriate silicon rev.
173 sil_index = get_cpu_rev() - 1;
175 /* Unlock MPU DPLL (slows things down, and needed later) */
176 sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS);
177 wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu, LDELAY);
179 /* Getting the base address of Core DPLL param table */
180 dpll_param_p = (dpll_param *) get_core_dpll_param();
182 /* Moving it to the right sysclk and ES rev base */
183 dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
187 * sr32(CM_CLKSEL2_EMU) set override to work when asleep
189 sr32(&prcm_base->clken_pll, 0, 3, PLL_FAST_RELOCK_BYPASS);
190 wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen,
194 * For OMAP3 ES1.0 Errata 1.50, default value directly doesn't
195 * work. write another value and then default value.
199 sr32(&prcm_base->clksel1_emu, 16, 5, CORE_M3X2 + 1);
201 sr32(&prcm_base->clksel1_emu, 16, 5, CORE_M3X2);
203 sr32(&prcm_base->clksel1_pll, 27, 2, dpll_param_p->m2);
205 sr32(&prcm_base->clksel1_pll, 16, 11, dpll_param_p->m);
207 sr32(&prcm_base->clksel1_pll, 8, 7, dpll_param_p->n);
209 sr32(&prcm_base->clksel1_pll, 6, 1, 0);
211 sr32(&prcm_base->clksel_core, 8, 4, CORE_SSI_DIV);
213 sr32(&prcm_base->clksel_core, 4, 2, CORE_FUSB_DIV);
215 sr32(&prcm_base->clksel_core, 2, 2, CORE_L4_DIV);
217 sr32(&prcm_base->clksel_core, 0, 2, CORE_L3_DIV);
219 sr32(&prcm_base->clksel_gfx, 0, 3, GFX_DIV);
221 sr32(&prcm_base->clksel_wkup, 1, 2, WKUP_RSM);
223 sr32(&prcm_base->clken_pll, 4, 4, dpll_param_p->fsel);
225 sr32(&prcm_base->clken_pll, 0, 3, PLL_LOCK);
227 wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen,
229 } else if (is_running_in_flash()) {
231 * if running from flash, jump to small relocated code
234 p0 = readl(&prcm_base->clken_pll);
235 sr32(&p0, 0, 3, PLL_FAST_RELOCK_BYPASS);
236 sr32(&p0, 4, 4, dpll_param_p->fsel); /* FREQSEL */
238 p1 = readl(&prcm_base->clksel1_pll);
239 sr32(&p1, 27, 2, dpll_param_p->m2); /* Set M2 */
240 sr32(&p1, 16, 11, dpll_param_p->m); /* Set M */
241 sr32(&p1, 8, 7, dpll_param_p->n); /* Set N */
242 sr32(&p1, 6, 1, 0); /* set source for 96M */
244 p2 = readl(&prcm_base->clksel_core);
245 sr32(&p2, 8, 4, CORE_SSI_DIV); /* ssi */
246 sr32(&p2, 4, 2, CORE_FUSB_DIV); /* fsusb */
247 sr32(&p2, 2, 2, CORE_L4_DIV); /* l4 */
248 sr32(&p2, 0, 2, CORE_L3_DIV); /* l3 */
250 p3 = (u32)&prcm_base->idlest_ckgen;
252 (*f_lock_pll) (p0, p1, p2, p3);
256 sr32(&prcm_base->clken_pll, 16, 3, PLL_STOP);
257 wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);
259 /* Getting the base address to PER DPLL param table */
262 dpll_param_p = (dpll_param *) get_per_dpll_param();
264 /* Moving it to the right sysclk base */
265 dpll_param_p = dpll_param_p + clk_index;
268 * Errata 1.50 Workaround for OMAP3 ES1.0 only
269 * If using default divisors, write default divisor + 1
270 * and then the actual divisor value
272 sr32(&prcm_base->clksel1_emu, 24, 5, PER_M6X2 + 1); /* set M6 */
273 sr32(&prcm_base->clksel1_emu, 24, 5, PER_M6X2); /* set M6 */
274 sr32(&prcm_base->clksel_cam, 0, 5, PER_M5X2 + 1); /* set M5 */
275 sr32(&prcm_base->clksel_cam, 0, 5, PER_M5X2); /* set M5 */
276 sr32(&prcm_base->clksel_dss, 0, 5, PER_M4X2 + 1); /* set M4 */
277 sr32(&prcm_base->clksel_dss, 0, 5, PER_M4X2); /* set M4 */
278 sr32(&prcm_base->clksel_dss, 8, 5, PER_M3X2 + 1); /* set M3 */
279 sr32(&prcm_base->clksel_dss, 8, 5, PER_M3X2); /* set M3 */
280 sr32(&prcm_base->clksel3_pll, 0, 5, dpll_param_p->m2 + 1); /* set M2 */
281 sr32(&prcm_base->clksel3_pll, 0, 5, dpll_param_p->m2); /* set M2 */
284 sr32(&prcm_base->clksel2_pll, 8, 11, dpll_param_p->m); /* set m */
285 sr32(&prcm_base->clksel2_pll, 0, 7, dpll_param_p->n); /* set n */
286 sr32(&prcm_base->clken_pll, 20, 4, dpll_param_p->fsel); /* FREQSEL */
287 sr32(&prcm_base->clken_pll, 16, 3, PLL_LOCK); /* lock mode */
288 wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
290 /* Getting the base address to MPU DPLL param table */
291 dpll_param_p = (dpll_param *) get_mpu_dpll_param();
293 /* Moving it to the right sysclk and ES rev base */
294 dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
296 /* MPU DPLL (unlocked already) */
299 sr32(&prcm_base->clksel2_pll_mpu, 0, 5, dpll_param_p->m2);
301 sr32(&prcm_base->clksel1_pll_mpu, 8, 11, dpll_param_p->m);
303 sr32(&prcm_base->clksel1_pll_mpu, 0, 7, dpll_param_p->n);
305 sr32(&prcm_base->clken_pll_mpu, 4, 4, dpll_param_p->fsel);
307 sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOCK);
308 wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu, LDELAY);
310 /* Getting the base address to IVA DPLL param table */
311 dpll_param_p = (dpll_param *) get_iva_dpll_param();
313 /* Moving it to the right sysclk and ES rev base */
314 dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
316 /* IVA DPLL (set to 12*20=240MHz) */
317 sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_STOP);
318 wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY);
320 sr32(&prcm_base->clksel2_pll_iva2, 0, 5, dpll_param_p->m2);
322 sr32(&prcm_base->clksel1_pll_iva2, 8, 11, dpll_param_p->m);
324 sr32(&prcm_base->clksel1_pll_iva2, 0, 7, dpll_param_p->n);
326 sr32(&prcm_base->clken_pll_iva2, 4, 4, dpll_param_p->fsel);
328 sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_LOCK);
329 wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY);
331 /* Set up GPTimers to sys_clk source only */
332 sr32(&prcm_base->clksel_per, 0, 8, 0xff);
333 sr32(&prcm_base->clksel_wkup, 0, 1, 1);
338 /******************************************************************************
339 * peripheral_enable() - Enable the clks & power for perifs (GPT2, UART1,...)
340 *****************************************************************************/
341 void per_clocks_enable(void)
343 prcm_t *prcm_base = (prcm_t *)PRCM_BASE;
345 /* Enable GP2 timer. */
346 sr32(&prcm_base->clksel_per, 0, 1, 0x1); /* GPT2 = sys clk */
347 sr32(&prcm_base->iclken_per, 3, 1, 0x1); /* ICKen GPT2 */
348 sr32(&prcm_base->fclken_per, 3, 1, 0x1); /* FCKen GPT2 */
350 #ifdef CONFIG_SYS_NS16550
351 /* Enable UART1 clocks */
352 sr32(&prcm_base->fclken1_core, 13, 1, 0x1);
353 sr32(&prcm_base->iclken1_core, 13, 1, 0x1);
356 sr32(&prcm_base->fclken_per, 11, 1, 0x1);
357 sr32(&prcm_base->iclken_per, 11, 1, 0x1);
359 #ifdef CONFIG_DRIVER_OMAP34XX_I2C
360 /* Turn on all 3 I2C clocks */
361 sr32(&prcm_base->fclken1_core, 15, 3, 0x7);
362 sr32(&prcm_base->iclken1_core, 15, 3, 0x7); /* I2C1,2,3 = on */
364 /* Enable the ICLK for 32K Sync Timer as its used in udelay */
365 sr32(&prcm_base->iclken_wkup, 2, 1, 0x1);
367 sr32(&prcm_base->fclken_iva2, 0, 32, FCK_IVA2_ON);
368 sr32(&prcm_base->fclken1_core, 0, 32, FCK_CORE1_ON);
369 sr32(&prcm_base->iclken1_core, 0, 32, ICK_CORE1_ON);
370 sr32(&prcm_base->iclken2_core, 0, 32, ICK_CORE2_ON);
371 sr32(&prcm_base->fclken_wkup, 0, 32, FCK_WKUP_ON);
372 sr32(&prcm_base->iclken_wkup, 0, 32, ICK_WKUP_ON);
373 sr32(&prcm_base->fclken_dss, 0, 32, FCK_DSS_ON);
374 sr32(&prcm_base->iclken_dss, 0, 32, ICK_DSS_ON);
375 sr32(&prcm_base->fclken_cam, 0, 32, FCK_CAM_ON);
376 sr32(&prcm_base->iclken_cam, 0, 32, ICK_CAM_ON);
377 sr32(&prcm_base->fclken_per, 0, 32, FCK_PER_ON);
378 sr32(&prcm_base->iclken_per, 0, 32, ICK_PER_ON);