3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
7 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
8 * Alex Zuepke <azu@sysgo.de>
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
36 #include <asm/arch/hardware.h>
38 #if !defined(CONFIG_DBGU) && !defined(CONFIG_USART0) && !defined(CONFIG_USART1)
39 #error must define one of CONFIG_DBGU or CONFIG_USART0 or CONFIG_USART1
42 /* read co-processor 15, register #1 (control register) */
43 static unsigned long read_p15_c1(void)
48 "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n"
52 /*printf("p15/c1 is = %08lx\n", value); */
56 /* write to co-processor 15, register #1 (control register) */
57 static void write_p15_c1(unsigned long value)
59 /*printf("write %08lx to p15/c1\n", value); */
61 "mcr p15, 0, %0, c1, c0, 0 @ write it back\n"
69 static void cp_delay(void)
73 /* copro seems to need some delay between reading and writing */
74 for (i=0; i<100; i++);
76 /* See also ARM Ref. Man. */
77 #define C1_MMU (1<<0) /* mmu off/on */
78 #define C1_ALIGN (1<<1) /* alignment faults off/on */
79 #define C1_IDC (1<<2) /* icache and/or dcache off/on */
80 #define C1_WRITE_BUFFER (1<<3) /* write buffer off/on */
81 #define C1_BIG_ENDIAN (1<<7) /* big endian off/on */
82 #define C1_SYS_PROT (1<<8) /* system protection */
83 #define C1_ROM_PROT (1<<9) /* ROM protection */
84 #define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */
89 * setup up stacks if necessary
92 DECLARE_GLOBAL_DATA_PTR;
94 IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
95 FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
100 int cleanup_before_linux(void)
103 * this function is called just before we call linux
104 * it prepares the processor for linux
106 * we turn off caches etc ...
107 * and we set the CPU-speed to 73 MHz - see start.S for details
110 disable_interrupts();
114 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
117 #ifdef CFG_SOFT_RESET
118 extern void reset_cpu(ulong addr);
120 disable_interrupts();
124 AT91PS_USART us = (AT91PS_USART) AT91C_BASE_DBGU;
127 AT91PS_USART us = AT91C_BASE_US0;
130 AT91PS_USART us = AT91C_BASE_US1;
132 AT91PS_PIO pio = AT91C_BASE_PIOA;
134 /*shutdown the console to avoid strange chars during reset */
135 us->US_CR = (AT91C_US_RSTRX | AT91C_US_RSTTX);
137 #ifdef CONFIG_AT91RM9200DK
138 /* Clear PA19 to trigger the hard reset */
139 pio->PIO_CODR = 0x00080000;
140 pio->PIO_OER = 0x00080000;
141 pio->PIO_PER = 0x00080000;
143 #ifdef CONFIG_CMC_PU2
144 /* this is the way Linux does it */
145 #define AT91C_ST_RSTEN (0x1 << 16)
146 #define AT91C_ST_EXTEN (0x1 << 17)
147 #define AT91C_ST_WDRST (0x1 << 0)
148 /* watchdog mode register */
149 #define ST_WDMR *((unsigned long *)0xfffffd08)
150 /* system clock control register */
151 #define ST_CR *((unsigned long *)0xfffffd00)
152 ST_WDMR = AT91C_ST_RSTEN | AT91C_ST_EXTEN | 1 ;
153 ST_CR = AT91C_ST_WDRST;
160 void icache_enable(void)
165 write_p15_c1(reg | C1_IDC);
168 void icache_disable(void)
173 write_p15_c1(reg & ~C1_IDC);
176 int icache_status(void)
178 return (read_p15_c1() & C1_IDC) != 0;
182 void dcache_enable(void)
187 write_p15_c1(reg | C1_IDC);
190 void dcache_disable(void)
195 write_p15_c1(reg & ~C1_IDC);
198 int dcache_status(void)
200 return (read_p15_c1() & C1_IDC) != 0;