2 #include <asm/linkage.h>
4 #include <asm/blackfin.h>
5 #include <asm/mach-common/bits/mpu.h>
9 ENTRY(_blackfin_icache_flush_range)
23 ENTRY(_blackfin_dcache_flush_range)
37 ENTRY(_icache_invalidate)
38 ENTRY(_invalidate_entire_icache)
41 P0.L = (IMEM_CONTROL & 0xFFFF);
42 P0.H = (IMEM_CONTROL >> 16);
46 * Clear the IMC bit , All valid bits in the instruction
47 * cache are set to the invalid state
51 /* SSYNC required before invalidating cache. */
58 /* Configures the instruction cache agian */
73 * Invalidate the Entire Data cache by
74 * clearing DMC[1:0] bits
76 ENTRY(_invalidate_entire_dcache)
77 ENTRY(_dcache_invalidate)
80 P0.L = (DMEM_CONTROL & 0xFFFF);
81 P0.H = (DMEM_CONTROL >> 16);
85 * Clear the DMC[1:0] bits, All valid bits in the data
86 * cache are set to the invalid state
96 /* Configures the data cache again */
98 R6 = (ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
111 ENTRY(_blackfin_dcache_invalidate_range)
123 * If the data crosses a cache line, then we'll be pointing to
124 * the last cache line, but won't have flushed/invalidated it yet, so do