2 * armboot - Startup Code for ARM920 CPU-core
4 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
5 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
6 * Copyright (c) 2002 Gary Jennejohn <gj@denx.de>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 *************************************************************************
35 * Jump vector table as in table 3.1 in [1]
37 *************************************************************************
43 ldr pc, _undefined_instruction
44 ldr pc, _software_interrupt
45 ldr pc, _prefetch_abort
51 _undefined_instruction: .word undefined_instruction
52 _software_interrupt: .word software_interrupt
53 _prefetch_abort: .word prefetch_abort
54 _data_abort: .word data_abort
55 _not_used: .word not_used
59 .balignl 16,0xdeadbeef
63 *************************************************************************
65 * Startup Code (reset vector)
67 * do important init only if we don't start from memory!
68 * relocate armboot to ram
70 * jump to second stage
72 *************************************************************************
83 * These are defined in the board-specific linker script.
94 /* IRQ stack memory (calculated at run-time) */
95 .globl IRQ_STACK_START
99 /* IRQ stack memory (calculated at run-time) */
100 .globl FIQ_STACK_START
107 * the actual reset code
112 * set the cpu to SVC32 mode
120 * we do sys-critical inits only at reboot,
121 * not when booting from ram!
123 #ifdef CONFIG_INIT_CRITICAL
127 relocate: /* relocate U-Boot to RAM */
128 adr r0, _start /* r0 <- current position of code */
129 ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
130 cmp r0, r1 /* don't reloc during debug */
133 ldr r2, _armboot_start
135 sub r2, r3, r2 /* r2 <- size of armboot */
136 add r2, r0, r2 /* r2 <- source end address */
139 ldmia r0!, {r3-r10} /* copy from source address [r0] */
140 stmia r1!, {r3-r10} /* copy to target address [r1] */
141 cmp r0, r2 /* until source end addreee [r2] */
144 /* Set up the stack */
146 ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
147 sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
148 sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
149 #ifdef CONFIG_USE_IRQ
150 sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
152 sub sp, r0, #12 /* leave 3 words for abort-stack */
155 ldr r0, _bss_start /* find start of bss segment */
156 ldr r1, _bss_end /* stop here */
157 mov r2, #0x00000000 /* clear */
159 clbss_l:str r2, [r0] /* clear loop... */
164 ldr pc, _start_armboot
166 _start_armboot: .word start_armboot
170 *************************************************************************
172 * CPU_init_critical registers
174 * setup important registers
175 * setup memory timing
177 *************************************************************************
183 * flush v4 I/D caches
186 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
187 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
190 * disable MMU stuff and caches
192 mrc p15, 0, r0, c1, c0, 0
193 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
194 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
195 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
196 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
197 mcr p15, 0, r0, c1, c0, 0
201 * before relocating, we have to setup RAM timing
202 * because memory timing is board-dependend, you will
203 * find a memsetup.S in your board directory.
213 *************************************************************************
217 *************************************************************************
223 #define S_FRAME_SIZE 72
245 #define MODE_SVC 0x13
249 * use bad_save_user_regs for abort/prefetch/undef/swi ...
250 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
253 .macro bad_save_user_regs
254 sub sp, sp, #S_FRAME_SIZE
255 stmia sp, {r0 - r12} @ Calling r0-r12
256 ldr r2, _armboot_start
257 sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
258 sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
259 ldmia r2, {r2 - r3} @ get pc, cpsr
260 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
264 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
268 .macro irq_save_user_regs
269 sub sp, sp, #S_FRAME_SIZE
270 stmia sp, {r0 - r12} @ Calling r0-r12
272 stmdb r8, {sp, lr}^ @ Calling SP, LR
273 str lr, [r8, #0] @ Save calling PC
275 str r6, [r8, #4] @ Save CPSR
276 str r0, [r8, #8] @ Save OLD_R0
280 .macro irq_restore_user_regs
281 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
283 ldr lr, [sp, #S_PC] @ Get PC
284 add sp, sp, #S_FRAME_SIZE
285 subs pc, lr, #4 @ return & move spsr_svc into cpsr
289 ldr r13, _armboot_start @ setup our mode stack
290 sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
291 sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
293 str lr, [r13] @ save caller lr / spsr
297 mov r13, #MODE_SVC @ prepare SVC-Mode
304 .macro get_irq_stack @ setup IRQ stack
305 ldr sp, IRQ_STACK_START
308 .macro get_fiq_stack @ setup FIQ stack
309 ldr sp, FIQ_STACK_START
316 undefined_instruction:
319 bl do_undefined_instruction
325 bl do_software_interrupt
345 #ifdef CONFIG_USE_IRQ
352 irq_restore_user_regs
357 /* someone ought to write a more effiction fiq_save_user_regs */
360 irq_restore_user_regs
382 mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
383 mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
384 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
385 bic ip, ip, #0x000f @ ............wcam
386 bic ip, ip, #0x2100 @ ..v....s........
387 mcr p15, 0, ip, c1, c0, 0 @ ctrl register