2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000 - 2003 Wolfgang Denk <wd@denx.de>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * U-Boot - Startup Code for MPC5xxx CPUs
32 #define CONFIG_MPC5XXX 1 /* needed for Linux kernel header files */
33 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
35 #include <ppc_asm.tmpl>
38 #include <asm/cache.h>
41 #ifndef CONFIG_IDENT_STRING
42 #define CONFIG_IDENT_STRING ""
45 /* We don't want the MMU yet.
48 /* Floating Point enable, Machine Check and Recoverable Interr. */
50 #define MSR_KERNEL (MSR_FP|MSR_RI)
52 #define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
56 * Set up GOT: Global Offset Table
58 * Use r14 to access the GOT
61 GOT_ENTRY(_GOT2_TABLE_)
62 GOT_ENTRY(_FIXUP_TABLE_)
65 GOT_ENTRY(_start_of_vectors)
66 GOT_ENTRY(_end_of_vectors)
67 GOT_ENTRY(transfer_to_handler)
71 GOT_ENTRY(__bss_start)
81 .ascii " (", __DATE__, " - ", __TIME__, ")"
82 .ascii CONFIG_IDENT_STRING, "\0"
91 li r21, BOOTFLAG_COLD /* Normal Power-On */
95 . = EXC_OFF_SYS_RESET + 0x10
99 li r21, BOOTFLAG_WARM /* Software reboot */
104 mfmsr r5 /* save msr contents */
106 #if defined(CFG_LOWBOOT)
107 #if defined(CFG_RAMBOOT)
108 #error CFG_LOWBOOT is incompatible with CFG_RAMBOOT
109 #endif /* CFG_RAMBOOT */
110 lis r4, CFG_DEFAULT_MBAR@h
112 ori r3, r3, 0x0000FF00@l
115 ori r3, r3, 0x0000FFFF@l
118 ori r3, r3, 0x00047800@l
121 ori r3, r3, 0x02010000@l
124 lis r3, lowboot_reentry@h
125 ori r3, r3, lowboot_reentry@l
127 blr /* jump to flash based address */
131 ori r3, r3, 0x0000FF00@l
134 ori r3, r3, 0x0000FFFF@l
137 ori r3, r3, 0x00047800@l
140 ori r3, r3, 0x02000001@l
142 #endif /* CFG_LOWBOOT */
144 #if defined(CFG_DEFAULT_MBAR) && !defined(CFG_RAMBOOT)
146 ori r3, r3, CFG_MBAR@l
147 #if defined(CONFIG_MPC5200)
148 rlwinm r3, r3, 16, 16, 31
150 #if defined(CONFIG_MGT5100)
151 rlwinm r3, r3, 17, 15, 31
153 lis r4, CFG_DEFAULT_MBAR@h
155 #endif /* CFG_DEFAULT_MBAR */
157 /* Initialise the MPC5xxx processor core */
158 /*--------------------------------------------------------------*/
162 /* initialize some things that are hard to access from C */
163 /*--------------------------------------------------------------*/
165 /* set up stack in on-chip SRAM */
166 lis r3, CFG_INIT_RAM_ADDR@h
167 ori r3, r3, CFG_INIT_RAM_ADDR@l
168 ori r1, r3, CFG_INIT_SP_OFFSET
169 li r0, 0 /* Make room for stack frame header and */
170 stwu r0, -4(r1) /* clear final stack frame so that */
171 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
173 /* let the C-code set up the rest */
175 /* Be careful to keep code relocatable ! */
176 /*--------------------------------------------------------------*/
178 GET_GOT /* initialize GOT access */
181 bl cpu_init_f /* run low-level CPU init code (in Flash)*/
185 bl board_init_f /* run 1st part of board init code (in Flash)*/
191 .globl _start_of_vectors
195 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
197 /* Data Storage exception. */
198 STD_EXCEPTION(0x300, DataStorage, UnknownException)
200 /* Instruction Storage exception. */
201 STD_EXCEPTION(0x400, InstStorage, UnknownException)
203 /* External Interrupt exception. */
204 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
206 /* Alignment exception. */
214 addi r3,r1,STACK_FRAME_OVERHEAD
216 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
217 rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */
218 lwz r6,GOT(transfer_to_handler)
222 .long AlignmentException - _start + EXC_OFF_SYS_RESET
223 .long int_return - _start + EXC_OFF_SYS_RESET
225 /* Program check exception */
229 addi r3,r1,STACK_FRAME_OVERHEAD
231 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
232 rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */
233 lwz r6,GOT(transfer_to_handler)
237 .long ProgramCheckException - _start + EXC_OFF_SYS_RESET
238 .long int_return - _start + EXC_OFF_SYS_RESET
240 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
242 /* I guess we could implement decrementer, and may have
243 * to someday for timekeeping.
245 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
247 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
248 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
249 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
250 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
252 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
253 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
255 STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
256 STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
257 STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
261 * This exception occurs when the program counter matches the
262 * Instruction Address Breakpoint Register (IABR).
264 * I want the cpu to halt if this occurs so I can hunt around
265 * with the debugger and look at things.
267 * When DEBUG is defined, both machine check enable (in the MSR)
268 * and checkstop reset enable (in the reset mode register) are
269 * turned off and so a checkstop condition will result in the cpu
272 * I force the cpu into a checkstop condition by putting an illegal
273 * instruction here (at least this is the theory).
275 * well - that didnt work, so just do an infinite loop!
279 STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException)
281 STD_EXCEPTION(0x1400, SMI, UnknownException)
283 STD_EXCEPTION(0x1500, Trap_15, UnknownException)
284 STD_EXCEPTION(0x1600, Trap_16, UnknownException)
285 STD_EXCEPTION(0x1700, Trap_17, UnknownException)
286 STD_EXCEPTION(0x1800, Trap_18, UnknownException)
287 STD_EXCEPTION(0x1900, Trap_19, UnknownException)
288 STD_EXCEPTION(0x1a00, Trap_1a, UnknownException)
289 STD_EXCEPTION(0x1b00, Trap_1b, UnknownException)
290 STD_EXCEPTION(0x1c00, Trap_1c, UnknownException)
291 STD_EXCEPTION(0x1d00, Trap_1d, UnknownException)
292 STD_EXCEPTION(0x1e00, Trap_1e, UnknownException)
293 STD_EXCEPTION(0x1f00, Trap_1f, UnknownException)
294 STD_EXCEPTION(0x2000, Trap_20, UnknownException)
295 STD_EXCEPTION(0x2100, Trap_21, UnknownException)
296 STD_EXCEPTION(0x2200, Trap_22, UnknownException)
297 STD_EXCEPTION(0x2300, Trap_23, UnknownException)
298 STD_EXCEPTION(0x2400, Trap_24, UnknownException)
299 STD_EXCEPTION(0x2500, Trap_25, UnknownException)
300 STD_EXCEPTION(0x2600, Trap_26, UnknownException)
301 STD_EXCEPTION(0x2700, Trap_27, UnknownException)
302 STD_EXCEPTION(0x2800, Trap_28, UnknownException)
303 STD_EXCEPTION(0x2900, Trap_29, UnknownException)
304 STD_EXCEPTION(0x2a00, Trap_2a, UnknownException)
305 STD_EXCEPTION(0x2b00, Trap_2b, UnknownException)
306 STD_EXCEPTION(0x2c00, Trap_2c, UnknownException)
307 STD_EXCEPTION(0x2d00, Trap_2d, UnknownException)
308 STD_EXCEPTION(0x2e00, Trap_2e, UnknownException)
309 STD_EXCEPTION(0x2f00, Trap_2f, UnknownException)
312 .globl _end_of_vectors
318 * This code finishes saving the registers to the exception frame
319 * and jumps to the appropriate handler for the exception.
320 * Register r21 is pointer into trap frame, r1 has new stack pointer.
322 .globl transfer_to_handler
333 andi. r24,r23,0x3f00 /* get vector offset */
337 lwz r24,0(r23) /* virtual address of handler */
338 lwz r23,4(r23) /* where to go when done */
343 rfi /* jump to handler, enable MMU */
346 mfmsr r28 /* Disable interrupts */
350 SYNC /* Some chip revs need this... */
365 lwz r2,_NIP(r1) /* Restore environment */
376 * This code initialises the MPC5xxx processor core
377 * (conforms to PowerPC 603e spec)
378 * Note: expects original MSR contents to be in r5.
384 /* Initialize machine status; enable machine check interrupt */
385 /*--------------------------------------------------------------*/
387 li r3, MSR_KERNEL /* Set ME and RI flags */
388 rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */
390 rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */
392 SYNC /* Some chip revs need this... */
395 mtspr SRR1, r3 /* Make SRR1 match MSR */
397 /* Initialize the Hardware Implementation-dependent Registers */
398 /* HID0 also contains cache control */
399 /*--------------------------------------------------------------*/
401 lis r3, CFG_HID0_INIT@h
402 ori r3, r3, CFG_HID0_INIT@l
406 lis r3, CFG_HID0_FINAL@h
407 ori r3, r3, CFG_HID0_FINAL@l
411 /* clear all BAT's */
412 /*--------------------------------------------------------------*/
449 /* invalidate all tlb's */
451 /* From the 603e User Manual: "The 603e provides the ability to */
452 /* invalidate a TLB entry. The TLB Invalidate Entry (tlbie) */
453 /* instruction invalidates the TLB entry indexed by the EA, and */
454 /* operates on both the instruction and data TLBs simultaneously*/
455 /* invalidating four TLB entries (both sets in each TLB). The */
456 /* index corresponds to bits 15-19 of the EA. To invalidate all */
457 /* entries within both TLBs, 32 tlbie instructions should be */
458 /* issued, incrementing this field by one each time." */
460 /* "Note that the tlbia instruction is not implemented on the */
463 /* bits 15-19 correspond to addresses 0x00000000 to 0x0001F000 */
464 /* incrementing by 0x1000 each time. The code below is sort of */
465 /* based on code in "flush_tlbs" from arch/ppc/kernel/head.S */
467 /*--------------------------------------------------------------*/
478 /*--------------------------------------------------------------*/
484 * Note: requires that all cache bits in
485 * HID0 are in the low half word.
492 ori r4, r4, HID0_ILOCK
494 ori r4, r3, HID0_ICFI
496 mtspr HID0, r4 /* sets enable and invalidate, clears lock */
498 mtspr HID0, r3 /* clears invalidate */
501 .globl icache_disable
505 ori r4, r4, HID0_ICE|HID0_ILOCK
507 ori r4, r3, HID0_ICFI
509 mtspr HID0, r4 /* sets invalidate, clears enable and lock */
511 mtspr HID0, r3 /* clears invalidate */
517 rlwinm r3, r3, HID0_ICE_BITPOS + 1, 31, 31
525 ori r4, r4, HID0_DLOCK
529 mtspr HID0, r4 /* sets enable and invalidate, clears lock */
531 mtspr HID0, r3 /* clears invalidate */
534 .globl dcache_disable
538 ori r4, r4, HID0_DCE|HID0_DLOCK
542 mtspr HID0, r4 /* sets invalidate, clears enable and lock */
544 mtspr HID0, r3 /* clears invalidate */
550 rlwinm r3, r3, HID0_DCE_BITPOS + 1, 31, 31
558 /*------------------------------------------------------------------------------*/
561 * void relocate_code (addr_sp, gd, addr_moni)
563 * This "function" does not return, instead it continues in RAM
564 * after relocating the monitor code.
568 * r5 = length in bytes
573 mr r1, r3 /* Set new stack pointer */
574 mr r9, r4 /* Save copy of Global Data pointer */
575 mr r10, r5 /* Save copy of Destination Address */
577 mr r3, r5 /* Destination Address */
578 lis r4, CFG_MONITOR_BASE@h /* Source Address */
579 ori r4, r4, CFG_MONITOR_BASE@l
580 lwz r5, GOT(__init_end)
582 li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
587 * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
593 /* First our own GOT */
595 /* then the one used by the C code */
605 beq cr1,4f /* In place copy is not necessary */
606 beq 7f /* Protect against 0 count */
625 * Now flush the cache: note that we must start from a cache aligned
626 * address. Otherwise we might miss one cache line.
630 beq 7f /* Always flush prefetch queue in any case */
633 mfspr r7,HID0 /* don't do dcbst if dcache is disabled */
634 rlwinm r7,r7,HID0_DCE_BITPOS+1,31,31
642 sync /* Wait for all dcbst to complete on bus */
643 9: mfspr r7,HID0 /* don't do icbi if icache is disabled */
644 rlwinm r7,r7,HID0_ICE_BITPOS+1,31,31
652 7: sync /* Wait for all icbi to complete on bus */
656 * We are done. Do not return, instead branch to second part of board
657 * initialization, now running from RAM.
660 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
667 * Relocation Function, r14 point to got2+0x8000
669 * Adjust got2 pointers, no need to check for 0, this code
670 * already puts a few entries in the table.
672 li r0,__got2_entries@sectoff@l
673 la r3,GOT(_GOT2_TABLE_)
674 lwz r11,GOT(_GOT2_TABLE_)
684 * Now adjust the fixups and the pointers to the fixups
685 * in case we need to move ourselves again.
687 2: li r0,__fixup_entries@sectoff@l
688 lwz r3,GOT(_FIXUP_TABLE_)
702 * Now clear BSS segment
704 lwz r3,GOT(__bss_start)
718 mr r3, r9 /* Global Data pointer */
719 mr r4, r10 /* Destination Address */
723 * Copy exception vector code to low memory
726 * r7: source address, r8: end address, r9: target address
731 lwz r8, GOT(_end_of_vectors)
733 li r9, 0x100 /* reset vector always at 0x100 */
736 bgelr /* return if r7>=r8 - just in case */
738 mflr r4 /* save link register */
748 * relocate `hdlr' and `int_return' entries
750 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
751 li r8, Alignment - _start + EXC_OFF_SYS_RESET
754 addi r7, r7, 0x100 /* next exception vector */
758 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
761 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
764 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
765 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
768 addi r7, r7, 0x100 /* next exception vector */
772 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
773 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
776 addi r7, r7, 0x100 /* next exception vector */
780 mfmsr r3 /* now that the vectors have */
781 lis r7, MSR_IP@h /* relocated into low memory */
782 ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */
783 andc r3, r3, r7 /* (if it was on) */
784 SYNC /* Some chip revs need this... */
788 mtlr r4 /* restore link register */
792 * Function: relocate entries for one exception vector
795 lwz r0, 0(r7) /* hdlr ... */
796 add r0, r0, r3 /* ... += dest_addr */
799 lwz r0, 4(r7) /* int_return ... */
800 add r0, r0, r3 /* ... += dest_addr */