2 * Copyright 2004 Freescale Semiconductor.
3 * Copyright (C) 2003 Motorola Inc.
4 * Xianghua Xiao (x.xiao@motorola.com)
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * 20050101: Eran Liberty (liberty@freescale.com)
27 * Initial file creating (porting from 85XX & 8260)
31 * PCI Configuration space access support for MPC85xx PCI Bridge
38 #ifdef CONFIG_MPC8349ADS
42 #if defined(CONFIG_PCI)
45 pci_mpc83xx_init(volatile struct pci_controller *hose)
47 volatile immap_t * immr;
48 volatile clk8349_t * clk;
49 volatile law8349_t * pci_law;
50 volatile pot8349_t * pci_pot;
51 volatile pcictrl8349_t * pci_ctrl;
52 volatile pciconf8349_t * pci_conf;
58 immr = (immap_t *)CFG_IMMRBAR;
59 clk = (clk8349_t *)&immr->clk;
60 pci_law = immr->sysconf.pcilaw;
61 pci_pot = immr->ios.pot;
62 pci_ctrl = immr->pci_ctrl;
63 pci_conf = immr->pci_conf;
66 * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
70 clk->occr = 0xff000000;
74 * Configure PCI Local Access Windows
76 pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
77 pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
78 pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
79 pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M;
82 * Configure PCI Outbound Translation Windows
84 pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
85 pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
86 pci_pot[0].pocmr = POCMR_EN | (POCMR_CM_512M & POCMR_CM_MASK);
88 /* mapped to PCI1 IO space 0x0 to local 0xe2000000 */
89 pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
90 pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
91 pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK);
92 //#if defined(CONFIG_PCI_2)
93 pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK;
94 pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK;
95 pci_pot[3].pocmr = POCMR_EN | POCMR_DST | (POCMR_CM_512M & POCMR_CM_MASK);
97 /* mapped to PCI2 IO space 0x0 to local 0xe3000000 */
98 pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK;
99 pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK;
100 pci_pot[4].pocmr = POCMR_EN | POCMR_DST | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK);
104 * Configure PCI Inbound Translation Windows
106 pci_ctrl[0].pitar1 = 0x0;
107 pci_ctrl[0].pibar1 = 0x0;
108 pci_ctrl[0].piebar1 = 0x0;
109 pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G;
111 pci_ctrl[1].pitar1 = 0x0;
112 pci_ctrl[1].pibar1 = 0x0;
113 pci_ctrl[1].piebar1 = 0x0;
114 pci_ctrl[1].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G;
116 * Assign PIB PMC slot to desired PCI bus
118 #ifdef CONFIG_MPC8349ADS
119 mpc8349_i2c = (i2c_t*)(CFG_IMMRBAR + CFG_I2C2_OFFSET);
120 i2c_init(CFG_I2C_SPEED,CFG_I2C_SLAVE);
123 ret = i2c_write(0x23,0x6,1,&val8,1);
124 ret = i2c_write(0x23,0x7,1,&val8,1);
126 ret = i2c_write(0x23,0x2,1,&val8,1);
127 ret = i2c_write(0x23,0x3,1,&val8,1);
130 ret = i2c_write(0x26,0x6,1,&val8,1);
132 ret = i2c_write(0x26,0x7,1,&val8,1);
133 #if defined(PCI_64BIT)
134 val8 = 0xf4; // PMC2<->PCI1 64bit
135 #elif defined(PCI_ALL_PCI1)
136 val8 = 0xf3; // PMC1<->PCI1,PMC2<->PCI1,PMC3<->PCI1 32bit
137 #elif defined(PCI_ONE_PCI1)
138 val8 = 0xf9; // PMC1<->PCI1,PMC2<->PCI2,PMC3<->PCI2 32bit
139 #elif defined(PCI_TWO_PCI1)
140 val8 = 0xf5; // PMC1<->PCI1,PMC2<->PCI1,PMC3<->PCI2 32bit
144 ret = i2c_write(0x26,0x2,1,&val8,1);
146 ret = i2c_write(0x26,0x3,1,&val8,1);
148 ret = i2c_write(0x27,0x6,1,&val8,1);
149 ret = i2c_write(0x27,0x7,1,&val8,1);
151 ret = i2c_write(0x27,0x2,1,&val8,1);
153 ret = i2c_write(0x27,0x3,1,&val8,1);
157 * Release PCI RST Output signal
166 hose[0].first_busno = 0;
167 hose[0].last_busno = 0xff;
169 pci_set_region(hose[0].regions + 0,
175 pci_set_region(hose[0].regions + 1,
181 hose[0].region_count = 2;
183 pci_setup_indirect(&hose[0],
184 (CFG_IMMRBAR+0x8300),
185 (CFG_IMMRBAR+0x8304));
186 #define PCI_CLASS_BRIDGE 0x06
189 pci_hose_write_config_byte(&hose[0],PCI_BDF(0,0,0),PCI_CLASS_CODE,PCI_CLASS_BRIDGE);
191 pci_hose_read_config_word (&hose[0],PCI_BDF(0,0,0),PCI_COMMAND, ®16);
192 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
193 pci_hose_write_config_word(&hose[0],PCI_BDF(0,0,0), PCI_COMMAND, reg16);
196 * Clear non-reserved bits in status register.
198 pci_hose_write_config_word(&hose[0],PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
199 pci_hose_write_config_byte(&hose[0],PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80);
201 hose[1].first_busno = 0;
202 hose[1].last_busno = 0xff;
204 pci_set_region(hose[1].regions + 0,
210 pci_set_region(hose[1].regions + 1,
216 hose[1].region_count = 2;
218 pci_setup_indirect(&hose[1],
219 (CFG_IMMRBAR+0x8380),
220 (CFG_IMMRBAR+0x8384));
222 pci_hose_write_config_byte(&hose[1],PCI_BDF(0,0,0),PCI_CLASS_CODE,PCI_CLASS_BRIDGE);
223 pci_hose_read_config_word (&hose[1],PCI_BDF(0,0,0), PCI_COMMAND, ®16);
224 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
225 pci_hose_write_config_word(&hose[1],PCI_BDF(0,0,0), PCI_COMMAND, reg16);
228 * Clear non-reserved bits in status register.
230 pci_hose_write_config_word(&hose[1],PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
231 pci_hose_write_config_byte(&hose[1],PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80);
234 #if defined(PCI_64BIT)
235 printf("PCI1 64bit on PMC2\n");
236 #elif defined(PCI_ALL_PCI1)
237 printf("PCI1 32bit on PMC1 & PMC2 & PMC3\n");
238 #elif defined(PCI_ONE_PCI1)
239 printf("PCI1 32bit on PMC1,PCI2 32bit on PMC2 & PMC3\n");
241 printf("PCI1 32bit on PMC1 & PMC2 & PMC3 in default\n");
248 pci_register_hose(hose);
249 hose->last_busno = pci_hose_scan(hose);
253 #endif /* CONFIG_PCI */