2 * (C) Copyright 2006-2007 Freescale Semiconductor, Inc.
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
8 * (C) Copyright 2003 Motorola Inc.
9 * Xianghua Xiao (X.Xiao@motorola.com)
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/processor.h>
35 #include <spd_sdram.h>
37 DECLARE_GLOBAL_DATA_PTR;
39 void board_add_ram_info(int use_default)
41 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
42 volatile ddr83xx_t *ddr = &immap->ddr;
45 printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK)
46 >> SDRAM_CFG_SDRAM_TYPE_SHIFT) - 1);
48 if (ddr->sdram_cfg & SDRAM_CFG_32_BE)
53 if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
58 printf(", %s MHz)", strmhz(buf, gd->mem_clk));
60 #if defined(CONFIG_SYS_LB_SDRAM) && defined(CONFIG_SYS_LBC_SDRAM_SIZE)
62 print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, " (local bus)");
66 #ifdef CONFIG_SPD_EEPROM
68 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
69 extern void dma_init(void);
70 extern uint dma_check(void);
71 extern int dma_xfer(void *dest, uint count, void *src);
74 #ifndef CONFIG_SYS_READ_SPD
75 #define CONFIG_SYS_READ_SPD i2c_read
79 * Convert picoseconds into clock cycles (rounding up if needed).
82 picos_to_clk(int picos)
84 unsigned int mem_bus_clk;
87 mem_bus_clk = gd->mem_clk >> 1;
88 clks = picos / (1000000000 / (mem_bus_clk / 1000));
89 if (picos % (1000000000 / (mem_bus_clk / 1000)) != 0)
95 unsigned int banksize(unsigned char row_dens)
97 return ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
100 int read_spd(uint addr)
107 static void spd_debug(spd_eeprom_t *spd)
109 printf ("\nDIMM type: %-18.18s\n", spd->mpart);
110 printf ("SPD size: %d\n", spd->info_size);
111 printf ("EEPROM size: %d\n", 1 << spd->chip_size);
112 printf ("Memory type: %d\n", spd->mem_type);
113 printf ("Row addr: %d\n", spd->nrow_addr);
114 printf ("Column addr: %d\n", spd->ncol_addr);
115 printf ("# of rows: %d\n", spd->nrows);
116 printf ("Row density: %d\n", spd->row_dens);
117 printf ("# of banks: %d\n", spd->nbanks);
118 printf ("Data width: %d\n",
119 256 * spd->dataw_msb + spd->dataw_lsb);
120 printf ("Chip width: %d\n", spd->primw);
121 printf ("Refresh rate: %02X\n", spd->refresh);
122 printf ("CAS latencies: %02X\n", spd->cas_lat);
123 printf ("Write latencies: %02X\n", spd->write_lat);
124 printf ("tRP: %d\n", spd->trp);
125 printf ("tRCD: %d\n", spd->trcd);
128 #endif /* SPD_DEBUG */
132 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
133 volatile ddr83xx_t *ddr = &immap->ddr;
134 volatile law83xx_t *ecm = &immap->sysconf.ddrlaw[0];
136 unsigned int n_ranks;
137 unsigned int odt_rd_cfg, odt_wr_cfg;
138 unsigned char twr_clk, twtr_clk;
139 unsigned int sdram_type;
140 unsigned int memsize;
141 unsigned int law_size;
142 unsigned char caslat, caslat_ctrl;
143 unsigned int trfc, trfc_clk, trfc_low, trfc_high;
144 unsigned int trcd_clk, trtp_clk;
145 unsigned char cke_min_clk;
146 unsigned char add_lat, wr_lat;
147 unsigned char wr_data_delay;
148 unsigned char four_act;
150 unsigned char burstlen;
151 unsigned char odt_cfg, mode_odt_enable;
152 unsigned int max_bus_clk;
153 unsigned int max_data_rate, effective_data_rate;
154 unsigned int ddrc_clk;
155 unsigned int refresh_clk;
156 unsigned int sdram_cfg;
157 unsigned int ddrc_ecc_enable;
158 unsigned int pvr = get_pvr();
160 /* Read SPD parameters with I2C */
161 CONFIG_SYS_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
165 /* Check the memory type */
166 if (spd.mem_type != SPD_MEMTYPE_DDR && spd.mem_type != SPD_MEMTYPE_DDR2) {
167 debug("DDR: Module mem type is %02X\n", spd.mem_type);
171 /* Check the number of physical bank */
172 if (spd.mem_type == SPD_MEMTYPE_DDR) {
175 n_ranks = (spd.nrows & 0x7) + 1;
179 printf("DDR: The number of physical bank is %02X\n", n_ranks);
183 /* Check if the number of row of the module is in the range of DDRC */
184 if (spd.nrow_addr < 12 || spd.nrow_addr > 15) {
185 printf("DDR: Row number is out of range of DDRC, row=%02X\n",
190 /* Check if the number of col of the module is in the range of DDRC */
191 if (spd.ncol_addr < 8 || spd.ncol_addr > 11) {
192 printf("DDR: Col number is out of range of DDRC, col=%02X\n",
197 #ifdef CONFIG_SYS_DDRCDR_VALUE
199 * Adjust DDR II IO voltage biasing. It just makes it work.
201 if(spd.mem_type == SPD_MEMTYPE_DDR2) {
202 immap->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
208 * ODT configuration recommendation from DDR Controller Chapter.
210 odt_rd_cfg = 0; /* Never assert ODT */
211 odt_wr_cfg = 0; /* Never assert ODT */
212 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
213 odt_wr_cfg = 1; /* Assert ODT on writes to CSn */
216 /* Setup DDR chip select register */
217 #ifdef CONFIG_SYS_83XX_DDR_USES_CS0
218 ddr->csbnds[0].csbnds = (banksize(spd.row_dens) >> 24) - 1;
219 ddr->cs_config[0] = ( 1 << 31
222 | ((spd.nbanks == 8 ? 1 : 0) << 14)
223 | ((spd.nrow_addr - 12) << 8)
224 | (spd.ncol_addr - 8) );
226 debug("cs0_bnds = 0x%08x\n",ddr->csbnds[0].csbnds);
227 debug("cs0_config = 0x%08x\n",ddr->cs_config[0]);
230 ddr->csbnds[1].csbnds = ( (banksize(spd.row_dens) >> 8)
231 | ((banksize(spd.row_dens) >> 23) - 1) );
232 ddr->cs_config[1] = ( 1<<31
235 | ((spd.nbanks == 8 ? 1 : 0) << 14)
236 | ((spd.nrow_addr - 12) << 8)
237 | (spd.ncol_addr - 8) );
238 debug("cs1_bnds = 0x%08x\n",ddr->csbnds[1].csbnds);
239 debug("cs1_config = 0x%08x\n",ddr->cs_config[1]);
243 ddr->csbnds[2].csbnds = (banksize(spd.row_dens) >> 24) - 1;
244 ddr->cs_config[2] = ( 1 << 31
247 | ((spd.nbanks == 8 ? 1 : 0) << 14)
248 | ((spd.nrow_addr - 12) << 8)
249 | (spd.ncol_addr - 8) );
251 debug("cs2_bnds = 0x%08x\n",ddr->csbnds[2].csbnds);
252 debug("cs2_config = 0x%08x\n",ddr->cs_config[2]);
255 ddr->csbnds[3].csbnds = ( (banksize(spd.row_dens) >> 8)
256 | ((banksize(spd.row_dens) >> 23) - 1) );
257 ddr->cs_config[3] = ( 1<<31
260 | ((spd.nbanks == 8 ? 1 : 0) << 14)
261 | ((spd.nrow_addr - 12) << 8)
262 | (spd.ncol_addr - 8) );
263 debug("cs3_bnds = 0x%08x\n",ddr->csbnds[3].csbnds);
264 debug("cs3_config = 0x%08x\n",ddr->cs_config[3]);
269 * Figure out memory size in Megabytes.
271 memsize = n_ranks * banksize(spd.row_dens) / 0x100000;
274 * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23.
276 law_size = 19 + __ilog2(memsize);
279 * Set up LAWBAR for all of DDR.
281 ecm->bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
282 ecm->ar = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size));
283 debug("DDR:bar=0x%08x\n", ecm->bar);
284 debug("DDR:ar=0x%08x\n", ecm->ar);
287 * Find the largest CAS by locating the highest 1 bit
288 * in the spd.cas_lat field. Translate it to a DDR
289 * controller field value:
291 * CAS Lat DDR I DDR II Ctrl
292 * Clocks SPD Bit SPD Bit Value
293 * ------- ------- ------- -----
304 caslat = __ilog2(spd.cas_lat);
305 if ((spd.mem_type == SPD_MEMTYPE_DDR)
307 printf("DDR I: Invalid SPD CAS Latency: 0x%x.\n", spd.cas_lat);
309 } else if (spd.mem_type == SPD_MEMTYPE_DDR2
310 && (caslat < 2 || caslat > 5)) {
311 printf("DDR II: Invalid SPD CAS Latency: 0x%x.\n",
315 debug("DDR: caslat SPD bit is %d\n", caslat);
317 max_bus_clk = 1000 *10 / (((spd.clk_cycle & 0xF0) >> 4) * 10
318 + (spd.clk_cycle & 0x0f));
319 max_data_rate = max_bus_clk * 2;
321 debug("DDR:Module maximum data rate is: %d MHz\n", max_data_rate);
323 ddrc_clk = gd->mem_clk / 1000000;
324 effective_data_rate = 0;
326 if (max_data_rate >= 460) { /* it is DDR2-800, 667, 533 */
327 if (spd.cas_lat & 0x08)
331 if (ddrc_clk <= 460 && ddrc_clk > 350)
332 effective_data_rate = 400;
333 else if (ddrc_clk <=350 && ddrc_clk > 280)
334 effective_data_rate = 333;
335 else if (ddrc_clk <= 280 && ddrc_clk > 230)
336 effective_data_rate = 266;
338 effective_data_rate = 200;
339 } else if (max_data_rate >= 390 && max_data_rate < 460) { /* it is DDR 400 */
340 if (ddrc_clk <= 460 && ddrc_clk > 350) {
341 /* DDR controller clk at 350~460 */
342 effective_data_rate = 400; /* 5ns */
344 } else if (ddrc_clk <= 350 && ddrc_clk > 280) {
345 /* DDR controller clk at 280~350 */
346 effective_data_rate = 333; /* 6ns */
347 if (spd.clk_cycle2 == 0x60)
351 } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
352 /* DDR controller clk at 230~280 */
353 effective_data_rate = 266; /* 7.5ns */
354 if (spd.clk_cycle3 == 0x75)
356 else if (spd.clk_cycle2 == 0x75)
360 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
361 /* DDR controller clk at 90~230 */
362 effective_data_rate = 200; /* 10ns */
363 if (spd.clk_cycle3 == 0xa0)
365 else if (spd.clk_cycle2 == 0xa0)
370 } else if (max_data_rate >= 323) { /* it is DDR 333 */
371 if (ddrc_clk <= 350 && ddrc_clk > 280) {
372 /* DDR controller clk at 280~350 */
373 effective_data_rate = 333; /* 6ns */
375 } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
376 /* DDR controller clk at 230~280 */
377 effective_data_rate = 266; /* 7.5ns */
378 if (spd.clk_cycle2 == 0x75)
382 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
383 /* DDR controller clk at 90~230 */
384 effective_data_rate = 200; /* 10ns */
385 if (spd.clk_cycle3 == 0xa0)
387 else if (spd.clk_cycle2 == 0xa0)
392 } else if (max_data_rate >= 256) { /* it is DDR 266 */
393 if (ddrc_clk <= 350 && ddrc_clk > 280) {
394 /* DDR controller clk at 280~350 */
395 printf("DDR: DDR controller freq is more than "
396 "max data rate of the module\n");
398 } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
399 /* DDR controller clk at 230~280 */
400 effective_data_rate = 266; /* 7.5ns */
402 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
403 /* DDR controller clk at 90~230 */
404 effective_data_rate = 200; /* 10ns */
405 if (spd.clk_cycle2 == 0xa0)
408 } else if (max_data_rate >= 190) { /* it is DDR 200 */
409 if (ddrc_clk <= 350 && ddrc_clk > 230) {
410 /* DDR controller clk at 230~350 */
411 printf("DDR: DDR controller freq is more than "
412 "max data rate of the module\n");
414 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
415 /* DDR controller clk at 90~230 */
416 effective_data_rate = 200; /* 10ns */
421 debug("DDR:Effective data rate is: %dMHz\n", effective_data_rate);
422 debug("DDR:The MSB 1 of CAS Latency is: %d\n", caslat);
425 * Errata DDR6 work around: input enable 2 cycles earlier.
426 * including MPC834x Rev1.0/1.1 and MPC8360 Rev1.1/1.2.
428 if(PVR_MAJ(pvr) <= 1 && spd.mem_type == SPD_MEMTYPE_DDR){
430 ddr->debug_reg = 0x201c0000; /* CL=2 */
431 else if (caslat == 3)
432 ddr->debug_reg = 0x202c0000; /* CL=2.5 */
433 else if (caslat == 4)
434 ddr->debug_reg = 0x202c0000; /* CL=3.0 */
436 __asm__ __volatile__ ("sync");
438 debug("Errata DDR6 (debug_reg=0x%08x)\n", ddr->debug_reg);
442 * Convert caslat clocks to DDR controller value.
443 * Force caslat_ctrl to be DDR Controller field-sized.
445 if (spd.mem_type == SPD_MEMTYPE_DDR) {
446 caslat_ctrl = (caslat + 1) & 0x07;
448 caslat_ctrl = (2 * caslat - 1) & 0x0f;
451 debug("DDR: effective data rate is %d MHz\n", effective_data_rate);
452 debug("DDR: caslat SPD bit is %d, controller field is 0x%x\n",
453 caslat, caslat_ctrl);
457 * Avoid writing for DDR I.
459 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
460 unsigned char taxpd_clk = 8; /* By the book. */
461 unsigned char tmrd_clk = 2; /* By the book. */
462 unsigned char act_pd_exit = 2; /* Empirical? */
463 unsigned char pre_pd_exit = 6; /* Empirical? */
465 ddr->timing_cfg_0 = (0
466 | ((act_pd_exit & 0x7) << 20) /* ACT_PD_EXIT */
467 | ((pre_pd_exit & 0x7) << 16) /* PRE_PD_EXIT */
468 | ((taxpd_clk & 0xf) << 8) /* ODT_PD_EXIT */
469 | ((tmrd_clk & 0xf) << 0) /* MRS_CYC */
471 debug("DDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
475 * For DDR I, WRREC(Twr) and WRTORD(Twtr) are not in SPD,
476 * use conservative value.
477 * For DDR II, they are bytes 36 and 37, in quarter nanos.
480 if (spd.mem_type == SPD_MEMTYPE_DDR) {
481 twr_clk = 3; /* Clocks */
482 twtr_clk = 1; /* Clocks */
484 twr_clk = picos_to_clk(spd.twr * 250);
485 twtr_clk = picos_to_clk(spd.twtr * 250);
491 * Calculate Trfc, in picos.
492 * DDR I: Byte 42 straight up in ns.
493 * DDR II: Byte 40 and 42 swizzled some, in ns.
495 if (spd.mem_type == SPD_MEMTYPE_DDR) {
496 trfc = spd.trfc * 1000; /* up to ps */
498 unsigned int byte40_table_ps[8] = {
509 trfc = (((spd.trctrfc_ext & 0x1) * 256) + spd.trfc) * 1000
510 + byte40_table_ps[(spd.trctrfc_ext >> 1) & 0x7];
512 trfc_clk = picos_to_clk(trfc);
515 * Trcd, Byte 29, from quarter nanos to ps and clocks.
517 trcd_clk = picos_to_clk(spd.trcd * 250) & 0x7;
520 * Convert trfc_clk to DDR controller fields. DDR I should
521 * fit in the REFREC field (16-19) of TIMING_CFG_1, but the
522 * 83xx controller has an extended REFREC field of three bits.
523 * The controller automatically adds 8 clocks to this value,
524 * so preadjust it down 8 first before splitting it up.
526 trfc_low = (trfc_clk - 8) & 0xf;
527 trfc_high = ((trfc_clk - 8) >> 4) & 0x3;
530 (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) | /* PRETOACT */
531 ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) | /* ACTTOPRE */
532 (trcd_clk << 20 ) | /* ACTTORW */
533 (caslat_ctrl << 16 ) | /* CASLAT */
534 (trfc_low << 12 ) | /* REFEC */
535 ((twr_clk & 0x07) << 8) | /* WRRREC */
536 ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | /* ACTTOACT */
537 ((twtr_clk & 0x07) << 0) /* WRTORD */
543 * For DDR II, with ODT enabled, use "a value" less than ACTTORW,
544 * which comes from Trcd, and also note that:
545 * add_lat + caslat must be >= 4
548 if (spd.mem_type == SPD_MEMTYPE_DDR2
549 && (odt_wr_cfg || odt_rd_cfg)
551 add_lat = 4 - caslat;
552 if ((add_lat + caslat) < 4) {
559 * Historically 0x2 == 4/8 clock delay.
560 * Empirically, 0x3 == 6/8 clock delay is suggested for DDR I 266.
567 * Minimum CKE Pulse Width.
568 * Four Activate Window
570 if (spd.mem_type == SPD_MEMTYPE_DDR) {
572 * This is a lie. It should really be 1, but if it is
573 * set to 1, bits overlap into the old controller's
574 * otherwise unused ACSM field. If we leave it 0, then
575 * the HW will magically treat it as 1 for DDR 1. Oh Yea.
579 trtp_clk = 2; /* By the book. */
580 cke_min_clk = 1; /* By the book. */
581 four_act = 1; /* By the book. */
586 /* Convert SPD value from quarter nanos to picos. */
587 trtp_clk = picos_to_clk(spd.trtp * 250);
592 cke_min_clk = 3; /* By the book. */
593 four_act = picos_to_clk(37500); /* By the book. 1k pages? */
597 * Empirically set ~MCAS-to-preamble override for DDR 2.
598 * Your milage will vary.
601 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
602 if (effective_data_rate == 266) {
603 cpo = 0x4; /* READ_LAT + 1/2 */
604 } else if (effective_data_rate == 333) {
605 cpo = 0x6; /* READ_LAT + 1 */
606 } else if (effective_data_rate == 400) {
607 cpo = 0x7; /* READ_LAT + 5/4 */
609 /* Automatic calibration */
614 ddr->timing_cfg_2 = (0
615 | ((add_lat & 0x7) << 28) /* ADD_LAT */
616 | ((cpo & 0x1f) << 23) /* CPO */
617 | ((wr_lat & 0x7) << 19) /* WR_LAT */
618 | ((trtp_clk & 0x7) << 13) /* RD_TO_PRE */
619 | ((wr_data_delay & 0x7) << 10) /* WR_DATA_DELAY */
620 | ((cke_min_clk & 0x7) << 6) /* CKE_PLS */
621 | ((four_act & 0x1f) << 0) /* FOUR_ACT */
624 debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1);
625 debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2);
627 /* Check DIMM data bus width */
628 if (spd.dataw_lsb < 64) {
629 if (spd.mem_type == SPD_MEMTYPE_DDR)
630 burstlen = 0x03; /* 32 bit data bus, burst len is 8 */
632 burstlen = 0x02; /* 32 bit data bus, burst len is 4 */
633 debug("\n DDR DIMM: data bus width is 32 bit");
635 burstlen = 0x02; /* Others act as 64 bit bus, burst len is 4 */
636 debug("\n DDR DIMM: data bus width is 64 bit");
639 /* Is this an ECC DDR chip? */
640 if (spd.config == 0x02)
641 debug(" with ECC\n");
643 debug(" without ECC\n");
645 /* Burst length is always 4 for 64 bit data bus, 8 for 32 bit data bus,
646 Burst type is sequential
648 if (spd.mem_type == SPD_MEMTYPE_DDR) {
651 ddr->sdram_mode = 0x50 | burstlen; /* CL=1.5 */
654 ddr->sdram_mode = 0x20 | burstlen; /* CL=2.0 */
657 ddr->sdram_mode = 0x60 | burstlen; /* CL=2.5 */
660 ddr->sdram_mode = 0x30 | burstlen; /* CL=3.0 */
663 printf("DDR:only CL 1.5, 2.0, 2.5, 3.0 is supported\n");
667 mode_odt_enable = 0x0; /* Default disabled */
668 if (odt_wr_cfg || odt_rd_cfg) {
670 * Bits 6 and 2 in Extended MRS(1)
671 * Bit 2 == 0x04 == 75 Ohm, with 2 DIMM modules.
672 * Bit 6 == 0x40 == 150 Ohm, with 1 DIMM module.
674 mode_odt_enable = 0x40; /* 150 Ohm */
679 | (1 << (16 + 10)) /* DQS Differential disable */
680 | (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */
681 | (mode_odt_enable << 16) /* ODT Enable in EMRS1 */
682 | ((twr_clk - 1) << 9) /* Write Recovery Autopre */
683 | (caslat << 4) /* caslat */
684 | (burstlen << 0) /* Burst length */
687 debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode);
690 * Clear EMRS2 and EMRS3.
692 ddr->sdram_mode2 = 0;
693 debug("DDR: sdram_mode2 = 0x%08x\n", ddr->sdram_mode2);
695 switch (spd.refresh) {
698 refresh_clk = picos_to_clk(15625000);
702 refresh_clk = picos_to_clk(3900000);
706 refresh_clk = picos_to_clk(7800000);
710 refresh_clk = picos_to_clk(31300000);
714 refresh_clk = picos_to_clk(62500000);
718 refresh_clk = picos_to_clk(125000000);
726 * Set BSTOPRE to 0x100 for page mode
727 * If auto-charge is used, set BSTOPRE = 0
729 ddr->sdram_interval = ((refresh_clk & 0x3fff) << 16) | 0x100;
730 debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval);
736 #ifndef CONFIG_NEVER_ASSERT_ODT_TO_CPU
737 if (odt_rd_cfg | odt_wr_cfg) {
738 odt_cfg = 0x2; /* ODT to IOs during reads */
741 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
743 | (0 << 26) /* True DQS */
744 | (odt_cfg << 21) /* ODT only read */
745 | (1 << 12) /* 1 refresh at a time */
748 debug("DDR: sdram_cfg2 = 0x%08x\n", ddr->sdram_cfg2);
751 #ifdef CONFIG_SYS_DDR_SDRAM_CLK_CNTL /* Optional platform specific value */
752 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
754 debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl);
761 * Figure out the settings for the sdram_cfg register. Build up
762 * the value in 'sdram_cfg' before writing since the write into
763 * the register will actually enable the memory controller, and all
764 * settings must be done before enabling.
766 * sdram_cfg[0] = 1 (ddr sdram logic enable)
767 * sdram_cfg[1] = 1 (self-refresh-enable)
768 * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM)
771 * sdram_cfg[12] = 0 (32_BE =0 , 64 bit bus mode)
772 * sdram_cfg[13] = 0 (8_BE =0, 4-beat bursts)
774 if (spd.mem_type == SPD_MEMTYPE_DDR)
775 sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR1;
777 sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR2;
780 | SDRAM_CFG_MEM_EN /* DDR enable */
781 | SDRAM_CFG_SREN /* Self refresh */
782 | sdram_type /* SDRAM type */
785 /* sdram_cfg[3] = RD_EN - registered DIMM enable */
786 if (spd.mod_attr & 0x02)
787 sdram_cfg |= SDRAM_CFG_RD_EN;
789 /* The DIMM is 32bit width */
790 if (spd.dataw_lsb < 64) {
791 if (spd.mem_type == SPD_MEMTYPE_DDR)
792 sdram_cfg |= SDRAM_CFG_32_BE | SDRAM_CFG_8_BE;
793 if (spd.mem_type == SPD_MEMTYPE_DDR2)
794 sdram_cfg |= SDRAM_CFG_32_BE;
799 #if defined(CONFIG_DDR_ECC)
800 /* Enable ECC with sdram_cfg[2] */
801 if (spd.config == 0x02) {
802 sdram_cfg |= 0x20000000;
804 /* disable error detection */
805 ddr->err_disable = ~ECC_ERROR_ENABLE;
806 /* set single bit error threshold to maximum value,
807 * reset counter to zero */
808 ddr->err_sbe = (255 << ECC_ERROR_MAN_SBET_SHIFT) |
809 (0 << ECC_ERROR_MAN_SBEC_SHIFT);
812 debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
813 debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
815 debug(" DDRC ECC mode: %s\n", ddrc_ecc_enable ? "ON":"OFF");
817 #if defined(CONFIG_DDR_2T_TIMING)
819 * Enable 2T timing by setting sdram_cfg[16].
821 sdram_cfg |= SDRAM_CFG_2T_EN;
823 /* Enable controller, and GO! */
824 ddr->sdram_cfg = sdram_cfg;
828 debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg);
829 return memsize; /*in MBytes*/
831 #endif /* CONFIG_SPD_EEPROM */
833 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
835 * Use timebase counter, get_timer() is not availabe
836 * at this point of initialization yet.
838 static __inline__ unsigned long get_tbms (void)
841 unsigned long tbu1, tbu2;
843 unsigned long long tmp;
845 ulong tbclk = get_tbclk();
847 /* get the timebase ticks */
849 asm volatile ("mftbu %0":"=r" (tbu1):);
850 asm volatile ("mftb %0":"=r" (tbl):);
851 asm volatile ("mftbu %0":"=r" (tbu2):);
852 } while (tbu1 != tbu2);
854 /* convert ticks to ms */
855 tmp = (unsigned long long)(tbu1);
857 tmp += (unsigned long long)(tbl);
858 ms = tmp/(tbclk/1000);
864 * Initialize all of memory for ECC, then enable errors.
866 /* #define CONFIG_DDR_ECC_INIT_VIA_DMA */
867 void ddr_enable_ecc(unsigned int dram_size)
869 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
870 volatile ddr83xx_t *ddr= &immap->ddr;
871 unsigned long t_start, t_end;
874 unsigned int pattern[2];
875 #if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
879 t_start = get_tbms();
880 pattern[0] = 0xdeadbeef;
881 pattern[1] = 0xdeadbeef;
883 #if !defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
884 debug("ddr init: CPU FP write method\n");
886 for (p = 0; p < (u64*)(size); p++) {
887 ppcDWstore((u32*)p, pattern);
889 __asm__ __volatile__ ("sync");
891 debug("ddr init: DMA method\n");
893 for (p = 0; p < (u64*)(size); p++) {
894 ppcDWstore((u32*)p, pattern);
896 __asm__ __volatile__ ("sync");
898 /* Initialise DMA for direct transfer */
900 /* Start DMA to transfer */
901 dma_xfer((uint *)0x2000, 0x2000, (uint *)0); /* 8K */
902 dma_xfer((uint *)0x4000, 0x4000, (uint *)0); /* 16K */
903 dma_xfer((uint *)0x8000, 0x8000, (uint *)0); /* 32K */
904 dma_xfer((uint *)0x10000, 0x10000, (uint *)0); /* 64K */
905 dma_xfer((uint *)0x20000, 0x20000, (uint *)0); /* 128K */
906 dma_xfer((uint *)0x40000, 0x40000, (uint *)0); /* 256K */
907 dma_xfer((uint *)0x80000, 0x80000, (uint *)0); /* 512K */
908 dma_xfer((uint *)0x100000, 0x100000, (uint *)0); /* 1M */
909 dma_xfer((uint *)0x200000, 0x200000, (uint *)0); /* 2M */
910 dma_xfer((uint *)0x400000, 0x400000, (uint *)0); /* 4M */
912 for (i = 1; i < dram_size / 0x800000; i++) {
913 dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
920 debug("\nREADY!!\n");
921 debug("ddr init duration: %ld ms\n", t_end - t_start);
923 /* Clear All ECC Errors */
924 if ((ddr->err_detect & ECC_ERROR_DETECT_MME) == ECC_ERROR_DETECT_MME)
925 ddr->err_detect |= ECC_ERROR_DETECT_MME;
926 if ((ddr->err_detect & ECC_ERROR_DETECT_MBE) == ECC_ERROR_DETECT_MBE)
927 ddr->err_detect |= ECC_ERROR_DETECT_MBE;
928 if ((ddr->err_detect & ECC_ERROR_DETECT_SBE) == ECC_ERROR_DETECT_SBE)
929 ddr->err_detect |= ECC_ERROR_DETECT_SBE;
930 if ((ddr->err_detect & ECC_ERROR_DETECT_MSE) == ECC_ERROR_DETECT_MSE)
931 ddr->err_detect |= ECC_ERROR_DETECT_MSE;
933 /* Disable ECC-Interrupts */
934 ddr->err_int_en &= ECC_ERR_INT_DISABLE;
936 /* Enable errors for ECC */
937 ddr->err_disable &= ECC_ERROR_ENABLE;
939 __asm__ __volatile__ ("sync");
940 __asm__ __volatile__ ("isync");
942 #endif /* CONFIG_DDR_ECC */