3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Copyright 2004 Freescale Semiconductor.
6 * (C) Copyright 2003 Motorola Inc.
7 * Xianghua Xiao (X.Xiao@motorola.com)
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * 20050101: Eran Liberty (liberty@freescale.com)
30 * Initial file creating (porting from 85XX & 8260)
34 #include <asm/processor.h>
38 #include <spd_sdram.h>
40 #ifdef CONFIG_SPD_EEPROM
42 #if defined(CONFIG_DDR_ECC)
43 extern void dma_init(void);
44 extern uint dma_check(void);
45 extern int dma_xfer(void *dest, uint count, void *src);
49 #define CFG_READ_SPD i2c_read
53 * Convert picoseconds into clock cycles (rounding up if needed).
57 picos_to_clk(int picos)
61 clks = picos / (2000000000 / (get_bus_freq(0) / 1000));
62 if (picos % (2000000000 / (get_bus_freq(0) / 1000)) != 0) {
69 unsigned int banksize(unsigned char row_dens)
71 return ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
74 int read_spd(uint addr)
81 static void spd_debug(spd_eeprom_t *spd)
83 printf ("\nDIMM type: %-18.18s\n", spd->mpart);
84 printf ("SPD size: %d\n", spd->info_size);
85 printf ("EEPROM size: %d\n", 1 << spd->chip_size);
86 printf ("Memory type: %d\n", spd->mem_type);
87 printf ("Row addr: %d\n", spd->nrow_addr);
88 printf ("Column addr: %d\n", spd->ncol_addr);
89 printf ("# of rows: %d\n", spd->nrows);
90 printf ("Row density: %d\n", spd->row_dens);
91 printf ("# of banks: %d\n", spd->nbanks);
92 printf ("Data width: %d\n",
93 256 * spd->dataw_msb + spd->dataw_lsb);
94 printf ("Chip width: %d\n", spd->primw);
95 printf ("Refresh rate: %02X\n", spd->refresh);
96 printf ("CAS latencies: %02X\n", spd->cas_lat);
97 printf ("Write latencies: %02X\n", spd->write_lat);
98 printf ("tRP: %d\n", spd->trp);
99 printf ("tRCD: %d\n", spd->trcd);
102 #endif /* SPD_DEBUG */
106 volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
107 volatile ddr8349_t *ddr = &immap->ddr;
108 volatile law8349_t *ecm = &immap->sysconf.ddrlaw[0];
111 unsigned int memsize;
112 unsigned int law_size;
113 unsigned char caslat;
114 unsigned int trfc, trfc_clk, trfc_low;
116 CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
121 puts("DDR:Only two chip selects are supported on ADS.\n");
125 if (spd.nrow_addr < 12
126 || spd.nrow_addr > 14
128 || spd.ncol_addr > 11) {
129 puts("DDR:Row or Col number unsupported.\n");
133 ddr->csbnds[2].csbnds = (banksize(spd.row_dens) >> 24) - 1;
134 ddr->cs_config[2] = ( 1 << 31
135 | (spd.nrow_addr - 12) << 8
136 | (spd.ncol_addr - 8) );
138 debug("cs2_bnds = 0x%08x\n",ddr->csbnds[2].csbnds);
139 debug("cs2_config = 0x%08x\n",ddr->cs_config[2]);
141 if (spd.nrows == 2) {
142 ddr->csbnds[3].csbnds = ( (banksize(spd.row_dens) >> 8)
143 | ((banksize(spd.row_dens) >> 23) - 1) );
144 ddr->cs_config[3] = ( 1<<31
145 | (spd.nrow_addr-12) << 8
146 | (spd.ncol_addr-8) );
147 debug("cs3_bnds = 0x%08x\n",ddr->csbnds[3].csbnds);
148 debug("cs3_config = 0x%08x\n",ddr->cs_config[3]);
151 if (spd.mem_type != 0x07) {
152 puts("No DDR module found!\n");
157 * Figure out memory size in Megabytes.
159 memsize = spd.nrows * banksize(spd.row_dens) / 0x100000;
162 * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23.
164 law_size = 19 + __ilog2(memsize);
167 * Set up LAWBAR for all of DDR.
169 ecm->bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
170 ecm->ar = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size));
171 debug("DDR:bar=0x%08x\n", ecm->bar);
172 debug("DDR:ar=0x%08x\n", ecm->ar);
175 * find the largest CAS
177 if(spd.cas_lat & 0x40) {
179 } else if (spd.cas_lat & 0x20) {
181 } else if (spd.cas_lat & 0x10) {
183 } else if (spd.cas_lat & 0x08) {
185 } else if (spd.cas_lat & 0x04) {
187 } else if (spd.cas_lat & 0x02) {
189 } else if (spd.cas_lat & 0x01) {
192 puts("DDR:no valid CAS Latency information.\n");
196 tmp = 20000 / (((spd.clk_cycle & 0xF0) >> 4) * 10
197 + (spd.clk_cycle & 0x0f));
198 debug("DDR:Module maximum data rate is: %dMhz\n", tmp);
200 tmp1 = get_bus_freq(0) / 1000000;
201 if (tmp1 < 230 && tmp1 >= 90 && tmp >= 230) {
202 /* 90~230 range, treated as DDR 200 */
203 if (spd.clk_cycle3 == 0xa0)
205 else if(spd.clk_cycle2 == 0xa0)
207 } else if (tmp1 < 280 && tmp1 >= 230 && tmp >= 280) {
208 /* 230-280 range, treated as DDR 266 */
209 if (spd.clk_cycle3 == 0x75)
211 else if (spd.clk_cycle2 == 0x75)
213 } else if (tmp1 < 350 && tmp1 >= 280 && tmp >= 350) {
214 /* 280~350 range, treated as DDR 333 */
215 if (spd.clk_cycle3 == 0x60)
217 else if (spd.clk_cycle2 == 0x60)
219 } else if (tmp1 < 90 || tmp1 >= 350) {
220 /* DDR rate out-of-range */
221 puts("DDR:platform frequency is not fit for DDR rate\n");
226 * note: caslat must also be programmed into ddr->sdram_mode
229 * note: WRREC(Twr) and WRTORD(Twtr) are not in SPD,
230 * use conservative value here.
232 trfc = spd.trfc * 1000; /* up to ps */
233 trfc_clk = picos_to_clk(trfc);
234 trfc_low = (trfc_clk - 8) & 0xf;
237 (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) |
238 ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) |
239 ((picos_to_clk(spd.trcd * 250) & 0x07) << 20 ) |
240 ((caslat & 0x07) << 16 ) |
243 ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | 1);
245 ddr->timing_cfg_2 = 0x00000800;
247 debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1);
248 debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2);
251 * Only DDR I is supported
252 * DDR I and II have different mode-register-set definition
256 tmp = 0x50; /* 1.5 */
259 tmp = 0x20; /* 2.0 */
262 tmp = 0x60; /* 2.5 */
265 tmp = 0x30; /* 3.0 */
268 puts("DDR:only CAS Latency 1.5, 2.0, 2.5, 3.0 is supported.\n");
271 #if defined (CONFIG_DDR_32BIT)
272 /* set burst length to 8 for 32-bit data path */
275 /* set burst length to 4 - default for 64-bit data path */
278 ddr->sdram_mode = tmp;
279 debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode);
281 switch(spd.refresh) {
284 tmp = picos_to_clk(15625000);
288 tmp = picos_to_clk(3900000);
292 tmp = picos_to_clk(7800000);
296 tmp = picos_to_clk(31300000);
300 tmp = picos_to_clk(62500000);
304 tmp = picos_to_clk(125000000);
312 * Set BSTOPRE to 0x100 for page mode
313 * If auto-charge is used, set BSTOPRE = 0
315 ddr->sdram_interval = ((tmp & 0x3fff) << 16) | 0x100;
316 debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval);
319 * Is this an ECC DDR chip?
321 #if defined(CONFIG_DDR_ECC)
322 if (spd.config == 0x02) {
323 /* disable error detection */
324 ddr->err_disable = ~ECC_ERROR_ENABLE;
326 /* set single bit error threshold to maximum value,
327 * reset counter to zero */
328 ddr->err_sbe = (255 << ECC_ERROR_MAN_SBET_SHIFT) |
329 (0 << ECC_ERROR_MAN_SBEC_SHIFT);
331 debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
332 debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
340 * CLK_ADJST = 2-MCK/MCK_B, is lauched 1/2 of one SDRAM
341 * clock cycle after address/command
343 /*ddr->sdram_clk_cntl = 0x82000000;*/
344 ddr->sdram_clk_cntl = (DDR_SDRAM_CLK_CNTL_SS_EN|DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05);
347 * Figure out the settings for the sdram_cfg register. Build up
348 * the entire register in 'tmp' before writing since the write into
349 * the register will actually enable the memory controller, and all
350 * settings must be done before enabling.
352 * sdram_cfg[0] = 1 (ddr sdram logic enable)
353 * sdram_cfg[1] = 1 (self-refresh-enable)
354 * sdram_cfg[6:7] = 2 (SDRAM type = DDR SDRAM)
358 #if defined (CONFIG_DDR_32BIT)
359 /* in 32-Bit mode burst len is 8 beats */
360 tmp |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
363 * sdram_cfg[3] = RD_EN - registered DIMM enable
364 * A value of 0x26 indicates micron registered DIMMS (micron.com)
366 if (spd.mod_attr == 0x26) {
370 #if defined(CONFIG_DDR_ECC)
372 * If the user wanted ECC (enabled via sdram_cfg[2])
374 if (spd.config == 0x02) {
375 tmp |= SDRAM_CFG_ECC_EN;
379 #if defined(CONFIG_DDR_2T_TIMING)
381 * Enable 2T timing by setting sdram_cfg[16].
383 tmp |= SDRAM_CFG_2T_EN;
386 ddr->sdram_cfg = tmp;
390 debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg);
391 return memsize; /*in MBytes*/
393 #endif /* CONFIG_SPD_EEPROM */
396 #if defined(CONFIG_DDR_ECC)
398 * Use timebase counter, get_timer() is not availabe
399 * at this point of initialization yet.
401 static __inline__ unsigned long get_tbms (void)
404 unsigned long tbu1, tbu2;
406 unsigned long long tmp;
408 ulong tbclk = get_tbclk();
410 /* get the timebase ticks */
412 asm volatile ("mftbu %0":"=r" (tbu1):);
413 asm volatile ("mftb %0":"=r" (tbl):);
414 asm volatile ("mftbu %0":"=r" (tbu2):);
415 } while (tbu1 != tbu2);
417 /* convert ticks to ms */
418 tmp = (unsigned long long)(tbu1);
420 tmp += (unsigned long long)(tbl);
421 ms = tmp/(tbclk/1000);
427 * Initialize all of memory for ECC, then enable errors.
429 //#define CONFIG_DDR_ECC_INIT_VIA_DMA
430 void ddr_enable_ecc(unsigned int dram_size)
433 volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
434 volatile ddr8349_t *ddr = &immap->ddr;
435 unsigned long t_start, t_end;
436 #if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
440 debug("Initialize a Cachline in DRAM\n");
443 #if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
444 /* Initialise DMA for direct Transfers */
448 t_start = get_tbms();
450 #if !defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
451 debug("DDR init: Cache flush method\n");
452 for (p = 0; p < (uint *)(dram_size); p++) {
453 if (((unsigned int)p & 0x1f) == 0) {
454 ppcDcbz((unsigned long) p);
457 /* write pattern to cache and flush */
458 *p = (unsigned int)0xdeadbeef;
460 if (((unsigned int)p & 0x1c) == 0x1c) {
461 ppcDcbf((unsigned long) p);
465 printf("DDR init: DMA method\n");
466 for (p = 0; p < (uint *)(8 * 1024); p++) {
467 /* zero one data cache line */
468 if (((unsigned int)p & 0x1f) == 0) {
469 ppcDcbz((unsigned long)p);
472 /* write pattern to it and flush */
473 *p = (unsigned int)0xdeadbeef;
475 if (((unsigned int)p & 0x1c) == 0x1c) {
476 ppcDcbf((unsigned long)p);
481 dma_xfer((uint *)0x2000, 0x2000, (uint *)0);
483 dma_xfer((uint *)0x4000, 0x4000, (uint *)0);
485 dma_xfer((uint *)0x8000, 0x8000, (uint *)0);
487 dma_xfer((uint *)0x10000, 0x10000, (uint *)0);
489 dma_xfer((uint *)0x20000, 0x20000, (uint *)0);
491 dma_xfer((uint *)0x40000, 0x40000, (uint *)0);
493 dma_xfer((uint *)0x80000, 0x80000, (uint *)0);
495 dma_xfer((uint *)0x100000, 0x100000, (uint *)0);
497 dma_xfer((uint *)0x200000, 0x200000, (uint *)0);
499 dma_xfer((uint *)0x400000, 0x400000, (uint *)0);
501 for (i = 1; i < dram_size / 0x800000; i++) {
502 dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
509 debug("\nREADY!!\n");
510 debug("ddr init duration: %ld ms\n", t_end - t_start);
512 /* Clear All ECC Errors */
513 if ((ddr->err_detect & ECC_ERROR_DETECT_MME) == ECC_ERROR_DETECT_MME)
514 ddr->err_detect |= ECC_ERROR_DETECT_MME;
515 if ((ddr->err_detect & ECC_ERROR_DETECT_MBE) == ECC_ERROR_DETECT_MBE)
516 ddr->err_detect |= ECC_ERROR_DETECT_MBE;
517 if ((ddr->err_detect & ECC_ERROR_DETECT_SBE) == ECC_ERROR_DETECT_SBE)
518 ddr->err_detect |= ECC_ERROR_DETECT_SBE;
519 if ((ddr->err_detect & ECC_ERROR_DETECT_MSE) == ECC_ERROR_DETECT_MSE)
520 ddr->err_detect |= ECC_ERROR_DETECT_MSE;
522 /* Disable ECC-Interrupts */
523 ddr->err_int_en &= ECC_ERR_INT_DISABLE;
525 /* Enable errors for ECC */
526 ddr->err_disable &= ECC_ERROR_ENABLE;
528 __asm__ __volatile__ ("sync");
529 __asm__ __volatile__ ("isync");
531 #endif /* CONFIG_DDR_ECC */