2 * (C) Copyright 2006-2007 Freescale Semiconductor, Inc.
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
8 * (C) Copyright 2003 Motorola Inc.
9 * Xianghua Xiao (X.Xiao@motorola.com)
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/processor.h>
35 #include <spd_sdram.h>
37 DECLARE_GLOBAL_DATA_PTR;
39 void board_add_ram_info(int use_default)
41 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
42 volatile ddr83xx_t *ddr = &immap->ddr;
45 printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK)
46 >> SDRAM_CFG_SDRAM_TYPE_SHIFT) - 1);
48 if (ddr->sdram_cfg & SDRAM_CFG_32_BE)
53 if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
58 printf(", %s MHz)", strmhz(buf, gd->mem_clk));
60 #if defined(CONFIG_SYS_LB_SDRAM) && defined(CONFIG_SYS_LBC_SDRAM_SIZE)
62 print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, " (local bus)");
66 #ifdef CONFIG_SPD_EEPROM
68 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
69 extern void dma_init(void);
70 extern uint dma_check(void);
71 extern int dma_xfer(void *dest, uint count, void *src);
74 #ifndef CONFIG_SYS_READ_SPD
75 #define CONFIG_SYS_READ_SPD i2c_read
79 * Convert picoseconds into clock cycles (rounding up if needed).
82 picos_to_clk(int picos)
84 unsigned int mem_bus_clk;
87 mem_bus_clk = gd->mem_clk >> 1;
88 clks = picos / (1000000000 / (mem_bus_clk / 1000));
89 if (picos % (1000000000 / (mem_bus_clk / 1000)) != 0)
95 unsigned int banksize(unsigned char row_dens)
97 return ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
100 int read_spd(uint addr)
107 static void spd_debug(spd_eeprom_t *spd)
109 printf ("\nDIMM type: %-18.18s\n", spd->mpart);
110 printf ("SPD size: %d\n", spd->info_size);
111 printf ("EEPROM size: %d\n", 1 << spd->chip_size);
112 printf ("Memory type: %d\n", spd->mem_type);
113 printf ("Row addr: %d\n", spd->nrow_addr);
114 printf ("Column addr: %d\n", spd->ncol_addr);
115 printf ("# of rows: %d\n", spd->nrows);
116 printf ("Row density: %d\n", spd->row_dens);
117 printf ("# of banks: %d\n", spd->nbanks);
118 printf ("Data width: %d\n",
119 256 * spd->dataw_msb + spd->dataw_lsb);
120 printf ("Chip width: %d\n", spd->primw);
121 printf ("Refresh rate: %02X\n", spd->refresh);
122 printf ("CAS latencies: %02X\n", spd->cas_lat);
123 printf ("Write latencies: %02X\n", spd->write_lat);
124 printf ("tRP: %d\n", spd->trp);
125 printf ("tRCD: %d\n", spd->trcd);
128 #endif /* SPD_DEBUG */
132 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
133 volatile ddr83xx_t *ddr = &immap->ddr;
134 volatile law83xx_t *ecm = &immap->sysconf.ddrlaw[0];
136 unsigned int n_ranks;
137 unsigned int odt_rd_cfg, odt_wr_cfg;
138 unsigned char twr_clk, twtr_clk;
139 unsigned int sdram_type;
140 unsigned int memsize;
141 unsigned int law_size;
142 unsigned char caslat, caslat_ctrl;
143 unsigned int trfc, trfc_clk, trfc_low, trfc_high;
144 unsigned int trcd_clk, trtp_clk;
145 unsigned char cke_min_clk;
146 unsigned char add_lat, wr_lat;
147 unsigned char wr_data_delay;
148 unsigned char four_act;
150 unsigned char burstlen;
151 unsigned char odt_cfg, mode_odt_enable;
152 unsigned int max_bus_clk;
153 unsigned int max_data_rate, effective_data_rate;
154 unsigned int ddrc_clk;
155 unsigned int refresh_clk;
156 unsigned int sdram_cfg;
157 unsigned int ddrc_ecc_enable;
158 unsigned int pvr = get_pvr();
160 /* Read SPD parameters with I2C */
161 CONFIG_SYS_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
165 /* Check the memory type */
166 if (spd.mem_type != SPD_MEMTYPE_DDR && spd.mem_type != SPD_MEMTYPE_DDR2) {
167 debug("DDR: Module mem type is %02X\n", spd.mem_type);
171 /* Check the number of physical bank */
172 if (spd.mem_type == SPD_MEMTYPE_DDR) {
175 n_ranks = (spd.nrows & 0x7) + 1;
179 printf("DDR: The number of physical bank is %02X\n", n_ranks);
183 /* Check if the number of row of the module is in the range of DDRC */
184 if (spd.nrow_addr < 12 || spd.nrow_addr > 15) {
185 printf("DDR: Row number is out of range of DDRC, row=%02X\n",
190 /* Check if the number of col of the module is in the range of DDRC */
191 if (spd.ncol_addr < 8 || spd.ncol_addr > 11) {
192 printf("DDR: Col number is out of range of DDRC, col=%02X\n",
197 #ifdef CONFIG_SYS_DDRCDR_VALUE
199 * Adjust DDR II IO voltage biasing. It just makes it work.
201 if(spd.mem_type == SPD_MEMTYPE_DDR2) {
202 immap->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
208 * ODT configuration recommendation from DDR Controller Chapter.
210 odt_rd_cfg = 0; /* Never assert ODT */
211 odt_wr_cfg = 0; /* Never assert ODT */
212 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
213 odt_wr_cfg = 1; /* Assert ODT on writes to CSn */
216 /* Setup DDR chip select register */
217 #ifdef CONFIG_SYS_83XX_DDR_USES_CS0
218 ddr->csbnds[0].csbnds = (banksize(spd.row_dens) >> 24) - 1;
219 ddr->cs_config[0] = ( 1 << 31
222 | (spd.nrow_addr - 12) << 8
223 | (spd.ncol_addr - 8) );
225 debug("cs0_bnds = 0x%08x\n",ddr->csbnds[0].csbnds);
226 debug("cs0_config = 0x%08x\n",ddr->cs_config[0]);
229 ddr->csbnds[1].csbnds = ( (banksize(spd.row_dens) >> 8)
230 | ((banksize(spd.row_dens) >> 23) - 1) );
231 ddr->cs_config[1] = ( 1<<31
234 | (spd.nrow_addr-12) << 8
235 | (spd.ncol_addr-8) );
236 debug("cs1_bnds = 0x%08x\n",ddr->csbnds[1].csbnds);
237 debug("cs1_config = 0x%08x\n",ddr->cs_config[1]);
241 ddr->csbnds[2].csbnds = (banksize(spd.row_dens) >> 24) - 1;
242 ddr->cs_config[2] = ( 1 << 31
245 | (spd.nrow_addr - 12) << 8
246 | (spd.ncol_addr - 8) );
248 debug("cs2_bnds = 0x%08x\n",ddr->csbnds[2].csbnds);
249 debug("cs2_config = 0x%08x\n",ddr->cs_config[2]);
252 ddr->csbnds[3].csbnds = ( (banksize(spd.row_dens) >> 8)
253 | ((banksize(spd.row_dens) >> 23) - 1) );
254 ddr->cs_config[3] = ( 1<<31
257 | (spd.nrow_addr-12) << 8
258 | (spd.ncol_addr-8) );
259 debug("cs3_bnds = 0x%08x\n",ddr->csbnds[3].csbnds);
260 debug("cs3_config = 0x%08x\n",ddr->cs_config[3]);
265 * Figure out memory size in Megabytes.
267 memsize = n_ranks * banksize(spd.row_dens) / 0x100000;
270 * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23.
272 law_size = 19 + __ilog2(memsize);
275 * Set up LAWBAR for all of DDR.
277 ecm->bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
278 ecm->ar = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size));
279 debug("DDR:bar=0x%08x\n", ecm->bar);
280 debug("DDR:ar=0x%08x\n", ecm->ar);
283 * Find the largest CAS by locating the highest 1 bit
284 * in the spd.cas_lat field. Translate it to a DDR
285 * controller field value:
287 * CAS Lat DDR I DDR II Ctrl
288 * Clocks SPD Bit SPD Bit Value
289 * ------- ------- ------- -----
300 caslat = __ilog2(spd.cas_lat);
301 if ((spd.mem_type == SPD_MEMTYPE_DDR)
303 printf("DDR I: Invalid SPD CAS Latency: 0x%x.\n", spd.cas_lat);
305 } else if (spd.mem_type == SPD_MEMTYPE_DDR2
306 && (caslat < 2 || caslat > 5)) {
307 printf("DDR II: Invalid SPD CAS Latency: 0x%x.\n",
311 debug("DDR: caslat SPD bit is %d\n", caslat);
313 max_bus_clk = 1000 *10 / (((spd.clk_cycle & 0xF0) >> 4) * 10
314 + (spd.clk_cycle & 0x0f));
315 max_data_rate = max_bus_clk * 2;
317 debug("DDR:Module maximum data rate is: %d MHz\n", max_data_rate);
319 ddrc_clk = gd->mem_clk / 1000000;
320 effective_data_rate = 0;
322 if (max_data_rate >= 460) { /* it is DDR2-800, 667, 533 */
323 if (spd.cas_lat & 0x08)
327 if (ddrc_clk <= 460 && ddrc_clk > 350)
328 effective_data_rate = 400;
329 else if (ddrc_clk <=350 && ddrc_clk > 280)
330 effective_data_rate = 333;
331 else if (ddrc_clk <= 280 && ddrc_clk > 230)
332 effective_data_rate = 266;
334 effective_data_rate = 200;
335 } else if (max_data_rate >= 390 && max_data_rate < 460) { /* it is DDR 400 */
336 if (ddrc_clk <= 460 && ddrc_clk > 350) {
337 /* DDR controller clk at 350~460 */
338 effective_data_rate = 400; /* 5ns */
340 } else if (ddrc_clk <= 350 && ddrc_clk > 280) {
341 /* DDR controller clk at 280~350 */
342 effective_data_rate = 333; /* 6ns */
343 if (spd.clk_cycle2 == 0x60)
347 } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
348 /* DDR controller clk at 230~280 */
349 effective_data_rate = 266; /* 7.5ns */
350 if (spd.clk_cycle3 == 0x75)
352 else if (spd.clk_cycle2 == 0x75)
356 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
357 /* DDR controller clk at 90~230 */
358 effective_data_rate = 200; /* 10ns */
359 if (spd.clk_cycle3 == 0xa0)
361 else if (spd.clk_cycle2 == 0xa0)
366 } else if (max_data_rate >= 323) { /* it is DDR 333 */
367 if (ddrc_clk <= 350 && ddrc_clk > 280) {
368 /* DDR controller clk at 280~350 */
369 effective_data_rate = 333; /* 6ns */
371 } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
372 /* DDR controller clk at 230~280 */
373 effective_data_rate = 266; /* 7.5ns */
374 if (spd.clk_cycle2 == 0x75)
378 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
379 /* DDR controller clk at 90~230 */
380 effective_data_rate = 200; /* 10ns */
381 if (spd.clk_cycle3 == 0xa0)
383 else if (spd.clk_cycle2 == 0xa0)
388 } else if (max_data_rate >= 256) { /* it is DDR 266 */
389 if (ddrc_clk <= 350 && ddrc_clk > 280) {
390 /* DDR controller clk at 280~350 */
391 printf("DDR: DDR controller freq is more than "
392 "max data rate of the module\n");
394 } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
395 /* DDR controller clk at 230~280 */
396 effective_data_rate = 266; /* 7.5ns */
398 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
399 /* DDR controller clk at 90~230 */
400 effective_data_rate = 200; /* 10ns */
401 if (spd.clk_cycle2 == 0xa0)
404 } else if (max_data_rate >= 190) { /* it is DDR 200 */
405 if (ddrc_clk <= 350 && ddrc_clk > 230) {
406 /* DDR controller clk at 230~350 */
407 printf("DDR: DDR controller freq is more than "
408 "max data rate of the module\n");
410 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
411 /* DDR controller clk at 90~230 */
412 effective_data_rate = 200; /* 10ns */
417 debug("DDR:Effective data rate is: %dMHz\n", effective_data_rate);
418 debug("DDR:The MSB 1 of CAS Latency is: %d\n", caslat);
421 * Errata DDR6 work around: input enable 2 cycles earlier.
422 * including MPC834x Rev1.0/1.1 and MPC8360 Rev1.1/1.2.
424 if(PVR_MAJ(pvr) <= 1 && spd.mem_type == SPD_MEMTYPE_DDR){
426 ddr->debug_reg = 0x201c0000; /* CL=2 */
427 else if (caslat == 3)
428 ddr->debug_reg = 0x202c0000; /* CL=2.5 */
429 else if (caslat == 4)
430 ddr->debug_reg = 0x202c0000; /* CL=3.0 */
432 __asm__ __volatile__ ("sync");
434 debug("Errata DDR6 (debug_reg=0x%08x)\n", ddr->debug_reg);
438 * Convert caslat clocks to DDR controller value.
439 * Force caslat_ctrl to be DDR Controller field-sized.
441 if (spd.mem_type == SPD_MEMTYPE_DDR) {
442 caslat_ctrl = (caslat + 1) & 0x07;
444 caslat_ctrl = (2 * caslat - 1) & 0x0f;
447 debug("DDR: effective data rate is %d MHz\n", effective_data_rate);
448 debug("DDR: caslat SPD bit is %d, controller field is 0x%x\n",
449 caslat, caslat_ctrl);
453 * Avoid writing for DDR I.
455 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
456 unsigned char taxpd_clk = 8; /* By the book. */
457 unsigned char tmrd_clk = 2; /* By the book. */
458 unsigned char act_pd_exit = 2; /* Empirical? */
459 unsigned char pre_pd_exit = 6; /* Empirical? */
461 ddr->timing_cfg_0 = (0
462 | ((act_pd_exit & 0x7) << 20) /* ACT_PD_EXIT */
463 | ((pre_pd_exit & 0x7) << 16) /* PRE_PD_EXIT */
464 | ((taxpd_clk & 0xf) << 8) /* ODT_PD_EXIT */
465 | ((tmrd_clk & 0xf) << 0) /* MRS_CYC */
467 debug("DDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
471 * For DDR I, WRREC(Twr) and WRTORD(Twtr) are not in SPD,
472 * use conservative value.
473 * For DDR II, they are bytes 36 and 37, in quarter nanos.
476 if (spd.mem_type == SPD_MEMTYPE_DDR) {
477 twr_clk = 3; /* Clocks */
478 twtr_clk = 1; /* Clocks */
480 twr_clk = picos_to_clk(spd.twr * 250);
481 twtr_clk = picos_to_clk(spd.twtr * 250);
487 * Calculate Trfc, in picos.
488 * DDR I: Byte 42 straight up in ns.
489 * DDR II: Byte 40 and 42 swizzled some, in ns.
491 if (spd.mem_type == SPD_MEMTYPE_DDR) {
492 trfc = spd.trfc * 1000; /* up to ps */
494 unsigned int byte40_table_ps[8] = {
505 trfc = (((spd.trctrfc_ext & 0x1) * 256) + spd.trfc) * 1000
506 + byte40_table_ps[(spd.trctrfc_ext >> 1) & 0x7];
508 trfc_clk = picos_to_clk(trfc);
511 * Trcd, Byte 29, from quarter nanos to ps and clocks.
513 trcd_clk = picos_to_clk(spd.trcd * 250) & 0x7;
516 * Convert trfc_clk to DDR controller fields. DDR I should
517 * fit in the REFREC field (16-19) of TIMING_CFG_1, but the
518 * 83xx controller has an extended REFREC field of three bits.
519 * The controller automatically adds 8 clocks to this value,
520 * so preadjust it down 8 first before splitting it up.
522 trfc_low = (trfc_clk - 8) & 0xf;
523 trfc_high = ((trfc_clk - 8) >> 4) & 0x3;
526 (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) | /* PRETOACT */
527 ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) | /* ACTTOPRE */
528 (trcd_clk << 20 ) | /* ACTTORW */
529 (caslat_ctrl << 16 ) | /* CASLAT */
530 (trfc_low << 12 ) | /* REFEC */
531 ((twr_clk & 0x07) << 8) | /* WRRREC */
532 ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | /* ACTTOACT */
533 ((twtr_clk & 0x07) << 0) /* WRTORD */
539 * For DDR II, with ODT enabled, use "a value" less than ACTTORW,
540 * which comes from Trcd, and also note that:
541 * add_lat + caslat must be >= 4
544 if (spd.mem_type == SPD_MEMTYPE_DDR2
545 && (odt_wr_cfg || odt_rd_cfg)
547 add_lat = 4 - caslat;
548 if ((add_lat + caslat) < 4) {
555 * Historically 0x2 == 4/8 clock delay.
556 * Empirically, 0x3 == 6/8 clock delay is suggested for DDR I 266.
563 * Minimum CKE Pulse Width.
564 * Four Activate Window
566 if (spd.mem_type == SPD_MEMTYPE_DDR) {
568 * This is a lie. It should really be 1, but if it is
569 * set to 1, bits overlap into the old controller's
570 * otherwise unused ACSM field. If we leave it 0, then
571 * the HW will magically treat it as 1 for DDR 1. Oh Yea.
575 trtp_clk = 2; /* By the book. */
576 cke_min_clk = 1; /* By the book. */
577 four_act = 1; /* By the book. */
582 /* Convert SPD value from quarter nanos to picos. */
583 trtp_clk = picos_to_clk(spd.trtp * 250);
588 cke_min_clk = 3; /* By the book. */
589 four_act = picos_to_clk(37500); /* By the book. 1k pages? */
593 * Empirically set ~MCAS-to-preamble override for DDR 2.
594 * Your milage will vary.
597 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
598 if (effective_data_rate == 266) {
599 cpo = 0x4; /* READ_LAT + 1/2 */
600 } else if (effective_data_rate == 333) {
601 cpo = 0x6; /* READ_LAT + 1 */
602 } else if (effective_data_rate == 400) {
603 cpo = 0x7; /* READ_LAT + 5/4 */
605 /* Automatic calibration */
610 ddr->timing_cfg_2 = (0
611 | ((add_lat & 0x7) << 28) /* ADD_LAT */
612 | ((cpo & 0x1f) << 23) /* CPO */
613 | ((wr_lat & 0x7) << 19) /* WR_LAT */
614 | ((trtp_clk & 0x7) << 13) /* RD_TO_PRE */
615 | ((wr_data_delay & 0x7) << 10) /* WR_DATA_DELAY */
616 | ((cke_min_clk & 0x7) << 6) /* CKE_PLS */
617 | ((four_act & 0x1f) << 0) /* FOUR_ACT */
620 debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1);
621 debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2);
623 /* Check DIMM data bus width */
624 if (spd.dataw_lsb < 64) {
625 if (spd.mem_type == SPD_MEMTYPE_DDR)
626 burstlen = 0x03; /* 32 bit data bus, burst len is 8 */
628 burstlen = 0x02; /* 32 bit data bus, burst len is 4 */
629 debug("\n DDR DIMM: data bus width is 32 bit");
631 burstlen = 0x02; /* Others act as 64 bit bus, burst len is 4 */
632 debug("\n DDR DIMM: data bus width is 64 bit");
635 /* Is this an ECC DDR chip? */
636 if (spd.config == 0x02)
637 debug(" with ECC\n");
639 debug(" without ECC\n");
641 /* Burst length is always 4 for 64 bit data bus, 8 for 32 bit data bus,
642 Burst type is sequential
644 if (spd.mem_type == SPD_MEMTYPE_DDR) {
647 ddr->sdram_mode = 0x50 | burstlen; /* CL=1.5 */
650 ddr->sdram_mode = 0x20 | burstlen; /* CL=2.0 */
653 ddr->sdram_mode = 0x60 | burstlen; /* CL=2.5 */
656 ddr->sdram_mode = 0x30 | burstlen; /* CL=3.0 */
659 printf("DDR:only CL 1.5, 2.0, 2.5, 3.0 is supported\n");
663 mode_odt_enable = 0x0; /* Default disabled */
664 if (odt_wr_cfg || odt_rd_cfg) {
666 * Bits 6 and 2 in Extended MRS(1)
667 * Bit 2 == 0x04 == 75 Ohm, with 2 DIMM modules.
668 * Bit 6 == 0x40 == 150 Ohm, with 1 DIMM module.
670 mode_odt_enable = 0x40; /* 150 Ohm */
675 | (1 << (16 + 10)) /* DQS Differential disable */
676 | (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */
677 | (mode_odt_enable << 16) /* ODT Enable in EMRS1 */
678 | ((twr_clk - 1) << 9) /* Write Recovery Autopre */
679 | (caslat << 4) /* caslat */
680 | (burstlen << 0) /* Burst length */
683 debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode);
686 * Clear EMRS2 and EMRS3.
688 ddr->sdram_mode2 = 0;
689 debug("DDR: sdram_mode2 = 0x%08x\n", ddr->sdram_mode2);
691 switch (spd.refresh) {
694 refresh_clk = picos_to_clk(15625000);
698 refresh_clk = picos_to_clk(3900000);
702 refresh_clk = picos_to_clk(7800000);
706 refresh_clk = picos_to_clk(31300000);
710 refresh_clk = picos_to_clk(62500000);
714 refresh_clk = picos_to_clk(125000000);
722 * Set BSTOPRE to 0x100 for page mode
723 * If auto-charge is used, set BSTOPRE = 0
725 ddr->sdram_interval = ((refresh_clk & 0x3fff) << 16) | 0x100;
726 debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval);
732 #ifndef CONFIG_NEVER_ASSERT_ODT_TO_CPU
733 if (odt_rd_cfg | odt_wr_cfg) {
734 odt_cfg = 0x2; /* ODT to IOs during reads */
737 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
739 | (0 << 26) /* True DQS */
740 | (odt_cfg << 21) /* ODT only read */
741 | (1 << 12) /* 1 refresh at a time */
744 debug("DDR: sdram_cfg2 = 0x%08x\n", ddr->sdram_cfg2);
747 #ifdef CONFIG_SYS_DDR_SDRAM_CLK_CNTL /* Optional platform specific value */
748 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
750 debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl);
757 * Figure out the settings for the sdram_cfg register. Build up
758 * the value in 'sdram_cfg' before writing since the write into
759 * the register will actually enable the memory controller, and all
760 * settings must be done before enabling.
762 * sdram_cfg[0] = 1 (ddr sdram logic enable)
763 * sdram_cfg[1] = 1 (self-refresh-enable)
764 * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM)
767 * sdram_cfg[12] = 0 (32_BE =0 , 64 bit bus mode)
768 * sdram_cfg[13] = 0 (8_BE =0, 4-beat bursts)
770 if (spd.mem_type == SPD_MEMTYPE_DDR)
771 sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR1;
773 sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR2;
776 | SDRAM_CFG_MEM_EN /* DDR enable */
777 | SDRAM_CFG_SREN /* Self refresh */
778 | sdram_type /* SDRAM type */
781 /* sdram_cfg[3] = RD_EN - registered DIMM enable */
782 if (spd.mod_attr & 0x02)
783 sdram_cfg |= SDRAM_CFG_RD_EN;
785 /* The DIMM is 32bit width */
786 if (spd.dataw_lsb < 64) {
787 if (spd.mem_type == SPD_MEMTYPE_DDR)
788 sdram_cfg |= SDRAM_CFG_32_BE | SDRAM_CFG_8_BE;
789 if (spd.mem_type == SPD_MEMTYPE_DDR2)
790 sdram_cfg |= SDRAM_CFG_32_BE;
795 #if defined(CONFIG_DDR_ECC)
796 /* Enable ECC with sdram_cfg[2] */
797 if (spd.config == 0x02) {
798 sdram_cfg |= 0x20000000;
800 /* disable error detection */
801 ddr->err_disable = ~ECC_ERROR_ENABLE;
802 /* set single bit error threshold to maximum value,
803 * reset counter to zero */
804 ddr->err_sbe = (255 << ECC_ERROR_MAN_SBET_SHIFT) |
805 (0 << ECC_ERROR_MAN_SBEC_SHIFT);
808 debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
809 debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
811 debug(" DDRC ECC mode: %s\n", ddrc_ecc_enable ? "ON":"OFF");
813 #if defined(CONFIG_DDR_2T_TIMING)
815 * Enable 2T timing by setting sdram_cfg[16].
817 sdram_cfg |= SDRAM_CFG_2T_EN;
819 /* Enable controller, and GO! */
820 ddr->sdram_cfg = sdram_cfg;
824 debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg);
825 return memsize; /*in MBytes*/
827 #endif /* CONFIG_SPD_EEPROM */
829 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
831 * Use timebase counter, get_timer() is not availabe
832 * at this point of initialization yet.
834 static __inline__ unsigned long get_tbms (void)
837 unsigned long tbu1, tbu2;
839 unsigned long long tmp;
841 ulong tbclk = get_tbclk();
843 /* get the timebase ticks */
845 asm volatile ("mftbu %0":"=r" (tbu1):);
846 asm volatile ("mftb %0":"=r" (tbl):);
847 asm volatile ("mftbu %0":"=r" (tbu2):);
848 } while (tbu1 != tbu2);
850 /* convert ticks to ms */
851 tmp = (unsigned long long)(tbu1);
853 tmp += (unsigned long long)(tbl);
854 ms = tmp/(tbclk/1000);
860 * Initialize all of memory for ECC, then enable errors.
862 /* #define CONFIG_DDR_ECC_INIT_VIA_DMA */
863 void ddr_enable_ecc(unsigned int dram_size)
865 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
866 volatile ddr83xx_t *ddr= &immap->ddr;
867 unsigned long t_start, t_end;
870 unsigned int pattern[2];
871 #if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
875 t_start = get_tbms();
876 pattern[0] = 0xdeadbeef;
877 pattern[1] = 0xdeadbeef;
879 #if !defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
880 debug("ddr init: CPU FP write method\n");
882 for (p = 0; p < (u64*)(size); p++) {
883 ppcDWstore((u32*)p, pattern);
885 __asm__ __volatile__ ("sync");
887 debug("ddr init: DMA method\n");
889 for (p = 0; p < (u64*)(size); p++) {
890 ppcDWstore((u32*)p, pattern);
892 __asm__ __volatile__ ("sync");
894 /* Initialise DMA for direct transfer */
896 /* Start DMA to transfer */
897 dma_xfer((uint *)0x2000, 0x2000, (uint *)0); /* 8K */
898 dma_xfer((uint *)0x4000, 0x4000, (uint *)0); /* 16K */
899 dma_xfer((uint *)0x8000, 0x8000, (uint *)0); /* 32K */
900 dma_xfer((uint *)0x10000, 0x10000, (uint *)0); /* 64K */
901 dma_xfer((uint *)0x20000, 0x20000, (uint *)0); /* 128K */
902 dma_xfer((uint *)0x40000, 0x40000, (uint *)0); /* 256K */
903 dma_xfer((uint *)0x80000, 0x80000, (uint *)0); /* 512K */
904 dma_xfer((uint *)0x100000, 0x100000, (uint *)0); /* 1M */
905 dma_xfer((uint *)0x200000, 0x200000, (uint *)0); /* 2M */
906 dma_xfer((uint *)0x400000, 0x400000, (uint *)0); /* 4M */
908 for (i = 1; i < dram_size / 0x800000; i++) {
909 dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
916 debug("\nREADY!!\n");
917 debug("ddr init duration: %ld ms\n", t_end - t_start);
919 /* Clear All ECC Errors */
920 if ((ddr->err_detect & ECC_ERROR_DETECT_MME) == ECC_ERROR_DETECT_MME)
921 ddr->err_detect |= ECC_ERROR_DETECT_MME;
922 if ((ddr->err_detect & ECC_ERROR_DETECT_MBE) == ECC_ERROR_DETECT_MBE)
923 ddr->err_detect |= ECC_ERROR_DETECT_MBE;
924 if ((ddr->err_detect & ECC_ERROR_DETECT_SBE) == ECC_ERROR_DETECT_SBE)
925 ddr->err_detect |= ECC_ERROR_DETECT_SBE;
926 if ((ddr->err_detect & ECC_ERROR_DETECT_MSE) == ECC_ERROR_DETECT_MSE)
927 ddr->err_detect |= ECC_ERROR_DETECT_MSE;
929 /* Disable ECC-Interrupts */
930 ddr->err_int_en &= ECC_ERR_INT_DISABLE;
932 /* Enable errors for ECC */
933 ddr->err_disable &= ECC_ERROR_ENABLE;
935 __asm__ __volatile__ ("sync");
936 __asm__ __volatile__ ("isync");
938 #endif /* CONFIG_DDR_ECC */