2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de>
5 * Copyright Freescale Semiconductor, Inc. 2004, 2006. All rights reserved.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * U-Boot - Startup Code for MPC83xx PowerPC based Embedded Boards
34 #define CONFIG_83XX 1 /* needed for Linux kernel header files*/
35 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
37 #include <ppc_asm.tmpl>
40 #include <asm/cache.h>
43 #ifndef CONFIG_IDENT_STRING
44 #define CONFIG_IDENT_STRING "MPC83XX"
47 /* We don't want the MMU yet.
52 * Floating Point enable, Machine Check and Recoverable Interr.
55 #define MSR_KERNEL (MSR_FP|MSR_RI)
57 #define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
61 * Set up GOT: Global Offset Table
63 * Use r14 to access the GOT
66 GOT_ENTRY(_GOT2_TABLE_)
67 GOT_ENTRY(_FIXUP_TABLE_)
70 GOT_ENTRY(_start_of_vectors)
71 GOT_ENTRY(_end_of_vectors)
72 GOT_ENTRY(transfer_to_handler)
76 GOT_ENTRY(__bss_start)
80 * The Hard Reset Configuration Word (HRCW) table is in the first 64
81 * (0x40) bytes of flash. It has 8 bytes, but each byte is repeated 8
82 * times so the processor can fetch it out of flash whether the flash
83 * is 8, 16, 32, or 64 bits wide (hardware trickery).
86 #define _HRCW_TABLE_ENTRY(w) \
87 .fill 8,1,(((w)>>24)&0xff); \
88 .fill 8,1,(((w)>>16)&0xff); \
89 .fill 8,1,(((w)>> 8)&0xff); \
90 .fill 8,1,(((w) )&0xff)
92 _HRCW_TABLE_ENTRY(CFG_HRCW_LOW)
93 _HRCW_TABLE_ENTRY(CFG_HRCW_HIGH)
96 * Magic number and version string - put it after the HRCW since it
97 * cannot be first in flash like it is in many other processors.
99 .long 0x27051956 /* U-Boot Magic Number */
101 .globl version_string
103 .ascii U_BOOT_VERSION
104 .ascii " (", __DATE__, " - ", __TIME__, ")"
105 .ascii " ", CONFIG_IDENT_STRING, "\0"
108 #ifndef CONFIG_DEFAULT_IMMR
109 #error CONFIG_DEFAULT_IMMR must be defined
110 #endif /* CFG_DEFAULT_IMMR */
112 #define CFG_IMMR CONFIG_DEFAULT_IMMR
113 #endif /* CFG_IMMR */
116 * After configuration, a system reset exception is executed using the
117 * vector at offset 0x100 relative to the base set by MSR[IP]. If
118 * MSR[IP] is 0, the base address is 0x00000000. If MSR[IP] is 1, the
119 * base address is 0xfff00000. In the case of a Power On Reset or Hard
120 * Reset, the value of MSR[IP] is determined by the CIP field in the
123 * Other bits in the HRCW set up the Base Address and Port Size in BR0.
124 * This determines the location of the boot ROM (flash or EPROM) in the
125 * processor's address space at boot time. As long as the HRCW is set up
126 * so that we eventually end up executing the code below when the
127 * processor executes the reset exception, the actual values used should
130 * Once we have got here, the address mask in OR0 is cleared so that the
131 * bottom 32K of the boot ROM is effectively repeated all throughout the
132 * processor's address space, after which we can jump to the absolute
133 * address at which the boot ROM was linked at compile time, and proceed
134 * to initialise the memory controller without worrying if the rug will
135 * be pulled out from under us, so to speak (it will be fine as long as
136 * we configure BR0 with the same boot ROM link address).
138 . = EXC_OFF_SYS_RESET
141 _start: /* time t 0 */
142 li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH*/
146 . = EXC_OFF_SYS_RESET + 0x10
150 li r21, BOOTFLAG_WARM /* Software reboot */
154 boot_cold: /* time t 3 */
155 lis r4, CONFIG_DEFAULT_IMMR@h
157 boot_warm: /* time t 5 */
158 mfmsr r5 /* save msr contents */
160 ori r3, r3, CFG_IMMR@l
163 /* Initialise the E300 processor core */
164 /*------------------------------------------*/
170 /* Inflate flash location so it appears everywhere, calculate */
171 /* the absolute address in final location of the FLASH, jump */
172 /* there and deflate the flash size back to minimal size */
173 /*------------------------------------------------------------*/
176 GET_GOT /* initialize GOT access */
178 addi r4, r4, -EXC_OFF_SYS_RESET
180 addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET
184 #if 1 /* Remapping flash with LAW0. */
185 bl remap_flash_by_law0
187 #endif /* CFG_RAMBOOT */
194 * Cache must be enabled here for stack-in-cache trick.
195 * This means we need to enable the BATS.
197 * 1) for the EVB, original gt regs need to be mapped
198 * 2) need to have an IBAT for the 0xf region,
199 * we are running there!
200 * Cache should be turned on after BATs, since by default
201 * everything is write-through.
202 * The init-mem BAT can be reused after reloc. The old
203 * gt-regs BAT can be reused after board_init_f calls
204 * board_early_init_f (EVB only).
206 /* enable address translation */
210 /* enable and invalidate the data cache */
213 #ifdef CFG_INIT_RAM_LOCK
218 /* set up the stack pointer in our newly created
220 lis r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h
221 ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l
223 li r0, 0 /* Make room for stack frame header and */
224 stwu r0, -4(r1) /* clear final stack frame so that */
225 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
228 /* let the C-code set up the rest */
230 /* Be careful to keep code relocatable & stack humble */
231 /*------------------------------------------------------*/
233 GET_GOT /* initialize GOT access */
237 /* run low-level CPU init code (in Flash)*/
242 /* run 1st part of board init code (in Flash)*/
249 .globl _start_of_vectors
253 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
255 /* Data Storage exception. */
256 STD_EXCEPTION(0x300, DataStorage, UnknownException)
258 /* Instruction Storage exception. */
259 STD_EXCEPTION(0x400, InstStorage, UnknownException)
261 /* External Interrupt exception. */
263 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
266 /* Alignment exception. */
269 EXCEPTION_PROLOG(SRR0, SRR1)
274 addi r3,r1,STACK_FRAME_OVERHEAD
276 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
277 rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */
278 lwz r6,GOT(transfer_to_handler)
282 .long AlignmentException - _start + EXC_OFF_SYS_RESET
283 .long int_return - _start + EXC_OFF_SYS_RESET
285 /* Program check exception */
288 EXCEPTION_PROLOG(SRR0, SRR1)
289 addi r3,r1,STACK_FRAME_OVERHEAD
291 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
292 rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */
293 lwz r6,GOT(transfer_to_handler)
297 .long ProgramCheckException - _start + EXC_OFF_SYS_RESET
298 .long int_return - _start + EXC_OFF_SYS_RESET
300 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
302 /* I guess we could implement decrementer, and may have
303 * to someday for timekeeping.
305 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
307 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
308 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
309 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
310 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
312 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
313 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
315 STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
316 STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
317 STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
321 * This exception occurs when the program counter matches the
322 * Instruction Address Breakpoint Register (IABR).
324 * I want the cpu to halt if this occurs so I can hunt around
325 * with the debugger and look at things.
327 * When DEBUG is defined, both machine check enable (in the MSR)
328 * and checkstop reset enable (in the reset mode register) are
329 * turned off and so a checkstop condition will result in the cpu
332 * I force the cpu into a checkstop condition by putting an illegal
333 * instruction here (at least this is the theory).
335 * well - that didnt work, so just do an infinite loop!
339 STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException)
341 STD_EXCEPTION(0x1400, SMI, UnknownException)
343 STD_EXCEPTION(0x1500, Trap_15, UnknownException)
344 STD_EXCEPTION(0x1600, Trap_16, UnknownException)
345 STD_EXCEPTION(0x1700, Trap_17, UnknownException)
346 STD_EXCEPTION(0x1800, Trap_18, UnknownException)
347 STD_EXCEPTION(0x1900, Trap_19, UnknownException)
348 STD_EXCEPTION(0x1a00, Trap_1a, UnknownException)
349 STD_EXCEPTION(0x1b00, Trap_1b, UnknownException)
350 STD_EXCEPTION(0x1c00, Trap_1c, UnknownException)
351 STD_EXCEPTION(0x1d00, Trap_1d, UnknownException)
352 STD_EXCEPTION(0x1e00, Trap_1e, UnknownException)
353 STD_EXCEPTION(0x1f00, Trap_1f, UnknownException)
354 STD_EXCEPTION(0x2000, Trap_20, UnknownException)
355 STD_EXCEPTION(0x2100, Trap_21, UnknownException)
356 STD_EXCEPTION(0x2200, Trap_22, UnknownException)
357 STD_EXCEPTION(0x2300, Trap_23, UnknownException)
358 STD_EXCEPTION(0x2400, Trap_24, UnknownException)
359 STD_EXCEPTION(0x2500, Trap_25, UnknownException)
360 STD_EXCEPTION(0x2600, Trap_26, UnknownException)
361 STD_EXCEPTION(0x2700, Trap_27, UnknownException)
362 STD_EXCEPTION(0x2800, Trap_28, UnknownException)
363 STD_EXCEPTION(0x2900, Trap_29, UnknownException)
364 STD_EXCEPTION(0x2a00, Trap_2a, UnknownException)
365 STD_EXCEPTION(0x2b00, Trap_2b, UnknownException)
366 STD_EXCEPTION(0x2c00, Trap_2c, UnknownException)
367 STD_EXCEPTION(0x2d00, Trap_2d, UnknownException)
368 STD_EXCEPTION(0x2e00, Trap_2e, UnknownException)
369 STD_EXCEPTION(0x2f00, Trap_2f, UnknownException)
372 .globl _end_of_vectors
378 * This code finishes saving the registers to the exception frame
379 * and jumps to the appropriate handler for the exception.
380 * Register r21 is pointer into trap frame, r1 has new stack pointer.
382 .globl transfer_to_handler
393 andi. r24,r23,0x3f00 /* get vector offset */
397 lwz r24,0(r23) /* virtual address of handler */
398 lwz r23,4(r23) /* where to go when done */
403 rfi /* jump to handler, enable MMU */
406 mfmsr r28 /* Disable interrupts */
410 SYNC /* Some chip revs need this... */
425 lwz r2,_NIP(r1) /* Restore environment */
436 * This code initialises the E300 processor core
437 * (conforms to PowerPC 603e spec)
438 * Note: expects original MSR contents to be in r5.
440 .globl init_e300_core
441 init_e300_core: /* time t 10 */
442 /* Initialize machine status; enable machine check interrupt */
443 /*-----------------------------------------------------------*/
445 li r3, MSR_KERNEL /* Set ME and RI flags */
446 rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */
448 rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */
450 SYNC /* Some chip revs need this... */
453 mtspr SRR1, r3 /* Make SRR1 match MSR */
457 #if defined(CONFIG_WATCHDOG)
458 /* Initialise the Wathcdog values and reset it (if req) */
459 /*------------------------------------------------------*/
460 lis r4, CFG_WATCHDOG_VALUE
461 ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
471 /* Disable Wathcdog */
472 /*-------------------*/
474 /* Check to see if its enabled for disabling
475 once disabled by SW you can't re-enable */
481 #endif /* CONFIG_WATCHDOG */
483 /* Initialize the Hardware Implementation-dependent Registers */
484 /* HID0 also contains cache control */
485 /*------------------------------------------------------*/
487 lis r3, CFG_HID0_INIT@h
488 ori r3, r3, CFG_HID0_INIT@l
492 lis r3, CFG_HID0_FINAL@h
493 ori r3, r3, CFG_HID0_FINAL@l
498 ori r3, r3, CFG_HID2@l
502 /* clear all BAT's */
503 /*----------------------------------*/
524 /* invalidate all tlb's
526 * From the 603e User Manual: "The 603e provides the ability to
527 * invalidate a TLB entry. The TLB Invalidate Entry (tlbie)
528 * instruction invalidates the TLB entry indexed by the EA, and
529 * operates on both the instruction and data TLBs simultaneously
530 * invalidating four TLB entries (both sets in each TLB). The
531 * index corresponds to bits 15-19 of the EA. To invalidate all
532 * entries within both TLBs, 32 tlbie instructions should be
533 * issued, incrementing this field by one each time."
535 * "Note that the tlbia instruction is not implemented on the
538 * bits 15-19 correspond to addresses 0x00000000 to 0x0001F000
539 * incrementing by 0x1000 each time. The code below is sort of
540 * based on code in "flush_tlbs" from arch/ppc/kernel/head.S
553 /*------------------------------*/
556 .globl invalidate_bats
558 /* invalidate BATs */
563 #if (CFG_HID2 & HID2_HBE)
574 #if (CFG_HID2 & HID2_HBE)
584 /* setup_bats - set them up to some initial state */
590 addis r4, r0, CFG_IBAT0L@h
591 ori r4, r4, CFG_IBAT0L@l
592 addis r3, r0, CFG_IBAT0U@h
593 ori r3, r3, CFG_IBAT0U@l
599 addis r4, r0, CFG_DBAT0L@h
600 ori r4, r4, CFG_DBAT0L@l
601 addis r3, r0, CFG_DBAT0U@h
602 ori r3, r3, CFG_DBAT0U@l
608 addis r4, r0, CFG_IBAT1L@h
609 ori r4, r4, CFG_IBAT1L@l
610 addis r3, r0, CFG_IBAT1U@h
611 ori r3, r3, CFG_IBAT1U@l
617 addis r4, r0, CFG_DBAT1L@h
618 ori r4, r4, CFG_DBAT1L@l
619 addis r3, r0, CFG_DBAT1U@h
620 ori r3, r3, CFG_DBAT1U@l
626 addis r4, r0, CFG_IBAT2L@h
627 ori r4, r4, CFG_IBAT2L@l
628 addis r3, r0, CFG_IBAT2U@h
629 ori r3, r3, CFG_IBAT2U@l
635 addis r4, r0, CFG_DBAT2L@h
636 ori r4, r4, CFG_DBAT2L@l
637 addis r3, r0, CFG_DBAT2U@h
638 ori r3, r3, CFG_DBAT2U@l
644 addis r4, r0, CFG_IBAT3L@h
645 ori r4, r4, CFG_IBAT3L@l
646 addis r3, r0, CFG_IBAT3U@h
647 ori r3, r3, CFG_IBAT3U@l
653 addis r4, r0, CFG_DBAT3L@h
654 ori r4, r4, CFG_DBAT3L@l
655 addis r3, r0, CFG_DBAT3U@h
656 ori r3, r3, CFG_DBAT3U@l
661 #if (CFG_HID2 & HID2_HBE)
663 addis r4, r0, CFG_IBAT4L@h
664 ori r4, r4, CFG_IBAT4L@l
665 addis r3, r0, CFG_IBAT4U@h
666 ori r3, r3, CFG_IBAT4U@l
672 addis r4, r0, CFG_DBAT4L@h
673 ori r4, r4, CFG_DBAT4L@l
674 addis r3, r0, CFG_DBAT4U@h
675 ori r3, r3, CFG_DBAT4U@l
681 addis r4, r0, CFG_IBAT5L@h
682 ori r4, r4, CFG_IBAT5L@l
683 addis r3, r0, CFG_IBAT5U@h
684 ori r3, r3, CFG_IBAT5U@l
690 addis r4, r0, CFG_DBAT5L@h
691 ori r4, r4, CFG_DBAT5L@l
692 addis r3, r0, CFG_DBAT5U@h
693 ori r3, r3, CFG_DBAT5U@l
699 addis r4, r0, CFG_IBAT6L@h
700 ori r4, r4, CFG_IBAT6L@l
701 addis r3, r0, CFG_IBAT6U@h
702 ori r3, r3, CFG_IBAT6U@l
708 addis r4, r0, CFG_DBAT6L@h
709 ori r4, r4, CFG_DBAT6L@l
710 addis r3, r0, CFG_DBAT6U@h
711 ori r3, r3, CFG_DBAT6U@l
717 addis r4, r0, CFG_IBAT7L@h
718 ori r4, r4, CFG_IBAT7L@l
719 addis r3, r0, CFG_IBAT7U@h
720 ori r3, r3, CFG_IBAT7U@l
726 addis r4, r0, CFG_DBAT7L@h
727 ori r4, r4, CFG_DBAT7L@l
728 addis r3, r0, CFG_DBAT7U@h
729 ori r3, r3, CFG_DBAT7U@l
736 * -> for (val = 0; val < 0x20000; val+=0x1000)
750 .globl enable_addr_trans
752 /* enable address translation */
754 ori r5, r5, (MSR_IR | MSR_DR)
759 .globl disable_addr_trans
761 /* disable address translation */
764 andi. r0, r3, (MSR_IR | MSR_DR)
773 * Note: requires that all cache bits in
774 * HID0 are in the low half word.
781 ori r4, r4, HID0_ILOCK
783 ori r4, r3, HID0_ICFI
785 mtspr HID0, r4 /* sets enable and invalidate, clears lock */
787 mtspr HID0, r3 /* clears invalidate */
790 .globl icache_disable
794 ori r4, r4, HID0_ICE|HID0_ILOCK
796 ori r4, r3, HID0_ICFI
798 mtspr HID0, r4 /* sets invalidate, clears enable and lock*/
800 mtspr HID0, r3 /* clears invalidate */
806 rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31
812 li r5, HID0_DCFI|HID0_DLOCK
814 mtspr HID0, r3 /* no invalidate, unlock */
816 ori r5, r3, HID0_DCFI
817 mtspr HID0, r5 /* enable + invalidate */
818 mtspr HID0, r3 /* enable */
822 .globl dcache_disable
826 ori r4, r4, HID0_DCE|HID0_DLOCK
830 mtspr HID0, r4 /* sets invalidate, clears enable and lock */
832 mtspr HID0, r3 /* clears invalidate */
838 rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31
858 /*-------------------------------------------------------------------*/
861 * void relocate_code (addr_sp, gd, addr_moni)
863 * This "function" does not return, instead it continues in RAM
864 * after relocating the monitor code.
868 * r5 = length in bytes
873 mr r1, r3 /* Set new stack pointer */
874 mr r9, r4 /* Save copy of Global Data pointer */
875 mr r10, r5 /* Save copy of Destination Address */
877 mr r3, r5 /* Destination Address */
879 addi r4, r4, -EXC_OFF_SYS_RESET
880 lwz r5, GOT(__init_end)
882 li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
887 * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE)
888 * + Destination Address
894 /* First our own GOT */
896 /* then the one used by the C code */
906 beq cr1,4f /* In place copy is not necessary */
907 beq 7f /* Protect against 0 count */
936 2: slwi r0,r0,2 /* re copy in reverse order ... y do we needed it? */
944 * Now flush the cache: note that we must start from a cache aligned
945 * address. Otherwise we might miss one cache line.
949 beq 7f /* Always flush prefetch queue in any case */
957 sync /* Wait for all dcbst to complete on bus */
963 7: sync /* Wait for all icbi to complete on bus */
967 * We are done. Do not return, instead branch to second part of board
968 * initialization, now running from RAM.
970 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
977 * Relocation Function, r14 point to got2+0x8000
979 * Adjust got2 pointers, no need to check for 0, this code
980 * already puts a few entries in the table.
982 li r0,__got2_entries@sectoff@l
983 la r3,GOT(_GOT2_TABLE_)
984 lwz r11,GOT(_GOT2_TABLE_)
994 * Now adjust the fixups and the pointers to the fixups
995 * in case we need to move ourselves again.
997 2: li r0,__fixup_entries@sectoff@l
998 lwz r3,GOT(_FIXUP_TABLE_)
1012 * Now clear BSS segment
1014 lwz r3,GOT(__bss_start)
1015 #if defined(CONFIG_HYMOD)
1017 * For HYMOD - the environment is the very last item in flash.
1018 * The real .bss stops just before environment starts, so only
1019 * clear up to that point.
1021 * taken from mods for FADS board
1023 lwz r4,GOT(environment)
1039 mr r3, r9 /* Global Data pointer */
1040 mr r4, r10 /* Destination Address */
1044 * Copy exception vector code to low memory
1047 * r7: source address, r8: end address, r9: target address
1052 lwz r8, GOT(_end_of_vectors)
1054 li r9, 0x100 /* reset vector always at 0x100 */
1057 bgelr /* return if r7>=r8 - just in case */
1059 mflr r4 /* save link register */
1069 * relocate `hdlr' and `int_return' entries
1071 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
1072 li r8, Alignment - _start + EXC_OFF_SYS_RESET
1075 addi r7, r7, 0x100 /* next exception vector */
1079 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
1082 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
1085 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
1086 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
1089 addi r7, r7, 0x100 /* next exception vector */
1093 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
1094 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
1097 addi r7, r7, 0x100 /* next exception vector */
1101 mfmsr r3 /* now that the vectors have */
1102 lis r7, MSR_IP@h /* relocated into low memory */
1103 ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */
1104 andc r3, r3, r7 /* (if it was on) */
1105 SYNC /* Some chip revs need this... */
1109 mtlr r4 /* restore link register */
1113 * Function: relocate entries for one exception vector
1116 lwz r0, 0(r7) /* hdlr ... */
1117 add r0, r0, r3 /* ... += dest_addr */
1120 lwz r0, 4(r7) /* int_return ... */
1121 add r0, r0, r3 /* ... += dest_addr */
1126 #ifdef CFG_INIT_RAM_LOCK
1128 /* Allocate Initial RAM in data cache.
1130 lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
1131 ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
1132 li r2, ((CFG_INIT_RAM_END & ~31) + \
1133 (CFG_INIT_RAM_ADDR & 31) + 31) / 32
1140 /* Lock the data cache */
1148 .globl unlock_ram_in_cache
1149 unlock_ram_in_cache:
1150 /* invalidate the INIT_RAM section */
1151 lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
1152 ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
1159 sync /* Wait for all icbi to complete on bus */
1162 /* Unlock the data cache and invalidate it */
1164 li r5, HID0_DLOCK|HID0_DCFI
1165 andc r3, r3, r5 /* no invalidate, unlock */
1166 ori r5, r3, HID0_DCFI /* invalidate, unlock */
1167 mtspr HID0, r5 /* invalidate, unlock */
1168 mtspr HID0, r3 /* no invalidate, unlock */
1174 /* When booting from ROM (Flash or EPROM), clear the */
1175 /* Address Mask in OR0 so ROM appears everywhere */
1176 /*----------------------------------------------------*/
1177 lis r3, (CFG_IMMR)@h /* r3 <= CFG_IMMR */
1179 li r5, 0x7fff /* r5 <= 0x00007FFFF */
1181 stw r4, OR0@l(r3) /* OR0 <= OR0 & 0x00007FFFF */
1183 /* As MPC8349E User's Manual presented, when RCW[BMS] is set to 0,
1184 * system will boot from 0x0000_0100, and the LBLAWBAR0[BASE_ADDR]
1185 * reset value is 0x00000; when RCW[BMS] is set to 1, system will boot
1186 * from 0xFFF0_0100, and the LBLAWBAR0[BASE_ADDR] reset value is
1187 * 0xFF800. From the hard resetting to here, the processor fetched and
1188 * executed the instructions one by one. There is not absolutely
1189 * jumping happened. Laterly, the u-boot code has to do an absolutely
1190 * jumping to tell the CPU instruction fetching component what the
1191 * u-boot TEXT base address is. Because the TEXT base resides in the
1192 * boot ROM memory space, to garantee the code can run smoothly after
1193 * that jumping, we must map in the entire boot ROM by Local Access
1194 * Window. Sometimes, we desire an non-0x00000 or non-0xFF800 starting
1195 * address for boot ROM, such as 0xFE000000. In this case, the default
1196 * LBIU Local Access Widow 0 will not cover this memory space. So, we
1197 * need another window to map in it.
1199 lis r4, (CFG_FLASH_BASE)@h
1200 ori r4, r4, (CFG_FLASH_BASE)@l
1201 stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CFG_FLASH_BASE */
1203 /* Store 0x80000012 + log2(CFG_FLASH_SIZE) into LBLAWAR1 */
1204 lis r4, (0x80000012)@h
1205 ori r4, r4, (0x80000012)@l
1206 li r5, CFG_FLASH_SIZE
1207 1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */
1211 stw r4, LBLAWAR1(r3) /* LBLAWAR1 <= 8MB Flash Size */
1214 /* Though all the LBIU Local Access Windows and LBC Banks will be
1215 * initialized in the C code, we'd better configure boot ROM's
1216 * window 0 and bank 0 correctly at here.
1218 remap_flash_by_law0:
1219 /* Initialize the BR0 with the boot ROM starting address. */
1223 lis r5, (CFG_FLASH_BASE & 0xFFFF8000)@h
1224 ori r5, r5, (CFG_FLASH_BASE & 0xFFFF8000)@l
1226 stw r5, BR0(r3) /* r5 <= (CFG_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */
1229 lis r5, ~((CFG_FLASH_SIZE << 4) - 1)
1233 lis r4, (CFG_FLASH_BASE)@h
1234 ori r4, r4, (CFG_FLASH_BASE)@l
1235 stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CFG_FLASH_BASE */
1237 /* Store 0x80000012 + log2(CFG_FLASH_SIZE) into LBLAWAR0 */
1238 lis r4, (0x80000012)@h
1239 ori r4, r4, (0x80000012)@l
1240 li r5, CFG_FLASH_SIZE
1241 1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */
1244 stw r4, LBLAWAR0(r3) /* LBLAWAR0 <= Flash Size */
1248 stw r4, LBLAWBAR1(r3)
1249 stw r4, LBLAWAR1(r3) /* Off LBIU LAW1 */