2 * Copyright 2004,2007,2008 Freescale Semiconductor, Inc.
3 * (C) Copyright 2002, 2003 Motorola Inc.
4 * Xianghua Xiao (X.Xiao@motorola.com)
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/cache.h>
34 DECLARE_GLOBAL_DATA_PTR;
36 struct cpu_type cpu_type_list [] = {
37 CPU_TYPE_ENTRY(8533, 8533),
38 CPU_TYPE_ENTRY(8533, 8533_E),
39 CPU_TYPE_ENTRY(8536, 8536),
40 CPU_TYPE_ENTRY(8536, 8536_E),
41 CPU_TYPE_ENTRY(8540, 8540),
42 CPU_TYPE_ENTRY(8541, 8541),
43 CPU_TYPE_ENTRY(8541, 8541_E),
44 CPU_TYPE_ENTRY(8543, 8543),
45 CPU_TYPE_ENTRY(8543, 8543_E),
46 CPU_TYPE_ENTRY(8544, 8544),
47 CPU_TYPE_ENTRY(8544, 8544_E),
48 CPU_TYPE_ENTRY(8545, 8545),
49 CPU_TYPE_ENTRY(8545, 8545_E),
50 CPU_TYPE_ENTRY(8547, 8547_E),
51 CPU_TYPE_ENTRY(8548, 8548),
52 CPU_TYPE_ENTRY(8548, 8548_E),
53 CPU_TYPE_ENTRY(8555, 8555),
54 CPU_TYPE_ENTRY(8555, 8555_E),
55 CPU_TYPE_ENTRY(8560, 8560),
56 CPU_TYPE_ENTRY(8567, 8567),
57 CPU_TYPE_ENTRY(8567, 8567_E),
58 CPU_TYPE_ENTRY(8568, 8568),
59 CPU_TYPE_ENTRY(8568, 8568_E),
60 CPU_TYPE_ENTRY(8572, 8572),
61 CPU_TYPE_ENTRY(8572, 8572_E),
64 struct cpu_type *identify_cpu(u32 ver)
67 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
68 if (cpu_type_list[i].soc_ver == ver)
69 return &cpu_type_list[i];
77 uint lcrr; /* local bus clock ratio register */
78 uint clkdiv; /* clock divider portion of lcrr */
84 #ifdef CONFIG_DDR_CLK_FREQ
85 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
86 u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
92 ver = SVR_SOC_VER(svr);
95 major &= 0x7; /* the msb of this nibble is a mfg code */
101 cpu = identify_cpu(ver);
105 if (IS_E_PROCESSOR(svr))
111 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
116 major = PVR_MAJ(pvr);
117 minor = PVR_MIN(pvr);
121 case PVR_FAM(PVR_85xx):
128 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
130 get_sys_info(&sysinfo);
132 puts("Clock Configuration:\n");
133 printf(" CPU:%4lu MHz, ", DIV_ROUND_UP(sysinfo.freqProcessor,1000000));
134 printf("CCB:%4lu MHz,\n", DIV_ROUND_UP(sysinfo.freqSystemBus,1000000));
138 printf(" DDR:%4lu MHz (%lu MT/s data rate), ",
139 DIV_ROUND_UP(sysinfo.freqDDRBus,2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000));
142 printf(" DDR:%4lu MHz (%lu MT/s data rate) (Synchronous), ",
143 DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus, 1000000));
146 printf(" DDR:%4lu MHz (%lu MT/s data rate) (Asynchronous), ",
147 DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000));
151 #if defined(CFG_LBC_LCRR)
155 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
160 clkdiv = lcrr & 0x0f;
161 if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
162 #if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544) || \
163 defined(CONFIG_MPC8572) || defined(CONFIG_MPC8536)
165 * Yes, the entire PQ38 family use the same
166 * bit-representation for twice the clock divider values.
170 printf("LBC:%4lu MHz\n",
171 DIV_ROUND_UP(sysinfo.freqSystemBus, 1000000) / clkdiv);
173 printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr);
177 printf("CPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000);
180 puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
186 /* ------------------------------------------------------------------------- */
188 int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
192 unsigned long val, msr;
198 /* e500 v2 core has reset control register */
199 volatile unsigned int * rstcr;
200 rstcr = (volatile unsigned int *)(CFG_IMMR + 0xE00B0);
201 *rstcr = 0x2; /* HRESET_REQ */
206 * Fallthrough if the code above failed
207 * Initiate hard reset in debug control register DBCR0
208 * Make sure MSR[DE] = 1
224 * Get timebase clock frequency
226 unsigned long get_tbclk (void)
228 return (gd->bus_clk + 4UL)/8UL;
232 #if defined(CONFIG_WATCHDOG)
236 int re_enable = disable_interrupts();
237 reset_85xx_watchdog();
238 if (re_enable) enable_interrupts();
242 reset_85xx_watchdog(void)
245 * Clear TSR(WIS) bit by writing 1
248 val = mfspr(SPRN_TSR);
250 mtspr(SPRN_TSR, val);
252 #endif /* CONFIG_WATCHDOG */
254 #if defined(CONFIG_DDR_ECC)
255 void dma_init(void) {
256 volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);
258 dma->satr0 = 0x02c40000;
259 dma->datr0 = 0x02c40000;
260 dma->sr0 = 0xfffffff; /* clear any errors */
261 asm("sync; isync; msync");
265 uint dma_check(void) {
266 volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);
267 volatile uint status = dma->sr0;
269 /* While the channel is busy, spin */
270 while((status & 4) == 4) {
274 /* clear MR0[CS] channel start bit */
275 dma->mr0 &= 0x00000001;
276 asm("sync;isync;msync");
279 printf ("DMA Error: status = %x\n", status);
284 int dma_xfer(void *dest, uint count, void *src) {
285 volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);
287 dma->dar0 = (uint) dest;
288 dma->sar0 = (uint) src;
290 dma->mr0 = 0xf000004;
291 asm("sync;isync;msync");
292 dma->mr0 = 0xf000005;
293 asm("sync;isync;msync");
298 * Configures a UPM. Currently, the loop fields in MxMR (RLF, WLF and TLF)
299 * are hardcoded as "1"."size" is the number or entries, not a sizeof.
301 void upmconfig (uint upm, uint * table, uint size)
303 int i, mdr, mad, old_mad = 0;
305 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
306 int loopval = 0x00004440;
307 volatile u32 *brp,*orp;
308 volatile u8* dummy = NULL;
314 upmmask = BR_MS_UPMA;
318 upmmask = BR_MS_UPMB;
322 upmmask = BR_MS_UPMC;
325 printf("%s: Bad UPM index %d to configure\n", __FUNCTION__, upm);
329 /* Find the address for the dummy write transaction */
330 for (brp = &lbc->br0, orp = &lbc->or0, i = 0; i < 8;
331 i++, brp += 2, orp += 2) {
333 /* Look for a valid BR with selected UPM */
334 if ((in_be32(brp) & (BR_V | upmmask)) == (BR_V | upmmask)) {
335 dummy = (volatile u8*)(in_be32(brp) >> BR_BA_SHIFT);
341 printf("Error: %s() could not find matching BR\n", __FUNCTION__);
345 for (i = 0; i < size; i++) {
347 out_be32(mxmr, loopval | 0x10000000 | i); /* OP_WRITE */
349 out_be32(&lbc->mdr, table[i]);
351 mdr = in_be32(&lbc->mdr);
353 *(volatile u8 *)dummy = 0;
356 mad = in_be32(mxmr) & 0x3f;
357 } while (mad <= old_mad && !(!mad && i == (size-1)));
360 out_be32(mxmr, loopval); /* OP_NORMAL */
363 #if defined(CONFIG_TSEC_ENET) || defined(CONFIGMPC85XX_FEC)
364 /* Default initializations for TSEC controllers. To override,
365 * create a board-specific function called:
366 * int board_eth_init(bd_t *bis)
369 extern int tsec_initialize(bd_t * bis, int index, char *devname);
371 int cpu_eth_init(bd_t *bis)
373 #if defined(CONFIG_TSEC1)
374 tsec_initialize(bis, 0, CONFIG_TSEC1_NAME);
376 #if defined(CONFIG_TSEC2)
377 tsec_initialize(bis, 1, CONFIG_TSEC2_NAME);
379 #if defined(CONFIG_MPC85XX_FEC)
380 tsec_initialize(bis, 2, CONFIG_MPC85XX_FEC_NAME);
382 #if defined(CONFIG_TSEC3)
383 tsec_initialize(bis, 2, CONFIG_TSEC3_NAME);
385 #if defined(CONFIG_TSEC4)
386 tsec_initialize(bis, 3, CONFIG_TSEC4_NAME);