2 * Copyright 2004,2007,2008 Freescale Semiconductor, Inc.
3 * (C) Copyright 2002, 2003 Motorola Inc.
4 * Xianghua Xiao (X.Xiao@motorola.com)
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #include <asm/cache.h>
36 DECLARE_GLOBAL_DATA_PTR;
38 struct cpu_type cpu_type_list [] = {
39 CPU_TYPE_ENTRY(8533, 8533),
40 CPU_TYPE_ENTRY(8533, 8533_E),
41 CPU_TYPE_ENTRY(8536, 8536),
42 CPU_TYPE_ENTRY(8536, 8536_E),
43 CPU_TYPE_ENTRY(8540, 8540),
44 CPU_TYPE_ENTRY(8541, 8541),
45 CPU_TYPE_ENTRY(8541, 8541_E),
46 CPU_TYPE_ENTRY(8543, 8543),
47 CPU_TYPE_ENTRY(8543, 8543_E),
48 CPU_TYPE_ENTRY(8544, 8544),
49 CPU_TYPE_ENTRY(8544, 8544_E),
50 CPU_TYPE_ENTRY(8545, 8545),
51 CPU_TYPE_ENTRY(8545, 8545_E),
52 CPU_TYPE_ENTRY(8547, 8547_E),
53 CPU_TYPE_ENTRY(8548, 8548),
54 CPU_TYPE_ENTRY(8548, 8548_E),
55 CPU_TYPE_ENTRY(8555, 8555),
56 CPU_TYPE_ENTRY(8555, 8555_E),
57 CPU_TYPE_ENTRY(8560, 8560),
58 CPU_TYPE_ENTRY(8567, 8567),
59 CPU_TYPE_ENTRY(8567, 8567_E),
60 CPU_TYPE_ENTRY(8568, 8568),
61 CPU_TYPE_ENTRY(8568, 8568_E),
62 CPU_TYPE_ENTRY(8572, 8572),
63 CPU_TYPE_ENTRY(8572, 8572_E),
66 struct cpu_type *identify_cpu(u32 ver)
69 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
70 if (cpu_type_list[i].soc_ver == ver)
71 return &cpu_type_list[i];
79 uint lcrr; /* local bus clock ratio register */
80 uint clkdiv; /* clock divider portion of lcrr */
86 #ifdef CONFIG_DDR_CLK_FREQ
87 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
88 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
89 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
95 ver = SVR_SOC_VER(svr);
98 major &= 0x7; /* the msb of this nibble is a mfg code */
100 minor = SVR_MIN(svr);
102 #if (CONFIG_NUM_CPUS > 1)
103 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
104 printf("CPU%d: ", pic->whoami);
109 cpu = identify_cpu(ver);
113 if (IS_E_PROCESSOR(svr))
119 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
124 major = PVR_MAJ(pvr);
125 minor = PVR_MIN(pvr);
129 case PVR_FAM(PVR_85xx):
136 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
138 get_sys_info(&sysinfo);
140 puts("Clock Configuration:\n");
141 printf(" CPU:%4lu MHz, ", DIV_ROUND_UP(sysinfo.freqProcessor,1000000));
142 printf("CCB:%4lu MHz,\n", DIV_ROUND_UP(sysinfo.freqSystemBus,1000000));
146 printf(" DDR:%4lu MHz (%lu MT/s data rate), ",
147 DIV_ROUND_UP(sysinfo.freqDDRBus,2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000));
150 printf(" DDR:%4lu MHz (%lu MT/s data rate) (Synchronous), ",
151 DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus, 1000000));
154 printf(" DDR:%4lu MHz (%lu MT/s data rate) (Asynchronous), ",
155 DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000));
159 #if defined(CONFIG_SYS_LBC_LCRR)
160 lcrr = CONFIG_SYS_LBC_LCRR;
163 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
168 clkdiv = lcrr & 0x0f;
169 if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
170 #if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544) || \
171 defined(CONFIG_MPC8572) || defined(CONFIG_MPC8536)
173 * Yes, the entire PQ38 family use the same
174 * bit-representation for twice the clock divider values.
178 printf("LBC:%4lu MHz\n",
179 DIV_ROUND_UP(sysinfo.freqSystemBus, 1000000) / clkdiv);
181 printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr);
185 printf("CPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000);
188 puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
194 /* ------------------------------------------------------------------------- */
196 int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
200 unsigned long val, msr;
206 /* e500 v2 core has reset control register */
207 volatile unsigned int * rstcr;
208 rstcr = (volatile unsigned int *)(CONFIG_SYS_IMMR + 0xE00B0);
209 *rstcr = 0x2; /* HRESET_REQ */
214 * Fallthrough if the code above failed
215 * Initiate hard reset in debug control register DBCR0
216 * Make sure MSR[DE] = 1
232 * Get timebase clock frequency
234 unsigned long get_tbclk (void)
236 return (gd->bus_clk + 4UL)/8UL;
240 #if defined(CONFIG_WATCHDOG)
244 int re_enable = disable_interrupts();
245 reset_85xx_watchdog();
246 if (re_enable) enable_interrupts();
250 reset_85xx_watchdog(void)
253 * Clear TSR(WIS) bit by writing 1
256 val = mfspr(SPRN_TSR);
258 mtspr(SPRN_TSR, val);
260 #endif /* CONFIG_WATCHDOG */
262 #if defined(CONFIG_DDR_ECC)
263 void dma_init(void) {
264 volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
266 dma->satr0 = 0x02c40000;
267 dma->datr0 = 0x02c40000;
268 dma->sr0 = 0xfffffff; /* clear any errors */
269 asm("sync; isync; msync");
273 uint dma_check(void) {
274 volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
275 volatile uint status = dma->sr0;
277 /* While the channel is busy, spin */
278 while((status & 4) == 4) {
282 /* clear MR0[CS] channel start bit */
283 dma->mr0 &= 0x00000001;
284 asm("sync;isync;msync");
287 printf ("DMA Error: status = %x\n", status);
292 int dma_xfer(void *dest, uint count, void *src) {
293 volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
295 dma->dar0 = (uint) dest;
296 dma->sar0 = (uint) src;
298 dma->mr0 = 0xf000004;
299 asm("sync;isync;msync");
300 dma->mr0 = 0xf000005;
301 asm("sync;isync;msync");
307 * Configures a UPM. The function requires the respective MxMR to be set
308 * before calling this function. "size" is the number or entries, not a sizeof.
310 void upmconfig (uint upm, uint * table, uint size)
312 int i, mdr, mad, old_mad = 0;
314 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
315 volatile u32 *brp,*orp;
316 volatile u8* dummy = NULL;
322 upmmask = BR_MS_UPMA;
326 upmmask = BR_MS_UPMB;
330 upmmask = BR_MS_UPMC;
333 printf("%s: Bad UPM index %d to configure\n", __FUNCTION__, upm);
337 /* Find the address for the dummy write transaction */
338 for (brp = &lbc->br0, orp = &lbc->or0, i = 0; i < 8;
339 i++, brp += 2, orp += 2) {
341 /* Look for a valid BR with selected UPM */
342 if ((in_be32(brp) & (BR_V | BR_MSEL)) == (BR_V | upmmask)) {
343 dummy = (volatile u8*)(in_be32(brp) & BR_BA);
349 printf("Error: %s() could not find matching BR\n", __FUNCTION__);
353 for (i = 0; i < size; i++) {
355 out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_WARR | i);
357 out_be32(&lbc->mdr, table[i]);
359 mdr = in_be32(&lbc->mdr);
361 *(volatile u8 *)dummy = 0;
364 mad = in_be32(mxmr) & MxMR_MAD_MSK;
365 } while (mad <= old_mad && !(!mad && i == (size-1)));
368 out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_NORM);
373 * Initializes on-chip ethernet controllers.
374 * to override, implement board_eth_init()
376 int cpu_eth_init(bd_t *bis)
378 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85xx_FEC)
379 tsec_standard_init(bis);