2 * Copyright 2004,2007,2008 Freescale Semiconductor, Inc.
3 * (C) Copyright 2002, 2003 Motorola Inc.
4 * Xianghua Xiao (X.Xiao@motorola.com)
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/cache.h>
33 DECLARE_GLOBAL_DATA_PTR;
35 struct cpu_type cpu_type_list [] = {
36 CPU_TYPE_ENTRY(8533, 8533),
37 CPU_TYPE_ENTRY(8533, 8533_E),
38 CPU_TYPE_ENTRY(8540, 8540),
39 CPU_TYPE_ENTRY(8541, 8541),
40 CPU_TYPE_ENTRY(8541, 8541_E),
41 CPU_TYPE_ENTRY(8543, 8543),
42 CPU_TYPE_ENTRY(8543, 8543_E),
43 CPU_TYPE_ENTRY(8544, 8544),
44 CPU_TYPE_ENTRY(8544, 8544_E),
45 CPU_TYPE_ENTRY(8545, 8545),
46 CPU_TYPE_ENTRY(8545, 8545_E),
47 CPU_TYPE_ENTRY(8547, 8547_E),
48 CPU_TYPE_ENTRY(8548, 8548),
49 CPU_TYPE_ENTRY(8548, 8548_E),
50 CPU_TYPE_ENTRY(8555, 8555),
51 CPU_TYPE_ENTRY(8555, 8555_E),
52 CPU_TYPE_ENTRY(8560, 8560),
53 CPU_TYPE_ENTRY(8567, 8567),
54 CPU_TYPE_ENTRY(8567, 8567_E),
55 CPU_TYPE_ENTRY(8568, 8568),
56 CPU_TYPE_ENTRY(8568, 8568_E),
57 CPU_TYPE_ENTRY(8572, 8572),
58 CPU_TYPE_ENTRY(8572, 8572_E),
61 struct cpu_type *identify_cpu(uint ver)
64 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
65 if (cpu_type_list[i].soc_ver == ver)
66 return &cpu_type_list[i];
74 uint lcrr; /* local bus clock ratio register */
75 uint clkdiv; /* clock divider portion of lcrr */
81 #ifdef CONFIG_DDR_CLK_FREQ
82 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
83 u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
89 ver = SVR_SOC_VER(svr);
95 cpu = identify_cpu(ver);
105 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
110 major = PVR_MAJ(pvr);
111 minor = PVR_MIN(pvr);
115 case PVR_FAM(PVR_85xx):
122 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
124 get_sys_info(&sysinfo);
126 puts("Clock Configuration:\n");
127 printf(" CPU:%4lu MHz, ", DIV_ROUND_UP(sysinfo.freqProcessor,1000000));
128 printf("CCB:%4lu MHz,\n", DIV_ROUND_UP(sysinfo.freqSystemBus,1000000));
132 printf(" DDR:%4lu MHz (%lu MT/s data rate), ",
133 DIV_ROUND_UP(sysinfo.freqDDRBus,2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000));
136 printf(" DDR:%4lu MHz (%lu MT/s data rate) (Synchronous), ",
137 DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus, 1000000));
140 printf(" DDR:%4lu MHz (%lu MT/s data rate) (Asynchronous), ",
141 DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000));
145 #if defined(CFG_LBC_LCRR)
149 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
154 clkdiv = lcrr & 0x0f;
155 if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
156 #if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544)
158 * Yes, the entire PQ38 family use the same
159 * bit-representation for twice the clock divider values.
163 printf("LBC:%4lu MHz\n",
164 DIV_ROUND_UP(sysinfo.freqSystemBus, 1000000) / clkdiv);
166 printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr);
170 printf("CPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000);
173 puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
179 /* ------------------------------------------------------------------------- */
181 int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
185 unsigned long val, msr;
191 /* e500 v2 core has reset control register */
192 volatile unsigned int * rstcr;
193 rstcr = (volatile unsigned int *)(CFG_IMMR + 0xE00B0);
194 *rstcr = 0x2; /* HRESET_REQ */
199 * Fallthrough if the code above failed
200 * Initiate hard reset in debug control register DBCR0
201 * Make sure MSR[DE] = 1
217 * Get timebase clock frequency
219 unsigned long get_tbclk (void)
221 return (gd->bus_clk + 4UL)/8UL;
225 #if defined(CONFIG_WATCHDOG)
229 int re_enable = disable_interrupts();
230 reset_85xx_watchdog();
231 if (re_enable) enable_interrupts();
235 reset_85xx_watchdog(void)
238 * Clear TSR(WIS) bit by writing 1
241 val = mfspr(SPRN_TSR);
243 mtspr(SPRN_TSR, val);
245 #endif /* CONFIG_WATCHDOG */
247 #if defined(CONFIG_DDR_ECC)
248 void dma_init(void) {
249 volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);
251 dma->satr0 = 0x02c40000;
252 dma->datr0 = 0x02c40000;
253 dma->sr0 = 0xfffffff; /* clear any errors */
254 asm("sync; isync; msync");
258 uint dma_check(void) {
259 volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);
260 volatile uint status = dma->sr0;
262 /* While the channel is busy, spin */
263 while((status & 4) == 4) {
267 /* clear MR0[CS] channel start bit */
268 dma->mr0 &= 0x00000001;
269 asm("sync;isync;msync");
272 printf ("DMA Error: status = %x\n", status);
277 int dma_xfer(void *dest, uint count, void *src) {
278 volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);
280 dma->dar0 = (uint) dest;
281 dma->sar0 = (uint) src;
283 dma->mr0 = 0xf000004;
284 asm("sync;isync;msync");
285 dma->mr0 = 0xf000005;
286 asm("sync;isync;msync");