2 * Copyright 2007-2009 Freescale Semiconductor, Inc.
4 * (C) Copyright 2003 Motorola Inc.
5 * Modified by Xianghua Xiao, X.Xiao@motorola.com
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/processor.h>
35 #include <asm/fsl_law.h>
38 DECLARE_GLOBAL_DATA_PTR;
41 extern void fsl_serdes_init(void);
45 extern qe_iop_conf_t qe_iop_conf_tab[];
46 extern void qe_config_iopin(u8 port, u8 pin, int dir,
47 int open_drain, int assign);
48 extern void qe_init(uint qe_base);
49 extern void qe_reset(void);
51 static void config_qe_ioports(void)
54 int dir, open_drain, assign;
57 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
58 port = qe_iop_conf_tab[i].port;
59 pin = qe_iop_conf_tab[i].pin;
60 dir = qe_iop_conf_tab[i].dir;
61 open_drain = qe_iop_conf_tab[i].open_drain;
62 assign = qe_iop_conf_tab[i].assign;
63 qe_config_iopin(port, pin, dir, open_drain, assign);
69 void config_8560_ioports (volatile ccsr_cpm_t * cpm)
73 for (portnum = 0; portnum < 4; portnum++) {
80 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
81 iop_conf_t *eiopc = iopc + 32;
86 * index 0 refers to pin 31,
87 * index 31 refers to pin 0
89 while (iopc < eiopc) {
109 volatile ioport_t *iop = ioport_addr (cpm, portnum);
113 * the (somewhat confused) paragraph at the
114 * bottom of page 35-5 warns that there might
115 * be "unknown behaviour" when programming
116 * PSORx and PDIRx, if PPARx = 1, so I
117 * decided this meant I had to disable the
118 * dedicated function first, and enable it
122 iop->psor = (iop->psor & tpmsk) | psor;
123 iop->podr = (iop->podr & tpmsk) | podr;
124 iop->pdat = (iop->pdat & tpmsk) | pdat;
125 iop->pdir = (iop->pdir & tpmsk) | pdir;
133 * Breathe some life into the CPU...
135 * Set up the memory map
136 * initialize a bunch of registers
139 void cpu_init_f (void)
141 volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
142 extern void m8560_cpm_reset (void);
143 #ifdef CONFIG_MPC8548
144 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
145 uint svr = get_svr();
148 * CPU2 errata workaround: A core hang possible while executing
149 * a msync instruction and a snoopable transaction from an I/O
150 * master tagged to make quick forward progress is present.
151 * Fixed in silicon rev 2.1.
153 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
154 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
161 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
164 /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
165 * addresses - these have to be modified later when FLASH size
166 * has been determined
168 #if defined(CONFIG_SYS_OR0_REMAP)
169 memctl->or0 = CONFIG_SYS_OR0_REMAP;
171 #if defined(CONFIG_SYS_OR1_REMAP)
172 memctl->or1 = CONFIG_SYS_OR1_REMAP;
175 /* now restrict to preliminary range */
176 /* if cs1 is already set via debugger, leave cs0/cs1 alone */
177 if (! memctl->br1 & 1) {
178 #if defined(CONFIG_SYS_BR0_PRELIM) && defined(CONFIG_SYS_OR0_PRELIM)
179 memctl->br0 = CONFIG_SYS_BR0_PRELIM;
180 memctl->or0 = CONFIG_SYS_OR0_PRELIM;
183 #if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
184 memctl->or1 = CONFIG_SYS_OR1_PRELIM;
185 memctl->br1 = CONFIG_SYS_BR1_PRELIM;
189 #if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
190 memctl->or2 = CONFIG_SYS_OR2_PRELIM;
191 memctl->br2 = CONFIG_SYS_BR2_PRELIM;
194 #if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
195 memctl->or3 = CONFIG_SYS_OR3_PRELIM;
196 memctl->br3 = CONFIG_SYS_BR3_PRELIM;
199 #if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
200 memctl->or4 = CONFIG_SYS_OR4_PRELIM;
201 memctl->br4 = CONFIG_SYS_BR4_PRELIM;
204 #if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
205 memctl->or5 = CONFIG_SYS_OR5_PRELIM;
206 memctl->br5 = CONFIG_SYS_BR5_PRELIM;
209 #if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
210 memctl->or6 = CONFIG_SYS_OR6_PRELIM;
211 memctl->br6 = CONFIG_SYS_BR6_PRELIM;
214 #if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
215 memctl->or7 = CONFIG_SYS_OR7_PRELIM;
216 memctl->br7 = CONFIG_SYS_BR7_PRELIM;
219 #if defined(CONFIG_CPM2)
223 /* Config QE ioports */
226 #if defined(CONFIG_MPC8536)
229 #if defined(CONFIG_FSL_DMA)
236 * Initialize L2 as cache.
238 * The newer 8548, etc, parts have twice as much cache, but
239 * use the same bit-encoding as the older 8555, etc, parts.
247 #if defined(CONFIG_L2_CACHE)
248 volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
249 volatile uint cache_ctl;
255 ver = SVR_SOC_VER(svr);
258 cache_ctl = l2cache->l2ctl;
260 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
261 if (cache_ctl & MPC85xx_L2CTL_L2E) {
262 /* Clear L2 SRAM memory-mapped base address */
263 out_be32(&l2cache->l2srbar0, 0x0);
264 out_be32(&l2cache->l2srbar1, 0x0);
266 /* set MBECCDIS=0, SBECCDIS=0 */
267 clrbits_be32(&l2cache->l2errdis,
268 (MPC85xx_L2ERRDIS_MBECC |
269 MPC85xx_L2ERRDIS_SBECC));
271 /* set L2E=0, L2SRAM=0 */
272 clrbits_be32(&l2cache->l2ctl,
274 MPC85xx_L2CTL_L2SRAM_ENTIRE));
278 l2siz_field = (cache_ctl >> 28) & 0x3;
280 switch (l2siz_field) {
282 printf(" unknown size (0x%08x)\n", cache_ctl);
286 if (ver == SVR_8540 || ver == SVR_8560 ||
287 ver == SVR_8541 || ver == SVR_8541_E ||
288 ver == SVR_8555 || ver == SVR_8555_E) {
290 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */
291 cache_ctl = 0xc4000000;
294 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
298 if (ver == SVR_8540 || ver == SVR_8560 ||
299 ver == SVR_8541 || ver == SVR_8541_E ||
300 ver == SVR_8555 || ver == SVR_8555_E) {
302 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */
303 cache_ctl = 0xc8000000;
306 /* set L2E=1, L2I=1, & L2SRAM=0 */
307 cache_ctl = 0xc0000000;
312 /* set L2E=1, L2I=1, & L2SRAM=0 */
313 cache_ctl = 0xc0000000;
317 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
318 puts("already enabled");
319 l2srbar = l2cache->l2srbar0;
320 #ifdef CONFIG_SYS_INIT_L2_ADDR
321 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
322 && l2srbar >= CONFIG_SYS_FLASH_BASE) {
323 l2srbar = CONFIG_SYS_INIT_L2_ADDR;
324 l2cache->l2srbar0 = l2srbar;
325 printf("moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
327 #endif /* CONFIG_SYS_INIT_L2_ADDR */
331 l2cache->l2ctl = cache_ctl; /* invalidate & enable */
335 #elif defined(CONFIG_BACKSIDE_L2_CACHE)
336 u32 l2cfg0 = mfspr(SPRN_L2CFG0);
338 /* invalidate the L2 cache */
339 mtspr(SPRN_L2CSR0, L2CSR0_L2FI);
340 while (mfspr(SPRN_L2CSR0) & L2CSR0_L2FI)
343 /* enable the cache */
344 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
346 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E)
347 printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64);
352 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
357 #if defined(CONFIG_MP)
363 extern void setup_ivors(void);
365 void arch_preboot_os(void)