2 * Copyright 2008-2009 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/processor.h>
31 DECLARE_GLOBAL_DATA_PTR;
35 return mfspr(SPRN_PIR);
40 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
41 out_be32(&pic->pir, 1 << nr);
42 /* the dummy read works around an errata on early 85xx MP PICs */
43 (void)in_be32(&pic->pir);
44 out_be32(&pic->pir, 0x0);
49 int cpu_status(int nr)
51 u32 *table, id = get_my_id();
54 table = (u32 *)get_spin_addr();
55 printf("table base @ 0x%p\n", table);
57 table = (u32 *)get_spin_addr() + nr * NUM_BOOT_ENTRY;
58 printf("Running on cpu %d\n", id);
60 printf("table @ 0x%p\n", table);
61 printf(" addr - 0x%08x\n", table[BOOT_ENTRY_ADDR_LOWER]);
62 printf(" pir - 0x%08x\n", table[BOOT_ENTRY_PIR]);
63 printf(" r3 - 0x%08x\n", table[BOOT_ENTRY_R3_LOWER]);
64 printf(" r6 - 0x%08x\n", table[BOOT_ENTRY_R6_LOWER]);
70 static u8 boot_entry_map[4] = {
77 int cpu_release(int nr, int argc, char *argv[])
79 u32 i, val, *table = (u32 *)get_spin_addr() + nr * NUM_BOOT_ENTRY;
82 if (nr == get_my_id()) {
83 printf("Invalid to release the boot core.\n\n");
88 printf("Invalid number of arguments to release.\n\n");
92 #ifdef CONFIG_SYS_64BIT_STRTOUL
93 boot_addr = simple_strtoull(argv[0], NULL, 16);
95 boot_addr = simple_strtoul(argv[0], NULL, 16);
98 /* handle pir, r3, r6 */
99 for (i = 1; i < 4; i++) {
100 if (argv[i][0] != '-') {
101 u8 entry = boot_entry_map[i];
102 val = simple_strtoul(argv[i], NULL, 16);
107 table[BOOT_ENTRY_ADDR_UPPER] = (u32)(boot_addr >> 32);
109 /* ensure all table updates complete before final address write */
112 table[BOOT_ENTRY_ADDR_LOWER] = (u32)(boot_addr & 0xffffffff);
117 u32 determine_mp_bootpg(void)
119 /* if we have 4G or more of memory, put the boot page at 4Gb-4k */
120 if ((u64)gd->ram_size > 0xfffff000)
123 return (gd->ram_size - 4096);
126 ulong get_spin_addr(void)
128 extern ulong __secondary_start_page;
129 extern ulong __spin_table;
132 (ulong)&__spin_table - (ulong)&__secondary_start_page;
138 static void pq3_mp_up(unsigned long bootpg)
140 u32 up, cpu_up_mask, whoami;
141 u32 *table = (u32 *)get_spin_addr();
143 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
144 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
145 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
149 whoami = in_be32(&pic->whoami);
150 out_be32(&ecm->bptr, 0x80000000 | (bootpg >> 12));
152 /* disable time base at the platform */
153 devdisr = in_be32(&gur->devdisr);
155 devdisr |= MPC85xx_DEVDISR_TB0;
157 devdisr |= MPC85xx_DEVDISR_TB1;
158 out_be32(&gur->devdisr, devdisr);
160 /* release the hounds */
161 up = ((1 << cpu_numcores()) - 1);
162 bpcr = in_be32(&ecm->eebpcr);
164 out_be32(&ecm->eebpcr, bpcr);
165 asm("sync; isync; msync");
167 cpu_up_mask = 1 << whoami;
168 /* wait for everyone */
171 for (i = 0; i < cpu_numcores(); i++) {
172 if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER])
173 cpu_up_mask |= (1 << i);
176 if ((cpu_up_mask & up) == up)
184 printf("CPU up timeout. CPU up mask is %x should be %x\n",
187 /* enable time base at the platform */
189 devdisr |= MPC85xx_DEVDISR_TB1;
191 devdisr |= MPC85xx_DEVDISR_TB0;
192 out_be32(&gur->devdisr, devdisr);
196 devdisr &= ~(MPC85xx_DEVDISR_TB0 | MPC85xx_DEVDISR_TB1);
197 out_be32(&gur->devdisr, devdisr);
200 void cpu_mp_lmb_reserve(struct lmb *lmb)
202 u32 bootpg = determine_mp_bootpg();
204 lmb_reserve(lmb, bootpg, 4096);
209 extern ulong __secondary_start_page;
210 ulong fixup = (ulong)&__secondary_start_page;
211 u32 bootpg = determine_mp_bootpg();
213 /* look for the tlb covering the reset page, there better be one */
214 int i = find_tlb_idx((void *)0xfffff000, 1);
216 /* we found a match */
218 /* map reset page to bootpg so we can copy code there */
221 set_tlb(1, 0xfffff000, bootpg, /* tlb, epn, rpn */
222 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, /* perms, wimge */
223 0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */
225 memcpy((void *)0xfffff000, (void *)fixup, 4096);
226 flush_cache(0xfffff000, 4096);
230 /* setup reset page back to 1:1, we'll use HW boot translation
231 * to map this where we want
233 set_tlb(1, 0xfffff000, 0xfffff000, /* tlb, epn, rpn */
234 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, /* perms, wimge */
235 0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */
239 puts("WARNING: No reset page TLB. "
240 "Skipping secondary core setup\n");