2 * Copyright 2004 Freescale Semiconductor.
4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * cpu_init.c - low level cpu init
32 DECLARE_GLOBAL_DATA_PTR;
35 * Breathe some life into the CPU...
37 * Set up the memory map
38 * initialize a bunch of registers
43 volatile immap_t *immap = (immap_t *)CFG_IMMR;
44 volatile ccsr_lbc_t *memctl = &immap->im_lbc;
46 /* Pointer is writable since we allocated a register for it */
47 gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
49 /* Clear initial global data */
50 memset ((void *) gd, 0, sizeof (gd_t));
56 /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
57 * addresses - these have to be modified later when FLASH size
61 #if defined(CFG_OR0_REMAP)
62 memctl->or0 = CFG_OR0_REMAP;
64 #if defined(CFG_OR1_REMAP)
65 memctl->or1 = CFG_OR1_REMAP;
68 /* now restrict to preliminary range */
69 #if defined(CFG_BR0_PRELIM) && defined(CFG_OR0_PRELIM)
70 memctl->br0 = CFG_BR0_PRELIM;
71 memctl->or0 = CFG_OR0_PRELIM;
74 #if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM)
75 memctl->or1 = CFG_OR1_PRELIM;
76 memctl->br1 = CFG_BR1_PRELIM;
79 #if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM)
80 memctl->or2 = CFG_OR2_PRELIM;
81 memctl->br2 = CFG_BR2_PRELIM;
84 #if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM)
85 memctl->or3 = CFG_OR3_PRELIM;
86 memctl->br3 = CFG_BR3_PRELIM;
89 #if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM)
90 memctl->or4 = CFG_OR4_PRELIM;
91 memctl->br4 = CFG_BR4_PRELIM;
94 #if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM)
95 memctl->or5 = CFG_OR5_PRELIM;
96 memctl->br5 = CFG_BR5_PRELIM;
99 #if defined(CFG_BR6_PRELIM) && defined(CFG_OR6_PRELIM)
100 memctl->or6 = CFG_OR6_PRELIM;
101 memctl->br6 = CFG_BR6_PRELIM;
104 #if defined(CFG_BR7_PRELIM) && defined(CFG_OR7_PRELIM)
105 memctl->or7 = CFG_OR7_PRELIM;
106 memctl->br7 = CFG_BR7_PRELIM;
109 /* enable the timebase bit in HID0 */
110 set_hid0(get_hid0() | 0x4000000);
112 /* enable EMCP, SYNCBE | ABE bits in HID1 */
113 set_hid1(get_hid1() | 0x80000C00);
117 * initialize higher level parts of CPU like timers
121 #ifdef CONFIG_FSL_LAW