2 * Copyright 2004 Freescale Semiconductor.
3 * Srikanth Srinivasan <srikanth.srinivaan@freescale.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* U-Boot - Startup Code for 86xx PowerPC based Embedded Boards
27 * The processor starts at 0xfff00100 and the code is executed
28 * from flash. The code is organized to be at an other address
29 * in memory, but as long we don't jump around before relocating.
30 * board_init lies at a quite high address and when the cpu has
31 * jumped there, everything is ok.
37 #include <ppc_asm.tmpl>
40 #include <asm/cache.h>
43 #ifndef CONFIG_IDENT_STRING
44 #define CONFIG_IDENT_STRING ""
47 /* We don't want the MMU yet.
50 /* Machine Check and Recoverable Interr. */
51 #define MSR_KERNEL ( MSR_ME | MSR_RI )
54 * Set up GOT: Global Offset Table
56 * Use r14 to access the GOT
59 GOT_ENTRY(_GOT2_TABLE_)
60 GOT_ENTRY(_FIXUP_TABLE_)
63 GOT_ENTRY(_start_of_vectors)
64 GOT_ENTRY(_end_of_vectors)
65 GOT_ENTRY(transfer_to_handler)
69 GOT_ENTRY(__bss_start)
73 * r3 - 1st arg to board_init(): IMMP pointer
74 * r4 - 2nd arg to board_init(): boot flag
77 .long 0x27051956 /* U-Boot Magic Number */
81 .ascii " (", __DATE__, " - ", __TIME__, ")"
82 .ascii CONFIG_IDENT_STRING, "\0"
87 li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */
91 . = EXC_OFF_SYS_RESET + 0x10
95 li r21, BOOTFLAG_WARM /* Software reboot */
99 /* the boot code is located below the exception table */
101 .globl _start_of_vectors
105 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
107 /* Data Storage exception. */
108 STD_EXCEPTION(0x300, DataStorage, UnknownException)
110 /* Instruction Storage exception. */
111 STD_EXCEPTION(0x400, InstStorage, UnknownException)
113 /* External Interrupt exception. */
114 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
116 /* Alignment exception. */
124 addi r3,r1,STACK_FRAME_OVERHEAD
126 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
127 lwz r6,GOT(transfer_to_handler)
131 .long AlignmentException - _start + EXC_OFF_SYS_RESET
132 .long int_return - _start + EXC_OFF_SYS_RESET
134 /* Program check exception */
138 addi r3,r1,STACK_FRAME_OVERHEAD
140 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
141 lwz r6,GOT(transfer_to_handler)
145 .long ProgramCheckException - _start + EXC_OFF_SYS_RESET
146 .long int_return - _start + EXC_OFF_SYS_RESET
148 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
150 /* I guess we could implement decrementer, and may have
151 * to someday for timekeeping.
153 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
154 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
155 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
156 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
157 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
158 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
159 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
160 STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
161 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
162 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
163 STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
164 STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
165 STD_EXCEPTION(0x1500, Reserved5, UnknownException)
166 STD_EXCEPTION(0x1600, Reserved6, UnknownException)
167 STD_EXCEPTION(0x1700, Reserved7, UnknownException)
168 STD_EXCEPTION(0x1800, Reserved8, UnknownException)
169 STD_EXCEPTION(0x1900, Reserved9, UnknownException)
170 STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
171 STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
172 STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
173 STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException)
174 STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
175 STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
177 .globl _end_of_vectors
185 /* if this is a multi-core system we need to check which cpu
186 * this is, if it is not cpu 0 send the cpu to the linux reset
188 #if (CONFIG_NUM_CPUS > 1)
191 rlwinm r0,r0,27,31,31
195 bl secondary_cpu_setup
198 /* disable everything */
207 /* init the L2 cache */
208 addis r3, r0, L2_INIT@h
209 ori r3, r3, L2_INIT@l
212 #ifdef CONFIG_ALTIVEC
215 /* invalidate the L2 cache */
216 bl l2cache_invalidate
221 * Calculate absolute address in FLASH and jump there
222 *------------------------------------------------------*/
223 lis r3, CFG_MONITOR_BASE@h
224 ori r3, r3, CFG_MONITOR_BASE@l
225 addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
230 /* let the C-code set up the rest */
232 /* Be careful to keep code relocatable ! */
233 /*------------------------------------------------------*/
234 /* perform low-level init */
236 /* enable extended addressing */
243 #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
248 /* setup the law entries */
252 /* Don't use this feature due to bug in 8641D PD4 */
253 /* Disable ERD_DIS */
254 lis r3, CFG_CCSRBAR@h
261 #if (EMULATOR_RUN == 1)
262 /* On the emulator we want to adjust these ASAP */
263 /* otherwise things are sloooow */
264 /* Setup OR0 (LALE FIX)*/
265 lis r3, CFG_CCSRBAR@h
272 lis r3, CFG_CCSRBAR@h
280 /* make sure timer enabled in guts register too */
281 lis r3, CFG_CCSRBAR@h
283 ori r3,r3,0x0070 /*Jason from 3*/
285 lis r5,0xFFFC /*Jason from 0xffff*/
291 * Cache must be enabled here for stack-in-cache trick.
292 * This means we need to enable the BATS.
293 * Cache should be turned on after BATs, since by default
294 * everything is write-through.
297 /* enable address translation */
301 /* enable and invalidate the data cache */
302 /* bl l1dcache_enable */
310 #ifdef CFG_INIT_RAM_LOCK
315 /* set up the stack pointer in our newly created
317 lis r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h
318 ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l
320 li r0, 0 /* Make room for stack frame header and */
321 stwu r0, -4(r1) /* clear final stack frame so that */
322 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
324 GET_GOT /* initialize GOT access */
326 /* run low-level CPU init code (from Flash) */
332 /* Sri: Code to run the diagnostic automatically */
334 /* Load PX_AUX register address in r4 */
337 /* Load contents of PX_AUX in r3 bits 24 to 31*/
340 /* Mask and obtain the bit in r3 */
341 rlwinm. r3, r3, 0, 24, 24
342 /* If not zero, jump and continue with u-boot */
345 /* Load back contents of PX_AUX in r3 bits 24 to 31 */
347 /* Set the MSB of the register value */
349 /* Write value in r3 back to PX_AUX */
352 /* Get the address to jump to in r3*/
353 lis r3, CFG_DIAG_ADDR@h
354 ori r3, r3, CFG_DIAG_ADDR@l
356 /* Load the LR with the branch address */
359 /* Branch to diagnostic */
365 /* bl l2cache_enable*/
369 /* run 1st part of board init code (from Flash) */
375 .globl invalidate_bats
378 /* invalidate BATs */
403 /* setup_bats - set them up to some initial state */
410 addis r4, r0, CFG_IBAT0L@h
411 ori r4, r4, CFG_IBAT0L@l
412 addis r3, r0, CFG_IBAT0U@h
413 ori r3, r3, CFG_IBAT0U@l
419 addis r4, r0, CFG_DBAT0L@h
420 ori r4, r4, CFG_DBAT0L@l
421 addis r3, r0, CFG_DBAT0U@h
422 ori r3, r3, CFG_DBAT0U@l
428 addis r4, r0, CFG_IBAT1L@h
429 ori r4, r4, CFG_IBAT1L@l
430 addis r3, r0, CFG_IBAT1U@h
431 ori r3, r3, CFG_IBAT1U@l
437 addis r4, r0, CFG_DBAT1L@h
438 ori r4, r4, CFG_DBAT1L@l
439 addis r3, r0, CFG_DBAT1U@h
440 ori r3, r3, CFG_DBAT1U@l
446 addis r4, r0, CFG_IBAT2L@h
447 ori r4, r4, CFG_IBAT2L@l
448 addis r3, r0, CFG_IBAT2U@h
449 ori r3, r3, CFG_IBAT2U@l
455 addis r4, r0, CFG_DBAT2L@h
456 ori r4, r4, CFG_DBAT2L@l
457 addis r3, r0, CFG_DBAT2U@h
458 ori r3, r3, CFG_DBAT2U@l
464 addis r4, r0, CFG_IBAT3L@h
465 ori r4, r4, CFG_IBAT3L@l
466 addis r3, r0, CFG_IBAT3U@h
467 ori r3, r3, CFG_IBAT3U@l
473 addis r4, r0, CFG_DBAT3L@h
474 ori r4, r4, CFG_DBAT3L@l
475 addis r3, r0, CFG_DBAT3U@h
476 ori r3, r3, CFG_DBAT3U@l
482 addis r4, r0, CFG_IBAT4L@h
483 ori r4, r4, CFG_IBAT4L@l
484 addis r3, r0, CFG_IBAT4U@h
485 ori r3, r3, CFG_IBAT4U@l
491 addis r4, r0, CFG_DBAT4L@h
492 ori r4, r4, CFG_DBAT4L@l
493 addis r3, r0, CFG_DBAT4U@h
494 ori r3, r3, CFG_DBAT4U@l
500 addis r4, r0, CFG_IBAT5L@h
501 ori r4, r4, CFG_IBAT5L@l
502 addis r3, r0, CFG_IBAT5U@h
503 ori r3, r3, CFG_IBAT5U@l
509 addis r4, r0, CFG_DBAT5L@h
510 ori r4, r4, CFG_DBAT5L@l
511 addis r3, r0, CFG_DBAT5U@h
512 ori r3, r3, CFG_DBAT5U@l
518 addis r4, r0, CFG_IBAT6L@h
519 ori r4, r4, CFG_IBAT6L@l
520 addis r3, r0, CFG_IBAT6U@h
521 ori r3, r3, CFG_IBAT6U@l
527 addis r4, r0, CFG_DBAT6L@h
528 ori r4, r4, CFG_DBAT6L@l
529 addis r3, r0, CFG_DBAT6U@h
530 ori r3, r3, CFG_DBAT6U@l
536 addis r4, r0, CFG_IBAT7L@h
537 ori r4, r4, CFG_IBAT7L@l
538 addis r3, r0, CFG_IBAT7U@h
539 ori r3, r3, CFG_IBAT7U@l
545 addis r4, r0, CFG_DBAT7L@h
546 ori r4, r4, CFG_DBAT7L@l
547 addis r3, r0, CFG_DBAT7U@h
548 ori r3, r3, CFG_DBAT7U@l
555 addis r5, 0, 0x4 /* upper bound of 0x00040000 for 7400/750 */
567 .globl enable_addr_trans
569 /* enable address translation */
571 ori r5, r5, (MSR_IR | MSR_DR)
576 .globl disable_addr_trans
578 /* disable address translation */
581 andi. r0, r3, (MSR_IR | MSR_DR)
589 * This code finishes saving the registers to the exception frame
590 * and jumps to the appropriate handler for the exception.
591 * Register r21 is pointer into trap frame, r1 has new stack pointer.
593 .globl transfer_to_handler
604 andi. r24,r23,0x3f00 /* get vector offset */
608 mtspr SPRG2,r22 /* r1 is now kernel sp */
609 lwz r24,0(r23) /* virtual address of handler */
610 lwz r23,4(r23) /* where to go when done */
615 rfi /* jump to handler, enable MMU */
618 mfmsr r28 /* Disable interrupts */
622 SYNC /* Some chip revs need this... */
637 lwz r2,_NIP(r1) /* Restore environment */
662 /*------------------------------------------------------------------------------- */
664 /* Description: Input 8 bits */
665 /*------------------------------------------------------------------------------- */
671 /*------------------------------------------------------------------------------- */
673 /* Description: Output 8 bits */
674 /*------------------------------------------------------------------------------- */
680 /*------------------------------------------------------------------------------- */
681 /* Function: out16 */
682 /* Description: Output 16 bits */
683 /*------------------------------------------------------------------------------- */
689 /*------------------------------------------------------------------------------- */
690 /* Function: out16r */
691 /* Description: Byte reverse and output 16 bits */
692 /*------------------------------------------------------------------------------- */
698 /*------------------------------------------------------------------------------- */
699 /* Function: out32 */
700 /* Description: Output 32 bits */
701 /*------------------------------------------------------------------------------- */
707 /*------------------------------------------------------------------------------- */
708 /* Function: out32r */
709 /* Description: Byte reverse and output 32 bits */
710 /*------------------------------------------------------------------------------- */
716 /*------------------------------------------------------------------------------- */
718 /* Description: Input 16 bits */
719 /*------------------------------------------------------------------------------- */
725 /*------------------------------------------------------------------------------- */
726 /* Function: in16r */
727 /* Description: Input 16 bits and byte reverse */
728 /*------------------------------------------------------------------------------- */
734 /*------------------------------------------------------------------------------- */
736 /* Description: Input 32 bits */
737 /*------------------------------------------------------------------------------- */
743 /*------------------------------------------------------------------------------- */
744 /* Function: in32r */
745 /* Description: Input 32 bits and byte reverse */
746 /*------------------------------------------------------------------------------- */
752 /*------------------------------------------------------------------------------- */
753 /* Function: ppcDcbf */
754 /* Description: Data Cache block flush */
755 /* Input: r3 = effective address */
757 /*------------------------------------------------------------------------------- */
763 /*------------------------------------------------------------------------------- */
764 /* Function: ppcDcbi */
765 /* Description: Data Cache block Invalidate */
766 /* Input: r3 = effective address */
768 /*------------------------------------------------------------------------------- */
774 /*--------------------------------------------------------------------------
776 * Description: Data Cache block zero.
777 * Input: r3 = effective address
779 *-------------------------------------------------------------------------- */
786 /*-------------------------------------------------------------------------- */
787 /* Function: ppcSync */
788 /* Description: Processor Synchronize */
791 /*-------------------------------------------------------------------------- */
797 /*-----------------------------------------------------------------------*/
799 * void relocate_code (addr_sp, gd, addr_moni)
801 * This "function" does not return, instead it continues in RAM
802 * after relocating the monitor code.
806 * r5 = length in bytes
812 mr r1, r3 /* Set new stack pointer */
813 mr r9, r4 /* Save copy of Global Data pointer */
814 mr r10, r5 /* Save copy of Destination Address */
816 mr r3, r5 /* Destination Address */
817 lis r4, CFG_MONITOR_BASE@h /* Source Address */
818 ori r4, r4, CFG_MONITOR_BASE@l
819 lwz r5, GOT(__init_end)
821 li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
826 * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
832 /* First our own GOT */
834 /* then the one used by the C code */
841 bl board_relocate_rom
843 mr r3, r10 /* Destination Address */
844 lis r4, CFG_MONITOR_BASE@h /* Source Address */
845 ori r4, r4, CFG_MONITOR_BASE@l
846 lwz r5, GOT(__init_end)
848 li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
853 beq cr1,4f /* In place copy is not necessary */
854 beq 7f /* Protect against 0 count */
873 * Now flush the cache: note that we must start from a cache aligned
874 * address. Otherwise we might miss one cache line.
878 beq 7f /* Always flush prefetch queue in any case */
886 sync /* Wait for all dcbst to complete on bus */
892 7: sync /* Wait for all icbi to complete on bus */
896 * We are done. Do not return, instead branch to second part of board
897 * initialization, now running from RAM.
899 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
908 * Relocation Function, r14 point to got2+0x8000
910 * Adjust got2 pointers, no need to check for 0, this code
911 * already puts a few entries in the table.
913 li r0,__got2_entries@sectoff@l
914 la r3,GOT(_GOT2_TABLE_)
915 lwz r11,GOT(_GOT2_TABLE_)
925 * Now adjust the fixups and the pointers to the fixups
926 * in case we need to move ourselves again.
928 2: li r0,__fixup_entries@sectoff@l
929 lwz r3,GOT(_FIXUP_TABLE_)
943 * Now clear BSS segment
945 lwz r3,GOT(__bss_start)
958 mr r3, r9 /* Init Date pointer */
959 mr r4, r10 /* Destination Address */
962 /* not reached - end relocate_code */
963 /*-----------------------------------------------------------------------*/
966 * Copy exception vector code to low memory
969 * r7: source address, r8: end address, r9: target address
974 lwz r8, GOT(_end_of_vectors)
976 li r9, 0x100 /* reset vector always at 0x100 */
979 bgelr /* return if r7>=r8 - just in case */
981 mflr r4 /* save link register */
991 * relocate `hdlr' and `int_return' entries
993 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
994 li r8, Alignment - _start + EXC_OFF_SYS_RESET
997 addi r7, r7, 0x100 /* next exception vector */
1001 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
1004 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
1007 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
1008 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
1011 addi r7, r7, 0x100 /* next exception vector */
1015 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
1016 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
1019 addi r7, r7, 0x100 /* next exception vector */
1023 /* enable execptions from RAM vectors */
1029 mtlr r4 /* restore link register */
1033 * Function: relocate entries for one exception vector
1036 lwz r0, 0(r7) /* hdlr ... */
1037 add r0, r0, r3 /* ... += dest_addr */
1040 lwz r0, 4(r7) /* int_return ... */
1041 add r0, r0, r3 /* ... += dest_addr */
1049 .globl enable_ext_addr
1052 lis r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@h
1053 ori r0, r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@l
1059 #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
1060 .globl setup_ccsrbar
1062 /* Special sequence needed to update CCSRBAR itself */
1063 lis r4, CFG_CCSRBAR_DEFAULT@h
1064 ori r4, r4, CFG_CCSRBAR_DEFAULT@l
1066 lis r5, CFG_CCSRBAR@h
1067 ori r5, r5, CFG_CCSRBAR@l
1077 lis r3, CFG_CCSRBAR@h
1078 lwz r5, CFG_CCSRBAR@l(r3)
1084 #ifdef CFG_INIT_RAM_LOCK
1086 /* Allocate Initial RAM in data cache.
1088 lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
1089 ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
1090 li r2, ((CFG_INIT_RAM_END & ~31) + \
1091 (CFG_INIT_RAM_ADDR & 31) + 31) / 32
1098 /* Lock the data cache */
1107 /* Lock the first way of the data cache */
1110 #if defined(CONFIG_ALTIVEC)
1120 .globl unlock_ram_in_cache
1121 unlock_ram_in_cache:
1122 /* invalidate the INIT_RAM section */
1123 lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
1124 ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
1125 li r2, ((CFG_INIT_RAM_END & ~31) + \
1126 (CFG_INIT_RAM_ADDR & 31) + 31) / 32
1131 sync /* Wait for all icbi to complete on bus */
1134 /* Unlock the data cache and invalidate it */
1146 /* Unlock the first way of the data cache */
1150 #ifdef CONFIG_ALTIVEC
1166 /* If this is a multi-cpu system then we need to handle the
1167 * 2nd cpu. The assumption is that the 2nd cpu is being
1168 * held in boot holdoff mode until the 1st cpu unlocks it
1169 * from Linux. We'll do some basic cpu init and then pass
1170 * it to the Linux Reset Vector.
1171 * Sri: Much of this initialization is not required. Linux
1172 * rewrites the bats, and the sprs and also enables the L1 cache.
1174 #if (CONFIG_NUM_CPUS > 1)
1175 .globl secondary_cpu_setup
1176 secondary_cpu_setup:
1177 /* Do only core setup on all cores except cpu0 */
1183 /* init the L2 cache */
1184 addis r3, r0, L2_INIT@h
1185 ori r3, r3, L2_INIT@l
1188 #ifdef CONFIG_ALTIVEC
1191 /* invalidate the L2 cache */
1192 bl l2cache_invalidate
1196 /* setup the bats */
1199 /* enable address translation */
1200 bl enable_addr_trans
1203 /* enable and invalidate the data cache */
1207 /* enable and invalidate the instruction cache*/
1211 /* Set up MSR and HID0, HID1*/
1212 /* Enable interrupts */
1227 /*SYNCBE|ABE in HID1*/
1234 lis r3, CONFIG_LINUX_RESET_VEC@h
1235 ori r3, r3, CONFIG_LINUX_RESET_VEC@l
1239 /* Never Returns, Running in Linux Now */