2 * Copyright 2008 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
10 #include <asm/fsl_ddr_sdram.h>
14 /* Board-specific functions defined in each board's ddr.c */
15 extern void fsl_ddr_board_options(memctl_options_t *popts,
16 unsigned int ctrl_num);
18 unsigned int populate_memctl_options(int all_DIMMs_registered,
19 memctl_options_t *popts,
20 unsigned int ctrl_num)
24 /* Chip select options. */
26 /* Pick chip-select local options. */
27 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
28 /* If not DDR2, odt_rd_cfg and odt_wr_cfg need to be 0. */
30 /* only for single CS? */
31 popts->cs_local_opts[i].odt_rd_cfg = 0;
33 popts->cs_local_opts[i].odt_wr_cfg = 1;
34 popts->cs_local_opts[i].auto_precharge = 0;
37 /* Pick interleaving mode. */
41 * 1 = interleaving between 2 controllers
43 popts->memctl_interleaving = 0;
49 * 3 = superbank (only if CS interleaving is enabled)
51 popts->memctl_interleaving_mode = 0;
54 * 0: cacheline: bit 30 of the 36-bit physical addr selects the memctl
55 * 1: page: bit to the left of the column bits selects the memctl
56 * 2: bank: bit to the left of the bank bits selects the memctl
57 * 3: superbank: bit to the left of the chip select selects the memctl
59 * NOTE: ba_intlv (rank interleaving) is independent of memory
60 * controller interleaving; it is only within a memory controller.
61 * Must use superbank interleaving if rank interleaving is used and
62 * memory controller interleaving is enabled.
69 * 0x60 = CS0,CS1 + CS2,CS3
70 * 0x04 = CS0,CS1,CS2,CS3
72 popts->ba_intlv_ctl = 0;
74 /* Memory Organization Parameters */
75 popts->registered_dimm_en = all_DIMMs_registered;
77 /* Operational Mode Paramters */
81 popts->ECC_mode = 1; /* 0 = disabled, 1 = enabled */
83 popts->ECC_mode = 0; /* 0 = disabled, 1 = enabled */
85 popts->ECC_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */
92 #if defined(CONFIG_FSL_DDR1)
93 popts->DQS_config = 0;
94 #elif defined(CONFIG_FSL_DDR2)
95 popts->DQS_config = 1;
97 #error "Fix DQS for DDR3"
100 /* Choose self-refresh during sleep. */
101 popts->self_refresh_in_sleep = 1;
103 /* Choose dynamic power management mode. */
104 popts->dynamic_power = 0;
106 /* 0 = 64-bit, 1 = 32-bit, 2 = 16-bit */
107 popts->data_bus_width = 0;
109 /* Choose burst length. */
110 popts->burst_length = 4; /* has to be 4 for DDR2 */
112 /* Global Timing Parameters. */
113 debug("mclk_ps = %u ps\n", get_memory_clk_period_ps());
115 /* Pick a caslat override. */
116 popts->cas_latency_override = 0;
117 popts->cas_latency_override_value = 3;
118 if (popts->cas_latency_override) {
119 debug("using caslat override value = %u\n",
120 popts->cas_latency_override_value);
123 /* Decide whether to use the computed derated latency */
124 popts->use_derated_caslat = 0;
126 /* Choose an additive latency. */
127 popts->additive_latency_override = 0;
128 popts->additive_latency_override_value = 3;
129 if (popts->additive_latency_override) {
130 debug("using additive latency override value = %u\n",
131 popts->additive_latency_override_value);
137 * Factors to consider for 2T_EN:
138 * - number of DIMMs installed
139 * - number of components, number of active ranks
140 * - how much time you want to spend playing around
143 popts->threeT_en = 0;
146 * BSTTOPRE precharge interval
148 * Set this to 0 for global auto precharge
150 * FIXME: Should this be configured in picoseconds?
151 * Why it should be in ps: better understanding of this
152 * relative to actual DRAM timing parameters such as tRAS.
153 * e.g. tRAS(min) = 40 ns
155 popts->bstopre = 0x100;
157 /* Minimum CKE pulse width -- tCKE(MIN) */
158 popts->tCKE_clock_pulse_width_ps
159 = mclk_to_picos(FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR);
162 * Window for four activates -- tFAW
164 * FIXME: UM: applies only to DDR2/DDR3 with eight logical banks only
165 * FIXME: varies depending upon number of column addresses or data
166 * FIXME: width, was considering looking at pdimm->primary_sdram_width
168 #if defined(CONFIG_FSL_DDR1)
169 popts->tFAW_window_four_activates_ps = mclk_to_picos(1);
171 #elif defined(CONFIG_FSL_DDR2)
173 * x4/x8; some datasheets have 35000
174 * x16 wide columns only? Use 50000?
176 popts->tFAW_window_four_activates_ps = 37500;
178 #elif defined(CONFIG_FSL_DDR3)
179 #error "FIXME determine four activates for DDR3"
182 /* ODT should only be used for DDR2 */
187 * Interleaving checks.
189 * If memory controller interleaving is enabled, then the data
190 * bus widths must be programmed identically for the 2 memory
194 fsl_ddr_board_options(popts, ctrl_num);