2 * cpu/ppc4xx/44x_spd_ddr2.c
3 * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
4 * DDR2 controller (non Denali Core). Those are 440SP/SPe.
7 * Stefan Roese, DENX Software Engineering, sr@denx.de.
9 * COPYRIGHT AMCC CORPORATION 2004
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 /* define DEBUG for debugging output (obviously ;-)) */
41 #include <asm/processor.h>
44 #if defined(CONFIG_SPD_EEPROM) && \
45 (defined(CONFIG_440SP) || defined(CONFIG_440SPE))
47 /*-----------------------------------------------------------------------------+
49 *-----------------------------------------------------------------------------*/
64 #define MAX_SPD_BYTES 256 /* Max number of bytes on the DIMM's SPD EEPROM */
66 #define ONE_BILLION 1000000000
68 #define MULDIV64(m1, m2, d) (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
70 #define CMD_NOP (7 << 19)
71 #define CMD_PRECHARGE (2 << 19)
72 #define CMD_REFRESH (1 << 19)
73 #define CMD_EMR (0 << 19)
74 #define CMD_READ (5 << 19)
75 #define CMD_WRITE (4 << 19)
77 #define SELECT_MR (0 << 16)
78 #define SELECT_EMR (1 << 16)
79 #define SELECT_EMR2 (2 << 16)
80 #define SELECT_EMR3 (3 << 16)
83 #define DLL_RESET 0x00000100
85 #define WRITE_RECOV_2 (1 << 9)
86 #define WRITE_RECOV_3 (2 << 9)
87 #define WRITE_RECOV_4 (3 << 9)
88 #define WRITE_RECOV_5 (4 << 9)
89 #define WRITE_RECOV_6 (5 << 9)
91 #define BURST_LEN_4 0x00000002
94 #define ODT_0_OHM 0x00000000
95 #define ODT_50_OHM 0x00000044
96 #define ODT_75_OHM 0x00000004
97 #define ODT_150_OHM 0x00000040
99 #define ODS_FULL 0x00000000
100 #define ODS_REDUCED 0x00000002
102 /* defines for ODT (On Die Termination) of the 440SP(e) DDR2 controller */
103 #define ODT_EB0R (0x80000000 >> 8)
104 #define ODT_EB0W (0x80000000 >> 7)
105 #define CALC_ODT_R(n) (ODT_EB0R << (n << 1))
106 #define CALC_ODT_W(n) (ODT_EB0W << (n << 1))
107 #define CALC_ODT_RW(n) (CALC_ODT_R(n) | CALC_ODT_W(n))
109 /* Defines for the Read Cycle Delay test */
110 #define NUMMEMTESTS 8
111 #define NUMMEMWORDS 8
112 #define NUMLOOPS 256 /* memory test loops */
114 #undef CONFIG_ECC_ERROR_RESET /* test-only: see description below, at check_ecc() */
117 * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
118 * region. Right now the cache should still be disabled in U-Boot because of the
119 * EMAC driver, that need it's buffer descriptor to be located in non cached
122 * If at some time this restriction doesn't apply anymore, just define
123 * CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup
124 * everything correctly.
126 #ifdef CFG_ENABLE_SDRAM_CACHE
127 #define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */
129 #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
132 #if defined(CONFIG_PPC4xx_USE_SPD_DDR_INIT_HANG)
133 extern void spd_ddr_init_hang (void);
134 #define HANG() spd_ddr_init_hang()
136 #define HANG() hang()
139 /* Private Structure Definitions */
141 /* enum only to ease code for cas latency setting */
142 typedef enum ddr_cas_id {
150 /*-----------------------------------------------------------------------------+
152 *-----------------------------------------------------------------------------*/
153 static unsigned long sdram_memsize(void);
154 void program_tlb(u32 start, u32 size, u32 tlb_word2_i_value);
155 static void get_spd_info(unsigned long *dimm_populated,
156 unsigned char *iic0_dimm_addr,
157 unsigned long num_dimm_banks);
158 static void check_mem_type(unsigned long *dimm_populated,
159 unsigned char *iic0_dimm_addr,
160 unsigned long num_dimm_banks);
161 static void check_frequency(unsigned long *dimm_populated,
162 unsigned char *iic0_dimm_addr,
163 unsigned long num_dimm_banks);
164 static void check_rank_number(unsigned long *dimm_populated,
165 unsigned char *iic0_dimm_addr,
166 unsigned long num_dimm_banks);
167 static void check_voltage_type(unsigned long *dimm_populated,
168 unsigned char *iic0_dimm_addr,
169 unsigned long num_dimm_banks);
170 static void program_memory_queue(unsigned long *dimm_populated,
171 unsigned char *iic0_dimm_addr,
172 unsigned long num_dimm_banks);
173 static void program_codt(unsigned long *dimm_populated,
174 unsigned char *iic0_dimm_addr,
175 unsigned long num_dimm_banks);
176 static void program_mode(unsigned long *dimm_populated,
177 unsigned char *iic0_dimm_addr,
178 unsigned long num_dimm_banks,
179 ddr_cas_id_t *selected_cas,
180 int *write_recovery);
181 static void program_tr(unsigned long *dimm_populated,
182 unsigned char *iic0_dimm_addr,
183 unsigned long num_dimm_banks);
184 static void program_rtr(unsigned long *dimm_populated,
185 unsigned char *iic0_dimm_addr,
186 unsigned long num_dimm_banks);
187 static void program_bxcf(unsigned long *dimm_populated,
188 unsigned char *iic0_dimm_addr,
189 unsigned long num_dimm_banks);
190 static void program_copt1(unsigned long *dimm_populated,
191 unsigned char *iic0_dimm_addr,
192 unsigned long num_dimm_banks);
193 static void program_initplr(unsigned long *dimm_populated,
194 unsigned char *iic0_dimm_addr,
195 unsigned long num_dimm_banks,
196 ddr_cas_id_t selected_cas,
198 static unsigned long is_ecc_enabled(void);
199 #ifdef CONFIG_DDR_ECC
200 static void program_ecc(unsigned long *dimm_populated,
201 unsigned char *iic0_dimm_addr,
202 unsigned long num_dimm_banks,
203 unsigned long tlb_word2_i_value);
204 static void program_ecc_addr(unsigned long start_address,
205 unsigned long num_bytes,
206 unsigned long tlb_word2_i_value);
208 static void program_DQS_calibration(unsigned long *dimm_populated,
209 unsigned char *iic0_dimm_addr,
210 unsigned long num_dimm_banks);
211 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
212 static void test(void);
214 static void DQS_calibration_process(void);
217 static void ppc440sp_sdram_register_dump(void);
219 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
220 void dcbz_area(u32 start_address, u32 num_bytes);
223 static u32 mfdcr_any(u32 dcr)
228 case SDRAM_R0BAS + 0:
229 val = mfdcr(SDRAM_R0BAS + 0);
231 case SDRAM_R0BAS + 1:
232 val = mfdcr(SDRAM_R0BAS + 1);
234 case SDRAM_R0BAS + 2:
235 val = mfdcr(SDRAM_R0BAS + 2);
237 case SDRAM_R0BAS + 3:
238 val = mfdcr(SDRAM_R0BAS + 3);
241 printf("DCR %d not defined in case statement!!!\n", dcr);
242 val = 0; /* just to satisfy the compiler */
248 static void mtdcr_any(u32 dcr, u32 val)
251 case SDRAM_R0BAS + 0:
252 mtdcr(SDRAM_R0BAS + 0, val);
254 case SDRAM_R0BAS + 1:
255 mtdcr(SDRAM_R0BAS + 1, val);
257 case SDRAM_R0BAS + 2:
258 mtdcr(SDRAM_R0BAS + 2, val);
260 case SDRAM_R0BAS + 3:
261 mtdcr(SDRAM_R0BAS + 3, val);
264 printf("DCR %d not defined in case statement!!!\n", dcr);
268 static unsigned char spd_read(uchar chip, uint addr)
270 unsigned char data[2];
272 if (i2c_probe(chip) == 0)
273 if (i2c_read(chip, addr, 1, data, 1) == 0)
279 /*-----------------------------------------------------------------------------+
281 *-----------------------------------------------------------------------------*/
282 static unsigned long sdram_memsize(void)
284 unsigned long mem_size;
285 unsigned long mcopt2;
286 unsigned long mcstat;
293 mfsdram(SDRAM_MCOPT2, mcopt2);
294 mfsdram(SDRAM_MCSTAT, mcstat);
296 /* DDR controller must be enabled and not in self-refresh. */
297 /* Otherwise memsize is zero. */
298 if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
299 && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
300 && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
301 == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
302 for (i = 0; i < MAXBXCF; i++) {
303 mfsdram(SDRAM_MB0CF + (i << 2), mb0cf);
305 if ((mb0cf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
306 sdsz = mfdcr_any(SDRAM_R0BAS + i) & SDRAM_RXBAS_SDSZ_MASK;
309 case SDRAM_RXBAS_SDSZ_8:
312 case SDRAM_RXBAS_SDSZ_16:
315 case SDRAM_RXBAS_SDSZ_32:
318 case SDRAM_RXBAS_SDSZ_64:
321 case SDRAM_RXBAS_SDSZ_128:
324 case SDRAM_RXBAS_SDSZ_256:
327 case SDRAM_RXBAS_SDSZ_512:
330 case SDRAM_RXBAS_SDSZ_1024:
333 case SDRAM_RXBAS_SDSZ_2048:
336 case SDRAM_RXBAS_SDSZ_4096:
347 mem_size *= 1024 * 1024;
351 /*-----------------------------------------------------------------------------+
352 * initdram. Initializes the 440SP Memory Queue and DDR SDRAM controller.
353 * Note: This routine runs from flash with a stack set up in the chip's
354 * sram space. It is important that the routine does not require .sbss, .bss or
355 * .data sections. It also cannot call routines that require these sections.
356 *-----------------------------------------------------------------------------*/
357 /*-----------------------------------------------------------------------------
359 * Description: Configures SDRAM memory banks for DDR operation.
360 * Auto Memory Configuration option reads the DDR SDRAM EEPROMs
361 * via the IIC bus and then configures the DDR SDRAM memory
362 * banks appropriately. If Auto Memory Configuration is
363 * not used, it is assumed that no DIMM is plugged
364 *-----------------------------------------------------------------------------*/
365 long int initdram(int board_type)
367 unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
368 unsigned char spd0[MAX_SPD_BYTES];
369 unsigned char spd1[MAX_SPD_BYTES];
370 unsigned char *dimm_spd[MAXDIMMS];
371 unsigned long dimm_populated[MAXDIMMS];
372 unsigned long num_dimm_banks; /* on board dimm banks */
374 ddr_cas_id_t selected_cas;
376 unsigned long dram_size = 0;
378 num_dimm_banks = sizeof(iic0_dimm_addr);
380 /*------------------------------------------------------------------
381 * Set up an array of SPD matrixes.
382 *-----------------------------------------------------------------*/
386 /*------------------------------------------------------------------
387 * Reset the DDR-SDRAM controller.
388 *-----------------------------------------------------------------*/
389 mtsdr(SDR0_SRST, (0x80000000 >> 10));
390 mtsdr(SDR0_SRST, 0x00000000);
393 * Make sure I2C controller is initialized
397 /* switch to correct I2C bus */
398 I2C_SET_BUS(CFG_SPD_BUS_NUM);
399 i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
401 /*------------------------------------------------------------------
402 * Clear out the serial presence detect buffers.
403 * Perform IIC reads from the dimm. Fill in the spds.
404 * Check to see if the dimm slots are populated
405 *-----------------------------------------------------------------*/
406 get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
408 /*------------------------------------------------------------------
409 * Check the memory type for the dimms plugged.
410 *-----------------------------------------------------------------*/
411 check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
413 /*------------------------------------------------------------------
414 * Check the frequency supported for the dimms plugged.
415 *-----------------------------------------------------------------*/
416 check_frequency(dimm_populated, iic0_dimm_addr, num_dimm_banks);
418 /*------------------------------------------------------------------
419 * Check the total rank number.
420 *-----------------------------------------------------------------*/
421 check_rank_number(dimm_populated, iic0_dimm_addr, num_dimm_banks);
423 /*------------------------------------------------------------------
424 * Check the voltage type for the dimms plugged.
425 *-----------------------------------------------------------------*/
426 check_voltage_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
428 /*------------------------------------------------------------------
429 * Program SDRAM controller options 2 register
430 * Except Enabling of the memory controller.
431 *-----------------------------------------------------------------*/
432 mfsdram(SDRAM_MCOPT2, val);
433 mtsdram(SDRAM_MCOPT2,
435 ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_PMEN_MASK |
436 SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_XSRP_MASK |
437 SDRAM_MCOPT2_ISIE_MASK))
438 | (SDRAM_MCOPT2_SREN_ENTER | SDRAM_MCOPT2_PMEN_DISABLE |
439 SDRAM_MCOPT2_IPTR_IDLE | SDRAM_MCOPT2_XSRP_ALLOW |
440 SDRAM_MCOPT2_ISIE_ENABLE));
442 /*------------------------------------------------------------------
443 * Program SDRAM controller options 1 register
444 * Note: Does not enable the memory controller.
445 *-----------------------------------------------------------------*/
446 program_copt1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
448 /*------------------------------------------------------------------
449 * Set the SDRAM Controller On Die Termination Register
450 *-----------------------------------------------------------------*/
451 program_codt(dimm_populated, iic0_dimm_addr, num_dimm_banks);
453 /*------------------------------------------------------------------
454 * Program SDRAM refresh register.
455 *-----------------------------------------------------------------*/
456 program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
458 /*------------------------------------------------------------------
459 * Program SDRAM mode register.
460 *-----------------------------------------------------------------*/
461 program_mode(dimm_populated, iic0_dimm_addr, num_dimm_banks,
462 &selected_cas, &write_recovery);
464 /*------------------------------------------------------------------
465 * Set the SDRAM Write Data/DM/DQS Clock Timing Reg
466 *-----------------------------------------------------------------*/
467 mfsdram(SDRAM_WRDTR, val);
468 mtsdram(SDRAM_WRDTR, (val & ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) |
469 (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV));
471 /*------------------------------------------------------------------
472 * Set the SDRAM Clock Timing Register
473 *-----------------------------------------------------------------*/
474 mfsdram(SDRAM_CLKTR, val);
475 #ifdef CFG_44x_DDR2_CKTR_180
476 mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) | SDRAM_CLKTR_CLKP_180_DEG_ADV);
478 mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) | SDRAM_CLKTR_CLKP_0_DEG);
481 /*------------------------------------------------------------------
482 * Program the BxCF registers.
483 *-----------------------------------------------------------------*/
484 program_bxcf(dimm_populated, iic0_dimm_addr, num_dimm_banks);
486 /*------------------------------------------------------------------
487 * Program SDRAM timing registers.
488 *-----------------------------------------------------------------*/
489 program_tr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
491 /*------------------------------------------------------------------
492 * Set the Extended Mode register
493 *-----------------------------------------------------------------*/
494 mfsdram(SDRAM_MEMODE, val);
495 mtsdram(SDRAM_MEMODE,
496 (val & ~(SDRAM_MEMODE_DIC_MASK | SDRAM_MEMODE_DLL_MASK |
497 SDRAM_MEMODE_RTT_MASK | SDRAM_MEMODE_DQS_MASK)) |
498 (SDRAM_MEMODE_DIC_NORMAL | SDRAM_MEMODE_DLL_ENABLE
499 | SDRAM_MEMODE_RTT_150OHM | SDRAM_MEMODE_DQS_ENABLE));
501 /*------------------------------------------------------------------
502 * Program Initialization preload registers.
503 *-----------------------------------------------------------------*/
504 program_initplr(dimm_populated, iic0_dimm_addr, num_dimm_banks,
505 selected_cas, write_recovery);
507 /*------------------------------------------------------------------
508 * Delay to ensure 200usec have elapsed since reset.
509 *-----------------------------------------------------------------*/
512 /*------------------------------------------------------------------
513 * Set the memory queue core base addr.
514 *-----------------------------------------------------------------*/
515 program_memory_queue(dimm_populated, iic0_dimm_addr, num_dimm_banks);
517 /*------------------------------------------------------------------
518 * Program SDRAM controller options 2 register
519 * Enable the memory controller.
520 *-----------------------------------------------------------------*/
521 mfsdram(SDRAM_MCOPT2, val);
522 mtsdram(SDRAM_MCOPT2,
523 (val & ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_DCEN_MASK |
524 SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_ISIE_MASK)) |
525 (SDRAM_MCOPT2_DCEN_ENABLE | SDRAM_MCOPT2_IPTR_EXECUTE));
527 /*------------------------------------------------------------------
528 * Wait for SDRAM_CFG0_DC_EN to complete.
529 *-----------------------------------------------------------------*/
531 mfsdram(SDRAM_MCSTAT, val);
532 } while ((val & SDRAM_MCSTAT_MIC_MASK) == SDRAM_MCSTAT_MIC_NOTCOMP);
534 /* get installed memory size */
535 dram_size = sdram_memsize();
537 /* and program tlb entries for this size (dynamic) */
538 program_tlb(0, dram_size, MY_TLB_WORD2_I_ENABLE);
540 /*------------------------------------------------------------------
542 *-----------------------------------------------------------------*/
543 program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks);
545 #ifdef CONFIG_DDR_ECC
546 /*------------------------------------------------------------------
547 * If ecc is enabled, initialize the parity bits.
548 *-----------------------------------------------------------------*/
549 program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, MY_TLB_WORD2_I_ENABLE);
553 ppc440sp_sdram_register_dump();
559 static void get_spd_info(unsigned long *dimm_populated,
560 unsigned char *iic0_dimm_addr,
561 unsigned long num_dimm_banks)
563 unsigned long dimm_num;
564 unsigned long dimm_found;
565 unsigned char num_of_bytes;
566 unsigned char total_size;
569 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
573 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
574 debug("\nspd_read(0x%x) returned %d\n",
575 iic0_dimm_addr[dimm_num], num_of_bytes);
576 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
577 debug("spd_read(0x%x) returned %d\n",
578 iic0_dimm_addr[dimm_num], total_size);
580 if ((num_of_bytes != 0) && (total_size != 0)) {
581 dimm_populated[dimm_num] = TRUE;
583 debug("DIMM slot %lu: populated\n", dimm_num);
585 dimm_populated[dimm_num] = FALSE;
586 debug("DIMM slot %lu: Not populated\n", dimm_num);
590 if (dimm_found == FALSE) {
591 printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
596 #ifdef CONFIG_ADD_RAM_INFO
597 void board_add_ram_info(int use_default)
599 PPC440_SYS_INFO board_cfg;
602 if (is_ecc_enabled())
607 get_sys_info(&board_cfg);
609 mfsdr(SDR0_DDR0, val);
610 val = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(val), 1);
611 printf(" enabled, %d MHz", (val * 2) / 1000000);
613 mfsdram(SDRAM_MMODE, val);
614 val = (val & SDRAM_MMODE_DCL_MASK) >> 4;
615 printf(", CL%d)", val);
619 /*------------------------------------------------------------------
620 * For the memory DIMMs installed, this routine verifies that they
621 * really are DDR specific DIMMs.
622 *-----------------------------------------------------------------*/
623 static void check_mem_type(unsigned long *dimm_populated,
624 unsigned char *iic0_dimm_addr,
625 unsigned long num_dimm_banks)
627 unsigned long dimm_num;
628 unsigned long dimm_type;
630 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
631 if (dimm_populated[dimm_num] == TRUE) {
632 dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
635 printf("ERROR: Standard Fast Page Mode DRAM DIMM detected in "
636 "slot %d.\n", (unsigned int)dimm_num);
637 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
638 printf("Replace the DIMM module with a supported DIMM.\n\n");
642 printf("ERROR: EDO DIMM detected in slot %d.\n",
643 (unsigned int)dimm_num);
644 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
645 printf("Replace the DIMM module with a supported DIMM.\n\n");
649 printf("ERROR: Pipelined Nibble DIMM detected in slot %d.\n",
650 (unsigned int)dimm_num);
651 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
652 printf("Replace the DIMM module with a supported DIMM.\n\n");
656 printf("ERROR: SDRAM DIMM detected in slot %d.\n",
657 (unsigned int)dimm_num);
658 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
659 printf("Replace the DIMM module with a supported DIMM.\n\n");
663 printf("ERROR: Multiplexed ROM DIMM detected in slot %d.\n",
664 (unsigned int)dimm_num);
665 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
666 printf("Replace the DIMM module with a supported DIMM.\n\n");
670 printf("ERROR: SGRAM DIMM detected in slot %d.\n",
671 (unsigned int)dimm_num);
672 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
673 printf("Replace the DIMM module with a supported DIMM.\n\n");
677 debug("DIMM slot %d: DDR1 SDRAM detected\n", dimm_num);
678 dimm_populated[dimm_num] = SDRAM_DDR1;
681 debug("DIMM slot %d: DDR2 SDRAM detected\n", dimm_num);
682 dimm_populated[dimm_num] = SDRAM_DDR2;
685 printf("ERROR: Unknown DIMM detected in slot %d.\n",
686 (unsigned int)dimm_num);
687 printf("Only DDR1 and DDR2 SDRAM DIMMs are supported.\n");
688 printf("Replace the DIMM module with a supported DIMM.\n\n");
694 for (dimm_num = 1; dimm_num < num_dimm_banks; dimm_num++) {
695 if ((dimm_populated[dimm_num-1] != SDRAM_NONE)
696 && (dimm_populated[dimm_num] != SDRAM_NONE)
697 && (dimm_populated[dimm_num-1] != dimm_populated[dimm_num])) {
698 printf("ERROR: DIMM's DDR1 and DDR2 type can not be mixed.\n");
704 /*------------------------------------------------------------------
705 * For the memory DIMMs installed, this routine verifies that
706 * frequency previously calculated is supported.
707 *-----------------------------------------------------------------*/
708 static void check_frequency(unsigned long *dimm_populated,
709 unsigned char *iic0_dimm_addr,
710 unsigned long num_dimm_banks)
712 unsigned long dimm_num;
713 unsigned long tcyc_reg;
714 unsigned long cycle_time;
715 unsigned long calc_cycle_time;
716 unsigned long sdram_freq;
717 unsigned long sdr_ddrpll;
718 PPC440_SYS_INFO board_cfg;
720 /*------------------------------------------------------------------
721 * Get the board configuration info.
722 *-----------------------------------------------------------------*/
723 get_sys_info(&board_cfg);
725 mfsdr(SDR0_DDR0, sdr_ddrpll);
726 sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
729 * calc_cycle_time is calculated from DDR frequency set by board/chip
730 * and is expressed in multiple of 10 picoseconds
731 * to match the way DIMM cycle time is calculated below.
733 calc_cycle_time = MULDIV64(ONE_BILLION, 100, sdram_freq);
735 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
736 if (dimm_populated[dimm_num] != SDRAM_NONE) {
737 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
739 * Byte 9, Cycle time for CAS Latency=X, is split into two nibbles:
740 * the higher order nibble (bits 4-7) designates the cycle time
741 * to a granularity of 1ns;
742 * the value presented by the lower order nibble (bits 0-3)
743 * has a granularity of .1ns and is added to the value designated
744 * by the higher nibble. In addition, four lines of the lower order
745 * nibble are assigned to support +.25,+.33, +.66 and +.75.
747 /* Convert from hex to decimal */
748 if ((tcyc_reg & 0x0F) == 0x0D)
749 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
750 else if ((tcyc_reg & 0x0F) == 0x0C)
751 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 66;
752 else if ((tcyc_reg & 0x0F) == 0x0B)
753 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 33;
754 else if ((tcyc_reg & 0x0F) == 0x0A)
755 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 25;
757 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) +
758 ((tcyc_reg & 0x0F)*10);
759 debug("cycle_time=%d [10 picoseconds]\n", cycle_time);
761 if (cycle_time > (calc_cycle_time + 10)) {
763 * the provided sdram cycle_time is too small
764 * for the available DIMM cycle_time.
765 * The additionnal 100ps is here to accept a small incertainty.
767 printf("ERROR: DRAM DIMM detected with cycle_time %d ps in "
768 "slot %d \n while calculated cycle time is %d ps.\n",
769 (unsigned int)(cycle_time*10),
770 (unsigned int)dimm_num,
771 (unsigned int)(calc_cycle_time*10));
772 printf("Replace the DIMM, or change DDR frequency via "
773 "strapping bits.\n\n");
780 /*------------------------------------------------------------------
781 * For the memory DIMMs installed, this routine verifies two
782 * ranks/banks maximum are availables.
783 *-----------------------------------------------------------------*/
784 static void check_rank_number(unsigned long *dimm_populated,
785 unsigned char *iic0_dimm_addr,
786 unsigned long num_dimm_banks)
788 unsigned long dimm_num;
789 unsigned long dimm_rank;
790 unsigned long total_rank = 0;
792 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
793 if (dimm_populated[dimm_num] != SDRAM_NONE) {
794 dimm_rank = spd_read(iic0_dimm_addr[dimm_num], 5);
795 if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
796 dimm_rank = (dimm_rank & 0x0F) +1;
798 dimm_rank = dimm_rank & 0x0F;
801 if (dimm_rank > MAXRANKS) {
802 printf("ERROR: DRAM DIMM detected with %d ranks in "
803 "slot %d is not supported.\n", dimm_rank, dimm_num);
804 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
805 printf("Replace the DIMM module with a supported DIMM.\n\n");
808 total_rank += dimm_rank;
810 if (total_rank > MAXRANKS) {
811 printf("ERROR: DRAM DIMM detected with a total of %d ranks "
812 "for all slots.\n", (unsigned int)total_rank);
813 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
814 printf("Remove one of the DIMM modules.\n\n");
820 /*------------------------------------------------------------------
821 * only support 2.5V modules.
822 * This routine verifies this.
823 *-----------------------------------------------------------------*/
824 static void check_voltage_type(unsigned long *dimm_populated,
825 unsigned char *iic0_dimm_addr,
826 unsigned long num_dimm_banks)
828 unsigned long dimm_num;
829 unsigned long voltage_type;
831 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
832 if (dimm_populated[dimm_num] != SDRAM_NONE) {
833 voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
834 switch (voltage_type) {
836 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
837 printf("This DIMM is 5.0 Volt/TTL.\n");
838 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
839 (unsigned int)dimm_num);
843 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
844 printf("This DIMM is LVTTL.\n");
845 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
846 (unsigned int)dimm_num);
850 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
851 printf("This DIMM is 1.5 Volt.\n");
852 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
853 (unsigned int)dimm_num);
857 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
858 printf("This DIMM is 3.3 Volt/TTL.\n");
859 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
860 (unsigned int)dimm_num);
864 /* 2.5 Voltage only for DDR1 */
867 /* 1.8 Voltage only for DDR2 */
870 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
871 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
872 (unsigned int)dimm_num);
880 /*-----------------------------------------------------------------------------+
882 *-----------------------------------------------------------------------------*/
883 static void program_copt1(unsigned long *dimm_populated,
884 unsigned char *iic0_dimm_addr,
885 unsigned long num_dimm_banks)
887 unsigned long dimm_num;
888 unsigned long mcopt1;
889 unsigned long ecc_enabled;
890 unsigned long ecc = 0;
891 unsigned long data_width = 0;
892 unsigned long dimm_32bit;
893 unsigned long dimm_64bit;
894 unsigned long registered = 0;
895 unsigned long attribute = 0;
896 unsigned long buf0, buf1; /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
897 unsigned long bankcount;
898 unsigned long ddrtype;
901 #ifdef CONFIG_DDR_ECC
911 /*------------------------------------------------------------------
912 * Set memory controller options reg 1, SDRAM_MCOPT1.
913 *-----------------------------------------------------------------*/
914 mfsdram(SDRAM_MCOPT1, val);
915 mcopt1 = val & ~(SDRAM_MCOPT1_MCHK_MASK | SDRAM_MCOPT1_RDEN_MASK |
916 SDRAM_MCOPT1_PMU_MASK | SDRAM_MCOPT1_DMWD_MASK |
917 SDRAM_MCOPT1_UIOS_MASK | SDRAM_MCOPT1_BCNT_MASK |
918 SDRAM_MCOPT1_DDR_TYPE_MASK | SDRAM_MCOPT1_RWOO_MASK |
919 SDRAM_MCOPT1_WOOO_MASK | SDRAM_MCOPT1_DCOO_MASK |
920 SDRAM_MCOPT1_DREF_MASK);
922 mcopt1 |= SDRAM_MCOPT1_QDEP;
923 mcopt1 |= SDRAM_MCOPT1_PMU_OPEN;
924 mcopt1 |= SDRAM_MCOPT1_RWOO_DISABLED;
925 mcopt1 |= SDRAM_MCOPT1_WOOO_DISABLED;
926 mcopt1 |= SDRAM_MCOPT1_DCOO_DISABLED;
927 mcopt1 |= SDRAM_MCOPT1_DREF_NORMAL;
929 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
930 if (dimm_populated[dimm_num] != SDRAM_NONE) {
931 /* test ecc support */
932 ecc = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11);
933 if (ecc != 0x02) /* ecc not supported */
936 /* test bank count */
937 bankcount = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 17);
938 if (bankcount == 0x04) /* bank count = 4 */
939 mcopt1 |= SDRAM_MCOPT1_4_BANKS;
940 else /* bank count = 8 */
941 mcopt1 |= SDRAM_MCOPT1_8_BANKS;
944 ddrtype = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2);
945 /* test for buffered/unbuffered, registered, differential clocks */
946 registered = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 20);
947 attribute = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 21);
949 /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
951 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
952 mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
953 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
954 mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
955 if (registered == 1) { /* DDR2 always buffered */
956 /* TODO: what about above comments ? */
957 mcopt1 |= SDRAM_MCOPT1_RDEN;
960 /* TODO: the mask 0x02 doesn't match Samsung def for byte 21. */
961 if ((attribute & 0x02) == 0x00) {
962 /* buffered not supported */
965 mcopt1 |= SDRAM_MCOPT1_RDEN;
970 else if (dimm_num == 1) {
971 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
972 mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
973 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
974 mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
975 if (registered == 1) {
976 /* DDR2 always buffered */
977 mcopt1 |= SDRAM_MCOPT1_RDEN;
980 if ((attribute & 0x02) == 0x00) {
981 /* buffered not supported */
984 mcopt1 |= SDRAM_MCOPT1_RDEN;
990 /* Note that for DDR2 the byte 7 is reserved, but OK to keep code as is. */
991 data_width = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 6) +
992 (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 7)) << 8);
994 switch (data_width) {
1004 printf("WARNING: Detected a DIMM with a data width of %d bits.\n",
1006 printf("Only DIMMs with 32 or 64 bit DDR-SDRAM widths are supported.\n");
1012 /* verify matching properties */
1013 if ((dimm_populated[0] != SDRAM_NONE) && (dimm_populated[1] != SDRAM_NONE)) {
1015 printf("ERROR: DIMM's buffered/unbuffered, registered, clocking don't match.\n");
1020 if ((dimm_64bit == TRUE) && (dimm_32bit == TRUE)) {
1021 printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n");
1024 else if ((dimm_64bit == TRUE) && (dimm_32bit == FALSE)) {
1025 mcopt1 |= SDRAM_MCOPT1_DMWD_64;
1026 } else if ((dimm_64bit == FALSE) && (dimm_32bit == TRUE)) {
1027 mcopt1 |= SDRAM_MCOPT1_DMWD_32;
1029 printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n");
1033 if (ecc_enabled == TRUE)
1034 mcopt1 |= SDRAM_MCOPT1_MCHK_GEN;
1036 mcopt1 |= SDRAM_MCOPT1_MCHK_NON;
1038 mtsdram(SDRAM_MCOPT1, mcopt1);
1041 /*-----------------------------------------------------------------------------+
1043 *-----------------------------------------------------------------------------*/
1044 static void program_codt(unsigned long *dimm_populated,
1045 unsigned char *iic0_dimm_addr,
1046 unsigned long num_dimm_banks)
1049 unsigned long modt0 = 0;
1050 unsigned long modt1 = 0;
1051 unsigned long modt2 = 0;
1052 unsigned long modt3 = 0;
1053 unsigned char dimm_num;
1054 unsigned char dimm_rank;
1055 unsigned char total_rank = 0;
1056 unsigned char total_dimm = 0;
1057 unsigned char dimm_type = 0;
1058 unsigned char firstSlot = 0;
1060 /*------------------------------------------------------------------
1061 * Set the SDRAM Controller On Die Termination Register
1062 *-----------------------------------------------------------------*/
1063 mfsdram(SDRAM_CODT, codt);
1064 codt |= (SDRAM_CODT_IO_NMODE
1065 & (~SDRAM_CODT_DQS_SINGLE_END
1066 & ~SDRAM_CODT_CKSE_SINGLE_END
1067 & ~SDRAM_CODT_FEEBBACK_RCV_SINGLE_END
1068 & ~SDRAM_CODT_FEEBBACK_DRV_SINGLE_END));
1070 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1071 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1072 dimm_rank = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 5);
1073 if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08) {
1074 dimm_rank = (dimm_rank & 0x0F) + 1;
1075 dimm_type = SDRAM_DDR2;
1077 dimm_rank = dimm_rank & 0x0F;
1078 dimm_type = SDRAM_DDR1;
1081 total_rank += dimm_rank;
1083 if ((dimm_num == 0) && (total_dimm == 1))
1089 if (dimm_type == SDRAM_DDR2) {
1090 codt |= SDRAM_CODT_DQS_1_8_V_DDR2;
1091 if ((total_dimm == 1) && (firstSlot == TRUE)) {
1092 if (total_rank == 1) {
1093 codt |= CALC_ODT_R(0);
1094 modt0 = CALC_ODT_W(0);
1099 if (total_rank == 2) {
1100 codt |= CALC_ODT_R(0) | CALC_ODT_R(1);
1101 modt0 = CALC_ODT_W(0);
1102 modt1 = CALC_ODT_W(0);
1106 } else if ((total_dimm == 1) && (firstSlot != TRUE)) {
1107 if (total_rank == 1) {
1108 codt |= CALC_ODT_R(2);
1111 modt2 = CALC_ODT_W(2);
1114 if (total_rank == 2) {
1115 codt |= CALC_ODT_R(2) | CALC_ODT_R(3);
1118 modt2 = CALC_ODT_W(2);
1119 modt3 = CALC_ODT_W(2);
1122 if (total_dimm == 2) {
1123 if (total_rank == 2) {
1124 codt |= CALC_ODT_R(0) | CALC_ODT_R(2);
1125 modt0 = CALC_ODT_RW(2);
1127 modt2 = CALC_ODT_RW(0);
1130 if (total_rank == 4) {
1131 codt |= CALC_ODT_R(0) | CALC_ODT_R(1) |
1132 CALC_ODT_R(2) | CALC_ODT_R(3);
1133 modt0 = CALC_ODT_RW(2);
1135 modt2 = CALC_ODT_RW(0);
1140 codt |= SDRAM_CODT_DQS_2_5_V_DDR1;
1146 if (total_dimm == 1) {
1147 if (total_rank == 1)
1149 if (total_rank == 2)
1152 if (total_dimm == 2) {
1153 if (total_rank == 2)
1155 if (total_rank == 4)
1160 debug("nb of dimm %d\n", total_dimm);
1161 debug("nb of rank %d\n", total_rank);
1162 if (total_dimm == 1)
1163 debug("dimm in slot %d\n", firstSlot);
1165 mtsdram(SDRAM_CODT, codt);
1166 mtsdram(SDRAM_MODT0, modt0);
1167 mtsdram(SDRAM_MODT1, modt1);
1168 mtsdram(SDRAM_MODT2, modt2);
1169 mtsdram(SDRAM_MODT3, modt3);
1172 /*-----------------------------------------------------------------------------+
1174 *-----------------------------------------------------------------------------*/
1175 static void program_initplr(unsigned long *dimm_populated,
1176 unsigned char *iic0_dimm_addr,
1177 unsigned long num_dimm_banks,
1178 ddr_cas_id_t selected_cas,
1192 /******************************************************
1193 ** Assumption: if more than one DIMM, all DIMMs are the same
1194 ** as already checked in check_memory_type
1195 ******************************************************/
1197 if ((dimm_populated[0] == SDRAM_DDR1) || (dimm_populated[1] == SDRAM_DDR1)) {
1198 mtsdram(SDRAM_INITPLR0, 0x81B80000);
1199 mtsdram(SDRAM_INITPLR1, 0x81900400);
1200 mtsdram(SDRAM_INITPLR2, 0x81810000);
1201 mtsdram(SDRAM_INITPLR3, 0xff800162);
1202 mtsdram(SDRAM_INITPLR4, 0x81900400);
1203 mtsdram(SDRAM_INITPLR5, 0x86080000);
1204 mtsdram(SDRAM_INITPLR6, 0x86080000);
1205 mtsdram(SDRAM_INITPLR7, 0x81000062);
1206 } else if ((dimm_populated[0] == SDRAM_DDR2) || (dimm_populated[1] == SDRAM_DDR2)) {
1207 switch (selected_cas) {
1218 printf("ERROR: ucode error on selected_cas value %d", selected_cas);
1225 * ToDo - Still a problem with the write recovery:
1226 * On the Corsair CM2X512-5400C4 module, setting write recovery
1227 * in the INITPLR reg to the value calculated in program_mode()
1228 * results in not correctly working DDR2 memory (crash after
1231 * So for now, set the write recovery to 3. This seems to work
1232 * on the Corair module too.
1236 switch (write_recovery) {
1250 printf("ERROR: write recovery not support (%d)", write_recovery);
1255 wr = WRITE_RECOV_3; /* test-only, see description above */
1258 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++)
1259 if (dimm_populated[dimm_num] != SDRAM_NONE)
1261 if (total_dimm == 1) {
1264 } else if (total_dimm == 2) {
1268 printf("ERROR: Unsupported number of DIMM's (%d)", total_dimm);
1272 mr = CMD_EMR | SELECT_MR | BURST_LEN_4 | wr | cas;
1273 emr = CMD_EMR | SELECT_EMR | odt | ods;
1274 emr2 = CMD_EMR | SELECT_EMR2;
1275 emr3 = CMD_EMR | SELECT_EMR3;
1276 mtsdram(SDRAM_INITPLR0, 0xB5000000 | CMD_NOP); /* NOP */
1278 mtsdram(SDRAM_INITPLR1, 0x82000400 | CMD_PRECHARGE); /* precharge 8 DDR clock cycle */
1279 mtsdram(SDRAM_INITPLR2, 0x80800000 | emr2); /* EMR2 */
1280 mtsdram(SDRAM_INITPLR3, 0x80800000 | emr3); /* EMR3 */
1281 mtsdram(SDRAM_INITPLR4, 0x80800000 | emr); /* EMR DLL ENABLE */
1282 mtsdram(SDRAM_INITPLR5, 0x80800000 | mr | DLL_RESET); /* MR w/ DLL reset */
1284 mtsdram(SDRAM_INITPLR6, 0x82000400 | CMD_PRECHARGE); /* precharge 8 DDR clock cycle */
1285 mtsdram(SDRAM_INITPLR7, 0x8a000000 | CMD_REFRESH); /* Refresh 50 DDR clock cycle */
1286 mtsdram(SDRAM_INITPLR8, 0x8a000000 | CMD_REFRESH); /* Refresh 50 DDR clock cycle */
1287 mtsdram(SDRAM_INITPLR9, 0x8a000000 | CMD_REFRESH); /* Refresh 50 DDR clock cycle */
1288 mtsdram(SDRAM_INITPLR10, 0x8a000000 | CMD_REFRESH); /* Refresh 50 DDR clock cycle */
1289 mtsdram(SDRAM_INITPLR11, 0x80000000 | mr); /* MR w/o DLL reset */
1290 mtsdram(SDRAM_INITPLR12, 0x80800380 | emr); /* EMR OCD Default */
1291 mtsdram(SDRAM_INITPLR13, 0x80800000 | emr); /* EMR OCD Exit */
1293 printf("ERROR: ucode error as unknown DDR type in program_initplr");
1298 /*------------------------------------------------------------------
1299 * This routine programs the SDRAM_MMODE register.
1300 * the selected_cas is an output parameter, that will be passed
1301 * by caller to call the above program_initplr( )
1302 *-----------------------------------------------------------------*/
1303 static void program_mode(unsigned long *dimm_populated,
1304 unsigned char *iic0_dimm_addr,
1305 unsigned long num_dimm_banks,
1306 ddr_cas_id_t *selected_cas,
1307 int *write_recovery)
1309 unsigned long dimm_num;
1310 unsigned long sdram_ddr1;
1311 unsigned long t_wr_ns;
1312 unsigned long t_wr_clk;
1313 unsigned long cas_bit;
1314 unsigned long cas_index;
1315 unsigned long sdram_freq;
1316 unsigned long ddr_check;
1317 unsigned long mmode;
1318 unsigned long tcyc_reg;
1319 unsigned long cycle_2_0_clk;
1320 unsigned long cycle_2_5_clk;
1321 unsigned long cycle_3_0_clk;
1322 unsigned long cycle_4_0_clk;
1323 unsigned long cycle_5_0_clk;
1324 unsigned long max_2_0_tcyc_ns_x_100;
1325 unsigned long max_2_5_tcyc_ns_x_100;
1326 unsigned long max_3_0_tcyc_ns_x_100;
1327 unsigned long max_4_0_tcyc_ns_x_100;
1328 unsigned long max_5_0_tcyc_ns_x_100;
1329 unsigned long cycle_time_ns_x_100[3];
1330 PPC440_SYS_INFO board_cfg;
1331 unsigned char cas_2_0_available;
1332 unsigned char cas_2_5_available;
1333 unsigned char cas_3_0_available;
1334 unsigned char cas_4_0_available;
1335 unsigned char cas_5_0_available;
1336 unsigned long sdr_ddrpll;
1338 /*------------------------------------------------------------------
1339 * Get the board configuration info.
1340 *-----------------------------------------------------------------*/
1341 get_sys_info(&board_cfg);
1343 mfsdr(SDR0_DDR0, sdr_ddrpll);
1344 sdram_freq = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(sdr_ddrpll), 1);
1345 debug("sdram_freq=%d\n", sdram_freq);
1347 /*------------------------------------------------------------------
1348 * Handle the timing. We need to find the worst case timing of all
1349 * the dimm modules installed.
1350 *-----------------------------------------------------------------*/
1352 cas_2_0_available = TRUE;
1353 cas_2_5_available = TRUE;
1354 cas_3_0_available = TRUE;
1355 cas_4_0_available = TRUE;
1356 cas_5_0_available = TRUE;
1357 max_2_0_tcyc_ns_x_100 = 10;
1358 max_2_5_tcyc_ns_x_100 = 10;
1359 max_3_0_tcyc_ns_x_100 = 10;
1360 max_4_0_tcyc_ns_x_100 = 10;
1361 max_5_0_tcyc_ns_x_100 = 10;
1364 /* loop through all the DIMM slots on the board */
1365 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1366 /* If a dimm is installed in a particular slot ... */
1367 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1368 if (dimm_populated[dimm_num] == SDRAM_DDR1)
1373 /* t_wr_ns = max(t_wr_ns, (unsigned long)dimm_spd[dimm_num][36] >> 2); */ /* not used in this loop. */
1374 cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
1375 debug("cas_bit[SPD byte 18]=%02x\n", cas_bit);
1377 /* For a particular DIMM, grab the three CAS values it supports */
1378 for (cas_index = 0; cas_index < 3; cas_index++) {
1379 switch (cas_index) {
1381 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
1384 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
1387 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
1391 if ((tcyc_reg & 0x0F) >= 10) {
1392 if ((tcyc_reg & 0x0F) == 0x0D) {
1393 /* Convert from hex to decimal */
1394 cycle_time_ns_x_100[cas_index] =
1395 (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
1397 printf("ERROR: SPD reported Tcyc is incorrect for DIMM "
1398 "in slot %d\n", (unsigned int)dimm_num);
1402 /* Convert from hex to decimal */
1403 cycle_time_ns_x_100[cas_index] =
1404 (((tcyc_reg & 0xF0) >> 4) * 100) +
1405 ((tcyc_reg & 0x0F)*10);
1407 debug("cas_index=%d: cycle_time_ns_x_100=%d\n", cas_index,
1408 cycle_time_ns_x_100[cas_index]);
1411 /* The rest of this routine determines if CAS 2.0, 2.5, 3.0, 4.0 and 5.0 are */
1412 /* supported for a particular DIMM. */
1417 * DDR devices use the following bitmask for CAS latency:
1418 * Bit 7 6 5 4 3 2 1 0
1419 * TBD 4.0 3.5 3.0 2.5 2.0 1.5 1.0
1421 if (((cas_bit & 0x40) == 0x40) && (cas_index < 3) &&
1422 (cycle_time_ns_x_100[cas_index] != 0)) {
1423 max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1424 cycle_time_ns_x_100[cas_index]);
1429 cas_4_0_available = FALSE;
1432 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1433 (cycle_time_ns_x_100[cas_index] != 0)) {
1434 max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1435 cycle_time_ns_x_100[cas_index]);
1440 cas_3_0_available = FALSE;
1443 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1444 (cycle_time_ns_x_100[cas_index] != 0)) {
1445 max_2_5_tcyc_ns_x_100 = max(max_2_5_tcyc_ns_x_100,
1446 cycle_time_ns_x_100[cas_index]);
1451 cas_2_5_available = FALSE;
1454 if (((cas_bit & 0x04) == 0x04) && (cas_index < 3) &&
1455 (cycle_time_ns_x_100[cas_index] != 0)) {
1456 max_2_0_tcyc_ns_x_100 = max(max_2_0_tcyc_ns_x_100,
1457 cycle_time_ns_x_100[cas_index]);
1462 cas_2_0_available = FALSE;
1466 * DDR2 devices use the following bitmask for CAS latency:
1467 * Bit 7 6 5 4 3 2 1 0
1468 * TBD 6.0 5.0 4.0 3.0 2.0 TBD TBD
1470 if (((cas_bit & 0x20) == 0x20) && (cas_index < 3) &&
1471 (cycle_time_ns_x_100[cas_index] != 0)) {
1472 max_5_0_tcyc_ns_x_100 = max(max_5_0_tcyc_ns_x_100,
1473 cycle_time_ns_x_100[cas_index]);
1478 cas_5_0_available = FALSE;
1481 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1482 (cycle_time_ns_x_100[cas_index] != 0)) {
1483 max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1484 cycle_time_ns_x_100[cas_index]);
1489 cas_4_0_available = FALSE;
1492 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1493 (cycle_time_ns_x_100[cas_index] != 0)) {
1494 max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1495 cycle_time_ns_x_100[cas_index]);
1500 cas_3_0_available = FALSE;
1506 /*------------------------------------------------------------------
1507 * Set the SDRAM mode, SDRAM_MMODE
1508 *-----------------------------------------------------------------*/
1509 mfsdram(SDRAM_MMODE, mmode);
1510 mmode = mmode & ~(SDRAM_MMODE_WR_MASK | SDRAM_MMODE_DCL_MASK);
1512 /* add 10 here because of rounding problems */
1513 cycle_2_0_clk = MULDIV64(ONE_BILLION, 100, max_2_0_tcyc_ns_x_100) + 10;
1514 cycle_2_5_clk = MULDIV64(ONE_BILLION, 100, max_2_5_tcyc_ns_x_100) + 10;
1515 cycle_3_0_clk = MULDIV64(ONE_BILLION, 100, max_3_0_tcyc_ns_x_100) + 10;
1516 cycle_4_0_clk = MULDIV64(ONE_BILLION, 100, max_4_0_tcyc_ns_x_100) + 10;
1517 cycle_5_0_clk = MULDIV64(ONE_BILLION, 100, max_5_0_tcyc_ns_x_100) + 10;
1518 debug("cycle_3_0_clk=%d\n", cycle_3_0_clk);
1519 debug("cycle_4_0_clk=%d\n", cycle_4_0_clk);
1520 debug("cycle_5_0_clk=%d\n", cycle_5_0_clk);
1522 if (sdram_ddr1 == TRUE) { /* DDR1 */
1523 if ((cas_2_0_available == TRUE) && (sdram_freq <= cycle_2_0_clk)) {
1524 mmode |= SDRAM_MMODE_DCL_DDR1_2_0_CLK;
1525 *selected_cas = DDR_CAS_2;
1526 } else if ((cas_2_5_available == TRUE) && (sdram_freq <= cycle_2_5_clk)) {
1527 mmode |= SDRAM_MMODE_DCL_DDR1_2_5_CLK;
1528 *selected_cas = DDR_CAS_2_5;
1529 } else if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1530 mmode |= SDRAM_MMODE_DCL_DDR1_3_0_CLK;
1531 *selected_cas = DDR_CAS_3;
1533 printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1534 printf("Only DIMMs DDR1 with CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
1535 printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n");
1539 debug("cas_3_0_available=%d\n", cas_3_0_available);
1540 debug("cas_4_0_available=%d\n", cas_4_0_available);
1541 debug("cas_5_0_available=%d\n", cas_5_0_available);
1542 if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1543 mmode |= SDRAM_MMODE_DCL_DDR2_3_0_CLK;
1544 *selected_cas = DDR_CAS_3;
1545 } else if ((cas_4_0_available == TRUE) && (sdram_freq <= cycle_4_0_clk)) {
1546 mmode |= SDRAM_MMODE_DCL_DDR2_4_0_CLK;
1547 *selected_cas = DDR_CAS_4;
1548 } else if ((cas_5_0_available == TRUE) && (sdram_freq <= cycle_5_0_clk)) {
1549 mmode |= SDRAM_MMODE_DCL_DDR2_5_0_CLK;
1550 *selected_cas = DDR_CAS_5;
1552 printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1553 printf("Only DIMMs DDR2 with CAS latencies of 3.0, 4.0, and 5.0 are supported.\n");
1554 printf("Make sure the PLB speed is within the supported range of the DIMMs.\n");
1555 printf("cas3=%d cas4=%d cas5=%d\n",
1556 cas_3_0_available, cas_4_0_available, cas_5_0_available);
1557 printf("sdram_freq=%d cycle3=%d cycle4=%d cycle5=%d\n\n",
1558 sdram_freq, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
1563 if (sdram_ddr1 == TRUE)
1564 mmode |= SDRAM_MMODE_WR_DDR1;
1567 /* loop through all the DIMM slots on the board */
1568 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1569 /* If a dimm is installed in a particular slot ... */
1570 if (dimm_populated[dimm_num] != SDRAM_NONE)
1571 t_wr_ns = max(t_wr_ns,
1572 spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1576 * convert from nanoseconds to ddr clocks
1577 * round up if necessary
1579 t_wr_clk = MULDIV64(sdram_freq, t_wr_ns, ONE_BILLION);
1580 ddr_check = MULDIV64(ONE_BILLION, t_wr_clk, t_wr_ns);
1581 if (sdram_freq != ddr_check)
1589 mmode |= SDRAM_MMODE_WR_DDR2_3_CYC;
1592 mmode |= SDRAM_MMODE_WR_DDR2_4_CYC;
1595 mmode |= SDRAM_MMODE_WR_DDR2_5_CYC;
1598 mmode |= SDRAM_MMODE_WR_DDR2_6_CYC;
1601 *write_recovery = t_wr_clk;
1604 debug("CAS latency = %d\n", *selected_cas);
1605 debug("Write recovery = %d\n", *write_recovery);
1607 mtsdram(SDRAM_MMODE, mmode);
1610 /*-----------------------------------------------------------------------------+
1612 *-----------------------------------------------------------------------------*/
1613 static void program_rtr(unsigned long *dimm_populated,
1614 unsigned char *iic0_dimm_addr,
1615 unsigned long num_dimm_banks)
1617 PPC440_SYS_INFO board_cfg;
1618 unsigned long max_refresh_rate;
1619 unsigned long dimm_num;
1620 unsigned long refresh_rate_type;
1621 unsigned long refresh_rate;
1623 unsigned long sdram_freq;
1624 unsigned long sdr_ddrpll;
1627 /*------------------------------------------------------------------
1628 * Get the board configuration info.
1629 *-----------------------------------------------------------------*/
1630 get_sys_info(&board_cfg);
1632 /*------------------------------------------------------------------
1633 * Set the SDRAM Refresh Timing Register, SDRAM_RTR
1634 *-----------------------------------------------------------------*/
1635 mfsdr(SDR0_DDR0, sdr_ddrpll);
1636 sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1638 max_refresh_rate = 0;
1639 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1640 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1642 refresh_rate_type = spd_read(iic0_dimm_addr[dimm_num], 12);
1643 refresh_rate_type &= 0x7F;
1644 switch (refresh_rate_type) {
1646 refresh_rate = 15625;
1649 refresh_rate = 3906;
1652 refresh_rate = 7812;
1655 refresh_rate = 31250;
1658 refresh_rate = 62500;
1661 refresh_rate = 125000;
1665 printf("ERROR: DIMM %d unsupported refresh rate/type.\n",
1666 (unsigned int)dimm_num);
1667 printf("Replace the DIMM module with a supported DIMM.\n\n");
1672 max_refresh_rate = max(max_refresh_rate, refresh_rate);
1676 rint = MULDIV64(sdram_freq, max_refresh_rate, ONE_BILLION);
1677 mfsdram(SDRAM_RTR, val);
1678 mtsdram(SDRAM_RTR, (val & ~SDRAM_RTR_RINT_MASK) |
1679 (SDRAM_RTR_RINT_ENCODE(rint)));
1682 /*------------------------------------------------------------------
1683 * This routine programs the SDRAM_TRx registers.
1684 *-----------------------------------------------------------------*/
1685 static void program_tr(unsigned long *dimm_populated,
1686 unsigned char *iic0_dimm_addr,
1687 unsigned long num_dimm_banks)
1689 unsigned long dimm_num;
1690 unsigned long sdram_ddr1;
1691 unsigned long t_rp_ns;
1692 unsigned long t_rcd_ns;
1693 unsigned long t_rrd_ns;
1694 unsigned long t_ras_ns;
1695 unsigned long t_rc_ns;
1696 unsigned long t_rfc_ns;
1697 unsigned long t_wpc_ns;
1698 unsigned long t_wtr_ns;
1699 unsigned long t_rpc_ns;
1700 unsigned long t_rp_clk;
1701 unsigned long t_rcd_clk;
1702 unsigned long t_rrd_clk;
1703 unsigned long t_ras_clk;
1704 unsigned long t_rc_clk;
1705 unsigned long t_rfc_clk;
1706 unsigned long t_wpc_clk;
1707 unsigned long t_wtr_clk;
1708 unsigned long t_rpc_clk;
1709 unsigned long sdtr1, sdtr2, sdtr3;
1710 unsigned long ddr_check;
1711 unsigned long sdram_freq;
1712 unsigned long sdr_ddrpll;
1714 PPC440_SYS_INFO board_cfg;
1716 /*------------------------------------------------------------------
1717 * Get the board configuration info.
1718 *-----------------------------------------------------------------*/
1719 get_sys_info(&board_cfg);
1721 mfsdr(SDR0_DDR0, sdr_ddrpll);
1722 sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1724 /*------------------------------------------------------------------
1725 * Handle the timing. We need to find the worst case timing of all
1726 * the dimm modules installed.
1727 *-----------------------------------------------------------------*/
1739 /* loop through all the DIMM slots on the board */
1740 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1741 /* If a dimm is installed in a particular slot ... */
1742 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1743 if (dimm_populated[dimm_num] == SDRAM_DDR2)
1748 t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2);
1749 t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2);
1750 t_rp_ns = max(t_rp_ns, spd_read(iic0_dimm_addr[dimm_num], 27) >> 2);
1751 t_ras_ns = max(t_ras_ns, spd_read(iic0_dimm_addr[dimm_num], 30));
1752 t_rc_ns = max(t_rc_ns, spd_read(iic0_dimm_addr[dimm_num], 41));
1753 t_rfc_ns = max(t_rfc_ns, spd_read(iic0_dimm_addr[dimm_num], 42));
1757 /*------------------------------------------------------------------
1758 * Set the SDRAM Timing Reg 1, SDRAM_TR1
1759 *-----------------------------------------------------------------*/
1760 mfsdram(SDRAM_SDTR1, sdtr1);
1761 sdtr1 &= ~(SDRAM_SDTR1_LDOF_MASK | SDRAM_SDTR1_RTW_MASK |
1762 SDRAM_SDTR1_WTWO_MASK | SDRAM_SDTR1_RTRO_MASK);
1764 /* default values */
1765 sdtr1 |= SDRAM_SDTR1_LDOF_2_CLK;
1766 sdtr1 |= SDRAM_SDTR1_RTW_2_CLK;
1768 /* normal operations */
1769 sdtr1 |= SDRAM_SDTR1_WTWO_0_CLK;
1770 sdtr1 |= SDRAM_SDTR1_RTRO_1_CLK;
1772 mtsdram(SDRAM_SDTR1, sdtr1);
1774 /*------------------------------------------------------------------
1775 * Set the SDRAM Timing Reg 2, SDRAM_TR2
1776 *-----------------------------------------------------------------*/
1777 mfsdram(SDRAM_SDTR2, sdtr2);
1778 sdtr2 &= ~(SDRAM_SDTR2_RCD_MASK | SDRAM_SDTR2_WTR_MASK |
1779 SDRAM_SDTR2_XSNR_MASK | SDRAM_SDTR2_WPC_MASK |
1780 SDRAM_SDTR2_RPC_MASK | SDRAM_SDTR2_RP_MASK |
1781 SDRAM_SDTR2_RRD_MASK);
1784 * convert t_rcd from nanoseconds to ddr clocks
1785 * round up if necessary
1787 t_rcd_clk = MULDIV64(sdram_freq, t_rcd_ns, ONE_BILLION);
1788 ddr_check = MULDIV64(ONE_BILLION, t_rcd_clk, t_rcd_ns);
1789 if (sdram_freq != ddr_check)
1792 switch (t_rcd_clk) {
1795 sdtr2 |= SDRAM_SDTR2_RCD_1_CLK;
1798 sdtr2 |= SDRAM_SDTR2_RCD_2_CLK;
1801 sdtr2 |= SDRAM_SDTR2_RCD_3_CLK;
1804 sdtr2 |= SDRAM_SDTR2_RCD_4_CLK;
1807 sdtr2 |= SDRAM_SDTR2_RCD_5_CLK;
1811 if (sdram_ddr1 == TRUE) { /* DDR1 */
1812 if (sdram_freq < 200000000) {
1813 sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1814 sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1815 sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1817 sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1818 sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1819 sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1822 /* loop through all the DIMM slots on the board */
1823 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1824 /* If a dimm is installed in a particular slot ... */
1825 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1826 t_wpc_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1827 t_wtr_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 37) >> 2);
1828 t_rpc_ns = max(t_rpc_ns, spd_read(iic0_dimm_addr[dimm_num], 38) >> 2);
1833 * convert from nanoseconds to ddr clocks
1834 * round up if necessary
1836 t_wpc_clk = MULDIV64(sdram_freq, t_wpc_ns, ONE_BILLION);
1837 ddr_check = MULDIV64(ONE_BILLION, t_wpc_clk, t_wpc_ns);
1838 if (sdram_freq != ddr_check)
1841 switch (t_wpc_clk) {
1845 sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1848 sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1851 sdtr2 |= SDRAM_SDTR2_WPC_4_CLK;
1854 sdtr2 |= SDRAM_SDTR2_WPC_5_CLK;
1857 sdtr2 |= SDRAM_SDTR2_WPC_6_CLK;
1862 * convert from nanoseconds to ddr clocks
1863 * round up if necessary
1865 t_wtr_clk = MULDIV64(sdram_freq, t_wtr_ns, ONE_BILLION);
1866 ddr_check = MULDIV64(ONE_BILLION, t_wtr_clk, t_wtr_ns);
1867 if (sdram_freq != ddr_check)
1870 switch (t_wtr_clk) {
1873 sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1876 sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1879 sdtr2 |= SDRAM_SDTR2_WTR_3_CLK;
1882 sdtr2 |= SDRAM_SDTR2_WTR_4_CLK;
1887 * convert from nanoseconds to ddr clocks
1888 * round up if necessary
1890 t_rpc_clk = MULDIV64(sdram_freq, t_rpc_ns, ONE_BILLION);
1891 ddr_check = MULDIV64(ONE_BILLION, t_rpc_clk, t_rpc_ns);
1892 if (sdram_freq != ddr_check)
1895 switch (t_rpc_clk) {
1899 sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1902 sdtr2 |= SDRAM_SDTR2_RPC_3_CLK;
1905 sdtr2 |= SDRAM_SDTR2_RPC_4_CLK;
1911 sdtr2 |= SDRAM_SDTR2_XSNR_16_CLK;
1914 * convert t_rrd from nanoseconds to ddr clocks
1915 * round up if necessary
1917 t_rrd_clk = MULDIV64(sdram_freq, t_rrd_ns, ONE_BILLION);
1918 ddr_check = MULDIV64(ONE_BILLION, t_rrd_clk, t_rrd_ns);
1919 if (sdram_freq != ddr_check)
1923 sdtr2 |= SDRAM_SDTR2_RRD_3_CLK;
1925 sdtr2 |= SDRAM_SDTR2_RRD_2_CLK;
1928 * convert t_rp from nanoseconds to ddr clocks
1929 * round up if necessary
1931 t_rp_clk = MULDIV64(sdram_freq, t_rp_ns, ONE_BILLION);
1932 ddr_check = MULDIV64(ONE_BILLION, t_rp_clk, t_rp_ns);
1933 if (sdram_freq != ddr_check)
1941 sdtr2 |= SDRAM_SDTR2_RP_3_CLK;
1944 sdtr2 |= SDRAM_SDTR2_RP_4_CLK;
1947 sdtr2 |= SDRAM_SDTR2_RP_5_CLK;
1950 sdtr2 |= SDRAM_SDTR2_RP_6_CLK;
1953 sdtr2 |= SDRAM_SDTR2_RP_7_CLK;
1957 mtsdram(SDRAM_SDTR2, sdtr2);
1959 /*------------------------------------------------------------------
1960 * Set the SDRAM Timing Reg 3, SDRAM_TR3
1961 *-----------------------------------------------------------------*/
1962 mfsdram(SDRAM_SDTR3, sdtr3);
1963 sdtr3 &= ~(SDRAM_SDTR3_RAS_MASK | SDRAM_SDTR3_RC_MASK |
1964 SDRAM_SDTR3_XCS_MASK | SDRAM_SDTR3_RFC_MASK);
1967 * convert t_ras from nanoseconds to ddr clocks
1968 * round up if necessary
1970 t_ras_clk = MULDIV64(sdram_freq, t_ras_ns, ONE_BILLION);
1971 ddr_check = MULDIV64(ONE_BILLION, t_ras_clk, t_ras_ns);
1972 if (sdram_freq != ddr_check)
1975 sdtr3 |= SDRAM_SDTR3_RAS_ENCODE(t_ras_clk);
1978 * convert t_rc from nanoseconds to ddr clocks
1979 * round up if necessary
1981 t_rc_clk = MULDIV64(sdram_freq, t_rc_ns, ONE_BILLION);
1982 ddr_check = MULDIV64(ONE_BILLION, t_rc_clk, t_rc_ns);
1983 if (sdram_freq != ddr_check)
1986 sdtr3 |= SDRAM_SDTR3_RC_ENCODE(t_rc_clk);
1988 /* default xcs value */
1989 sdtr3 |= SDRAM_SDTR3_XCS;
1992 * convert t_rfc from nanoseconds to ddr clocks
1993 * round up if necessary
1995 t_rfc_clk = MULDIV64(sdram_freq, t_rfc_ns, ONE_BILLION);
1996 ddr_check = MULDIV64(ONE_BILLION, t_rfc_clk, t_rfc_ns);
1997 if (sdram_freq != ddr_check)
2000 sdtr3 |= SDRAM_SDTR3_RFC_ENCODE(t_rfc_clk);
2002 mtsdram(SDRAM_SDTR3, sdtr3);
2005 /*-----------------------------------------------------------------------------+
2007 *-----------------------------------------------------------------------------*/
2008 static void program_bxcf(unsigned long *dimm_populated,
2009 unsigned char *iic0_dimm_addr,
2010 unsigned long num_dimm_banks)
2012 unsigned long dimm_num;
2013 unsigned long num_col_addr;
2014 unsigned long num_ranks;
2015 unsigned long num_banks;
2017 unsigned long ind_rank;
2019 unsigned long ind_bank;
2020 unsigned long bank_0_populated;
2022 /*------------------------------------------------------------------
2023 * Set the BxCF regs. First, wipe out the bank config registers.
2024 *-----------------------------------------------------------------*/
2025 mtdcr(SDRAMC_CFGADDR, SDRAM_MB0CF);
2026 mtdcr(SDRAMC_CFGDATA, 0x00000000);
2027 mtdcr(SDRAMC_CFGADDR, SDRAM_MB1CF);
2028 mtdcr(SDRAMC_CFGDATA, 0x00000000);
2029 mtdcr(SDRAMC_CFGADDR, SDRAM_MB2CF);
2030 mtdcr(SDRAMC_CFGDATA, 0x00000000);
2031 mtdcr(SDRAMC_CFGADDR, SDRAM_MB3CF);
2032 mtdcr(SDRAMC_CFGDATA, 0x00000000);
2034 mode = SDRAM_BXCF_M_BE_ENABLE;
2036 bank_0_populated = 0;
2038 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2039 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2040 num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
2041 num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2042 if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2043 num_ranks = (num_ranks & 0x0F) +1;
2045 num_ranks = num_ranks & 0x0F;
2047 num_banks = spd_read(iic0_dimm_addr[dimm_num], 17);
2049 for (ind_bank = 0; ind_bank < 2; ind_bank++) {
2054 switch (num_col_addr) {
2056 mode |= (SDRAM_BXCF_M_AM_0 + ind);
2059 mode |= (SDRAM_BXCF_M_AM_1 + ind);
2062 mode |= (SDRAM_BXCF_M_AM_2 + ind);
2065 mode |= (SDRAM_BXCF_M_AM_3 + ind);
2068 mode |= (SDRAM_BXCF_M_AM_4 + ind);
2071 printf("DDR-SDRAM: DIMM %d BxCF configuration.\n",
2072 (unsigned int)dimm_num);
2073 printf("ERROR: Unsupported value for number of "
2074 "column addresses: %d.\n", (unsigned int)num_col_addr);
2075 printf("Replace the DIMM module with a supported DIMM.\n\n");
2080 if ((dimm_populated[dimm_num] != SDRAM_NONE)&& (dimm_num ==1))
2081 bank_0_populated = 1;
2083 for (ind_rank = 0; ind_rank < num_ranks; ind_rank++) {
2084 mtdcr(SDRAMC_CFGADDR, SDRAM_MB0CF + ((dimm_num + bank_0_populated + ind_rank) << 2));
2085 mtdcr(SDRAMC_CFGDATA, mode);
2091 /*------------------------------------------------------------------
2092 * program memory queue.
2093 *-----------------------------------------------------------------*/
2094 static void program_memory_queue(unsigned long *dimm_populated,
2095 unsigned char *iic0_dimm_addr,
2096 unsigned long num_dimm_banks)
2098 unsigned long dimm_num;
2099 unsigned long rank_base_addr;
2100 unsigned long rank_reg;
2101 unsigned long rank_size_bytes;
2102 unsigned long rank_size_id;
2103 unsigned long num_ranks;
2104 unsigned long baseadd_size;
2106 unsigned long bank_0_populated = 0;
2108 /*------------------------------------------------------------------
2109 * Reset the rank_base_address.
2110 *-----------------------------------------------------------------*/
2111 rank_reg = SDRAM_R0BAS;
2113 rank_base_addr = 0x00000000;
2115 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2116 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2117 num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2118 if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2119 num_ranks = (num_ranks & 0x0F) + 1;
2121 num_ranks = num_ranks & 0x0F;
2123 rank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
2125 /*------------------------------------------------------------------
2127 *-----------------------------------------------------------------*/
2129 rank_size_bytes = 4 * 1024 * 1024 * rank_size_id;
2130 switch (rank_size_id) {
2132 baseadd_size |= SDRAM_RXBAS_SDSZ_8;
2135 baseadd_size |= SDRAM_RXBAS_SDSZ_16;
2138 baseadd_size |= SDRAM_RXBAS_SDSZ_32;
2141 baseadd_size |= SDRAM_RXBAS_SDSZ_64;
2144 baseadd_size |= SDRAM_RXBAS_SDSZ_128;
2147 baseadd_size |= SDRAM_RXBAS_SDSZ_256;
2150 baseadd_size |= SDRAM_RXBAS_SDSZ_512;
2153 printf("DDR-SDRAM: DIMM %d memory queue configuration.\n",
2154 (unsigned int)dimm_num);
2155 printf("ERROR: Unsupported value for the banksize: %d.\n",
2156 (unsigned int)rank_size_id);
2157 printf("Replace the DIMM module with a supported DIMM.\n\n");
2161 if ((dimm_populated[dimm_num] != SDRAM_NONE) && (dimm_num == 1))
2162 bank_0_populated = 1;
2164 for (i = 0; i < num_ranks; i++) {
2165 mtdcr_any(rank_reg+i+dimm_num+bank_0_populated,
2166 (SDRAM_RXBAS_SDBA_ENCODE(rank_base_addr) |
2168 rank_base_addr += rank_size_bytes;
2174 /*-----------------------------------------------------------------------------+
2176 *-----------------------------------------------------------------------------*/
2177 static unsigned long is_ecc_enabled(void)
2179 unsigned long dimm_num;
2184 /* loop through all the DIMM slots on the board */
2185 for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2186 mfsdram(SDRAM_MCOPT1, val);
2187 ecc = max(ecc, SDRAM_MCOPT1_MCHK_CHK_DECODE(val));
2193 static void blank_string(int size)
2197 for (i=0; i<size; i++)
2199 for (i=0; i<size; i++)
2201 for (i=0; i<size; i++)
2205 #ifdef CONFIG_DDR_ECC
2206 /*-----------------------------------------------------------------------------+
2208 *-----------------------------------------------------------------------------*/
2209 static void program_ecc(unsigned long *dimm_populated,
2210 unsigned char *iic0_dimm_addr,
2211 unsigned long num_dimm_banks,
2212 unsigned long tlb_word2_i_value)
2214 unsigned long mcopt1;
2215 unsigned long mcopt2;
2216 unsigned long mcstat;
2217 unsigned long dimm_num;
2221 /* loop through all the DIMM slots on the board */
2222 for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2223 /* If a dimm is installed in a particular slot ... */
2224 if (dimm_populated[dimm_num] != SDRAM_NONE)
2225 ecc = max(ecc, spd_read(iic0_dimm_addr[dimm_num], 11));
2230 mfsdram(SDRAM_MCOPT1, mcopt1);
2231 mfsdram(SDRAM_MCOPT2, mcopt2);
2233 if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
2234 /* DDR controller must be enabled and not in self-refresh. */
2235 mfsdram(SDRAM_MCSTAT, mcstat);
2236 if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
2237 && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
2238 && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
2239 == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
2241 program_ecc_addr(0, sdram_memsize(), tlb_word2_i_value);
2248 #ifdef CONFIG_ECC_ERROR_RESET
2250 * Check for ECC errors and reset board upon any error here
2252 * On the Katmai 440SPe eval board, from time to time, the first
2253 * lword write access after DDR2 initializazion with ECC checking
2254 * enabled, leads to an ECC error. I couldn't find a configuration
2255 * without this happening. On my board with the current setup it
2256 * happens about 1 from 10 times.
2258 * The ECC modules used for testing are:
2259 * - Kingston ValueRAM KVR667D2E5/512 (tested with 1 and 2 DIMM's)
2261 * This has to get fixed for the Katmai and tested for the other
2262 * board (440SP/440SPe) that will eventually use this code in the
2267 static void check_ecc(void)
2271 mfsdram(SDRAM_ECCCR, val);
2273 printf("\nECC error: MCIF0_ECCES=%08lx MQ0_ESL=%08lx address=%08lx\n",
2274 val, mfdcr(0x4c), mfdcr(0x4e));
2275 printf("ECC error occured, resetting board...\n");
2276 do_reset(NULL, 0, 0, NULL);
2281 static void wait_ddr_idle(void)
2286 mfsdram(SDRAM_MCSTAT, val);
2287 } while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT);
2290 /*-----------------------------------------------------------------------------+
2292 *-----------------------------------------------------------------------------*/
2293 static void program_ecc_addr(unsigned long start_address,
2294 unsigned long num_bytes,
2295 unsigned long tlb_word2_i_value)
2297 unsigned long current_address;
2298 unsigned long end_address;
2299 unsigned long address_increment;
2300 unsigned long mcopt1;
2301 char str[] = "ECC generation -";
2302 char slash[] = "\\|/-\\|/-";
2306 current_address = start_address;
2307 mfsdram(SDRAM_MCOPT1, mcopt1);
2308 if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
2309 mtsdram(SDRAM_MCOPT1,
2310 (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_GEN);
2316 if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
2317 /* ECC bit set method for non-cached memory */
2318 if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) == SDRAM_MCOPT1_DMWD_32)
2319 address_increment = 4;
2321 address_increment = 8;
2322 end_address = current_address + num_bytes;
2324 while (current_address < end_address) {
2325 *((unsigned long *)current_address) = 0x00000000;
2326 current_address += address_increment;
2328 if ((loop++ % (2 << 20)) == 0) {
2330 putc(slash[loopi++ % 8]);
2335 /* ECC bit set method for cached memory */
2336 dcbz_area(start_address, num_bytes);
2340 blank_string(strlen(str));
2346 /* clear ECC error repoting registers */
2347 mtsdram(SDRAM_ECCCR, 0xffffffff);
2348 mtdcr(0x4c, 0xffffffff);
2350 mtsdram(SDRAM_MCOPT1,
2351 (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_CHK_REP);
2356 #ifdef CONFIG_ECC_ERROR_RESET
2358 * One write to 0 is enough to trigger this ECC error
2359 * (see description above)
2361 out_be32(0, 0x12345678);
2368 /*-----------------------------------------------------------------------------+
2369 * program_DQS_calibration.
2370 *-----------------------------------------------------------------------------*/
2371 static void program_DQS_calibration(unsigned long *dimm_populated,
2372 unsigned char *iic0_dimm_addr,
2373 unsigned long num_dimm_banks)
2377 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
2378 mtsdram(SDRAM_RQDC, 0x80000037);
2379 mtsdram(SDRAM_RDCC, 0x40000000);
2380 mtsdram(SDRAM_RFDC, 0x000001DF);
2384 /*------------------------------------------------------------------
2385 * Program RDCC register
2386 * Read sample cycle auto-update enable
2387 *-----------------------------------------------------------------*/
2390 * Modified for the Katmai platform: with some DIMMs, the DDR2
2391 * controller automatically selects the T2 read cycle, but this
2392 * proves unreliable. Go ahead and force the DDR2 controller
2393 * to use the T4 sample and disable the automatic update of the
2396 mfsdram(SDRAM_RDCC, val);
2398 (val & ~(SDRAM_RDCC_RDSS_MASK | SDRAM_RDCC_RSAE_MASK))
2399 | (SDRAM_RDCC_RDSS_T4 | SDRAM_RDCC_RSAE_DISABLE));
2401 /*------------------------------------------------------------------
2402 * Program RQDC register
2403 * Internal DQS delay mechanism enable
2404 *-----------------------------------------------------------------*/
2405 mtsdram(SDRAM_RQDC, (SDRAM_RQDC_RQDE_ENABLE|SDRAM_RQDC_RQFD_ENCODE(0x38)));
2407 /*------------------------------------------------------------------
2408 * Program RFDC register
2409 * Set Feedback Fractional Oversample
2410 * Auto-detect read sample cycle enable
2411 *-----------------------------------------------------------------*/
2412 mfsdram(SDRAM_RFDC, val);
2414 (val & ~(SDRAM_RFDC_ARSE_MASK | SDRAM_RFDC_RFOS_MASK |
2415 SDRAM_RFDC_RFFD_MASK))
2416 | (SDRAM_RFDC_ARSE_ENABLE | SDRAM_RFDC_RFOS_ENCODE(0) |
2417 SDRAM_RFDC_RFFD_ENCODE(0)));
2419 DQS_calibration_process();
2423 static int short_mem_test(void)
2430 u32 test[NUMMEMTESTS][NUMMEMWORDS] = {
2431 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2432 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2433 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2434 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2435 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2436 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2437 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2438 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2439 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2440 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2441 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2442 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2443 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2444 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2445 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2446 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2449 for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
2450 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf);
2453 if ((bxcf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2454 /* Bank is enabled */
2456 /*------------------------------------------------------------------
2457 * Run the short memory test.
2458 *-----------------------------------------------------------------*/
2459 membase = (u32 *)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num)));
2461 for (i = 0; i < NUMMEMTESTS; i++) {
2462 for (j = 0; j < NUMMEMWORDS; j++) {
2463 membase[j] = test[i][j];
2464 ppcDcbf((u32)&(membase[j]));
2467 for (l=0; l<NUMLOOPS; l++) {
2468 for (j = 0; j < NUMMEMWORDS; j++) {
2469 if (membase[j] != test[i][j]) {
2470 ppcDcbf((u32)&(membase[j]));
2473 ppcDcbf((u32)&(membase[j]));
2478 } /* if bank enabled */
2479 } /* for bxcf_num */
2484 #ifndef HARD_CODED_DQS
2485 /*-----------------------------------------------------------------------------+
2486 * DQS_calibration_process.
2487 *-----------------------------------------------------------------------------*/
2488 static void DQS_calibration_process(void)
2490 unsigned long rfdc_reg;
2492 unsigned long rqdc_reg;
2499 unsigned long begin_rqfd[MAXRANKS];
2500 unsigned long begin_rffd[MAXRANKS];
2501 unsigned long end_rqfd[MAXRANKS];
2502 unsigned long end_rffd[MAXRANKS];
2504 unsigned long dlycal;
2505 unsigned long dly_val;
2506 unsigned long max_pass_length;
2507 unsigned long current_pass_length;
2508 unsigned long current_fail_length;
2509 unsigned long current_start;
2511 unsigned char fail_found;
2512 unsigned char pass_found;
2514 char str[] = "Auto calibration -";
2515 char slash[] = "\\|/-\\|/-";
2518 /*------------------------------------------------------------------
2519 * Test to determine the best read clock delay tuning bits.
2521 * Before the DDR controller can be used, the read clock delay needs to be
2522 * set. This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2523 * This value cannot be hardcoded into the program because it changes
2524 * depending on the board's setup and environment.
2525 * To do this, all delay values are tested to see if they
2526 * work or not. By doing this, you get groups of fails with groups of
2527 * passing values. The idea is to find the start and end of a passing
2528 * window and take the center of it to use as the read clock delay.
2530 * A failure has to be seen first so that when we hit a pass, we know
2531 * that it is truely the start of the window. If we get passing values
2532 * to start off with, we don't know if we are at the start of the window.
2534 * The code assumes that a failure will always be found.
2535 * If a failure is not found, there is no easy way to get the middle
2536 * of the passing window. I guess we can pretty much pick any value
2537 * but some values will be better than others. Since the lowest speed
2538 * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2539 * from experimentation it is safe to say you will always have a failure.
2540 *-----------------------------------------------------------------*/
2542 /* first fix RQDC[RQFD] to an average of 80 degre phase shift to find RFDC[RFFD] */
2543 rqfd_start = 64; /* test-only: don't know if this is the _best_ start value */
2548 mfsdram(SDRAM_RQDC, rqdc_reg);
2549 mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2550 SDRAM_RQDC_RQFD_ENCODE(rqfd_start));
2562 window_found = FALSE;
2564 max_pass_length = 0;
2567 current_pass_length = 0;
2568 current_fail_length = 0;
2570 window_found = FALSE;
2575 * get the delay line calibration register value
2577 mfsdram(SDRAM_DLCR, dlycal);
2578 dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
2580 for (rffd = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) {
2581 mfsdram(SDRAM_RFDC, rfdc_reg);
2582 rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
2584 /*------------------------------------------------------------------
2585 * Set the timing reg for the test.
2586 *-----------------------------------------------------------------*/
2587 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd));
2589 /*------------------------------------------------------------------
2590 * See if the rffd value passed.
2591 *-----------------------------------------------------------------*/
2592 if (short_mem_test()) {
2593 if (fail_found == TRUE) {
2595 if (current_pass_length == 0)
2596 current_start = rffd;
2598 current_fail_length = 0;
2599 current_pass_length++;
2601 if (current_pass_length > max_pass_length) {
2602 max_pass_length = current_pass_length;
2603 max_start = current_start;
2608 current_pass_length = 0;
2609 current_fail_length++;
2611 if (current_fail_length >= (dly_val >> 2)) {
2612 if (fail_found == FALSE) {
2614 } else if (pass_found == TRUE) {
2615 window_found = TRUE;
2622 /*------------------------------------------------------------------
2623 * Set the average RFFD value
2624 *-----------------------------------------------------------------*/
2625 rffd_average = ((max_start + max_end) >> 1);
2627 if (rffd_average < 0)
2630 if (rffd_average > SDRAM_RFDC_RFFD_MAX)
2631 rffd_average = SDRAM_RFDC_RFFD_MAX;
2632 /* now fix RFDC[RFFD] found and find RQDC[RQFD] */
2633 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
2635 max_pass_length = 0;
2638 current_pass_length = 0;
2639 current_fail_length = 0;
2641 window_found = FALSE;
2645 for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) {
2646 mfsdram(SDRAM_RQDC, rqdc_reg);
2647 rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
2649 /*------------------------------------------------------------------
2650 * Set the timing reg for the test.
2651 *-----------------------------------------------------------------*/
2652 mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd));
2654 /*------------------------------------------------------------------
2655 * See if the rffd value passed.
2656 *-----------------------------------------------------------------*/
2657 if (short_mem_test()) {
2658 if (fail_found == TRUE) {
2660 if (current_pass_length == 0)
2661 current_start = rqfd;
2663 current_fail_length = 0;
2664 current_pass_length++;
2666 if (current_pass_length > max_pass_length) {
2667 max_pass_length = current_pass_length;
2668 max_start = current_start;
2673 current_pass_length = 0;
2674 current_fail_length++;
2676 if (fail_found == FALSE) {
2678 } else if (pass_found == TRUE) {
2679 window_found = TRUE;
2685 rqfd_average = ((max_start + max_end) >> 1);
2687 /*------------------------------------------------------------------
2688 * Make sure we found the valid read passing window. Halt if not
2689 *-----------------------------------------------------------------*/
2690 if (window_found == FALSE) {
2691 if (rqfd_start < SDRAM_RQDC_RQFD_MAX) {
2693 putc(slash[loopi++ % 8]);
2695 /* try again from with a different RQFD start value */
2697 goto calibration_loop;
2700 printf("\nERROR: Cannot determine a common read delay for the "
2701 "DIMM(s) installed.\n");
2702 debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__);
2706 blank_string(strlen(str));
2708 if (rqfd_average < 0)
2711 if (rqfd_average > SDRAM_RQDC_RQFD_MAX)
2712 rqfd_average = SDRAM_RQDC_RQFD_MAX;
2715 (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2716 SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
2718 mfsdram(SDRAM_DLCR, val);
2719 debug("%s[%d] DLCR: 0x%08X\n", __FUNCTION__, __LINE__, val);
2720 mfsdram(SDRAM_RQDC, val);
2721 debug("%s[%d] RQDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2722 mfsdram(SDRAM_RFDC, val);
2723 debug("%s[%d] RFDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2725 #else /* calibration test with hardvalues */
2726 /*-----------------------------------------------------------------------------+
2727 * DQS_calibration_process.
2728 *-----------------------------------------------------------------------------*/
2729 static void test(void)
2731 unsigned long dimm_num;
2732 unsigned long ecc_temp;
2734 unsigned long *membase;
2735 unsigned long bxcf[MAXRANKS];
2738 char begin_found[MAXDIMMS];
2739 char end_found[MAXDIMMS];
2740 char search_end[MAXDIMMS];
2741 unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
2742 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2743 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2744 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2745 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2746 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2747 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2748 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2749 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2750 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2751 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2752 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2753 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2754 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2755 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2756 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2757 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2759 /*------------------------------------------------------------------
2760 * Test to determine the best read clock delay tuning bits.
2762 * Before the DDR controller can be used, the read clock delay needs to be
2763 * set. This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2764 * This value cannot be hardcoded into the program because it changes
2765 * depending on the board's setup and environment.
2766 * To do this, all delay values are tested to see if they
2767 * work or not. By doing this, you get groups of fails with groups of
2768 * passing values. The idea is to find the start and end of a passing
2769 * window and take the center of it to use as the read clock delay.
2771 * A failure has to be seen first so that when we hit a pass, we know
2772 * that it is truely the start of the window. If we get passing values
2773 * to start off with, we don't know if we are at the start of the window.
2775 * The code assumes that a failure will always be found.
2776 * If a failure is not found, there is no easy way to get the middle
2777 * of the passing window. I guess we can pretty much pick any value
2778 * but some values will be better than others. Since the lowest speed
2779 * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2780 * from experimentation it is safe to say you will always have a failure.
2781 *-----------------------------------------------------------------*/
2782 mfsdram(SDRAM_MCOPT1, ecc_temp);
2783 ecc_temp &= SDRAM_MCOPT1_MCHK_MASK;
2784 mfsdram(SDRAM_MCOPT1, val);
2785 mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) |
2786 SDRAM_MCOPT1_MCHK_NON);
2788 window_found = FALSE;
2789 begin_found[0] = FALSE;
2790 end_found[0] = FALSE;
2791 search_end[0] = FALSE;
2792 begin_found[1] = FALSE;
2793 end_found[1] = FALSE;
2794 search_end[1] = FALSE;
2796 for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2797 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf[bxcr_num]);
2800 if ((bxcf[dimm_num] & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2802 /* Bank is enabled */
2804 (unsigned long*)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+dimm_num)));
2806 /*------------------------------------------------------------------
2807 * Run the short memory test.
2808 *-----------------------------------------------------------------*/
2809 for (i = 0; i < NUMMEMTESTS; i++) {
2810 for (j = 0; j < NUMMEMWORDS; j++) {
2811 membase[j] = test[i][j];
2812 ppcDcbf((u32)&(membase[j]));
2815 for (j = 0; j < NUMMEMWORDS; j++) {
2816 if (membase[j] != test[i][j]) {
2817 ppcDcbf((u32)&(membase[j]));
2820 ppcDcbf((u32)&(membase[j]));
2823 if (j < NUMMEMWORDS)
2827 /*------------------------------------------------------------------
2828 * See if the rffd value passed.
2829 *-----------------------------------------------------------------*/
2830 if (i < NUMMEMTESTS) {
2831 if ((end_found[dimm_num] == FALSE) &&
2832 (search_end[dimm_num] == TRUE)) {
2833 end_found[dimm_num] = TRUE;
2835 if ((end_found[0] == TRUE) &&
2836 (end_found[1] == TRUE))
2839 if (begin_found[dimm_num] == FALSE) {
2840 begin_found[dimm_num] = TRUE;
2841 search_end[dimm_num] = TRUE;
2845 begin_found[dimm_num] = TRUE;
2846 end_found[dimm_num] = TRUE;
2850 if ((begin_found[0] == TRUE) && (begin_found[1] == TRUE))
2851 window_found = TRUE;
2853 /*------------------------------------------------------------------
2854 * Make sure we found the valid read passing window. Halt if not
2855 *-----------------------------------------------------------------*/
2856 if (window_found == FALSE) {
2857 printf("ERROR: Cannot determine a common read delay for the "
2858 "DIMM(s) installed.\n");
2862 /*------------------------------------------------------------------
2863 * Restore the ECC variable to what it originally was
2864 *-----------------------------------------------------------------*/
2865 mtsdram(SDRAM_MCOPT1,
2866 (ppcMfdcr_sdram(SDRAM_MCOPT1) & ~SDRAM_MCOPT1_MCHK_MASK)
2872 static void ppc440sp_sdram_register_dump(void)
2874 unsigned int sdram_reg;
2875 unsigned int sdram_data;
2876 unsigned int dcr_data;
2878 printf("\n Register Dump:\n");
2879 sdram_reg = SDRAM_MCSTAT;
2880 mfsdram(sdram_reg, sdram_data);
2881 printf(" SDRAM_MCSTAT = 0x%08X", sdram_data);
2882 sdram_reg = SDRAM_MCOPT1;
2883 mfsdram(sdram_reg, sdram_data);
2884 printf(" SDRAM_MCOPT1 = 0x%08X\n", sdram_data);
2885 sdram_reg = SDRAM_MCOPT2;
2886 mfsdram(sdram_reg, sdram_data);
2887 printf(" SDRAM_MCOPT2 = 0x%08X", sdram_data);
2888 sdram_reg = SDRAM_MODT0;
2889 mfsdram(sdram_reg, sdram_data);
2890 printf(" SDRAM_MODT0 = 0x%08X\n", sdram_data);
2891 sdram_reg = SDRAM_MODT1;
2892 mfsdram(sdram_reg, sdram_data);
2893 printf(" SDRAM_MODT1 = 0x%08X", sdram_data);
2894 sdram_reg = SDRAM_MODT2;
2895 mfsdram(sdram_reg, sdram_data);
2896 printf(" SDRAM_MODT2 = 0x%08X\n", sdram_data);
2897 sdram_reg = SDRAM_MODT3;
2898 mfsdram(sdram_reg, sdram_data);
2899 printf(" SDRAM_MODT3 = 0x%08X", sdram_data);
2900 sdram_reg = SDRAM_CODT;
2901 mfsdram(sdram_reg, sdram_data);
2902 printf(" SDRAM_CODT = 0x%08X\n", sdram_data);
2903 sdram_reg = SDRAM_VVPR;
2904 mfsdram(sdram_reg, sdram_data);
2905 printf(" SDRAM_VVPR = 0x%08X", sdram_data);
2906 sdram_reg = SDRAM_OPARS;
2907 mfsdram(sdram_reg, sdram_data);
2908 printf(" SDRAM_OPARS = 0x%08X\n", sdram_data);
2910 * OPAR2 is only used as a trigger register.
2911 * No data is contained in this register, and reading or writing
2912 * to is can cause bad things to happen (hangs). Just skip it
2914 * sdram_reg = SDRAM_OPAR2;
2915 * mfsdram(sdram_reg, sdram_data);
2916 * printf(" SDRAM_OPAR2 = 0x%08X\n", sdram_data);
2918 printf(" SDRAM_OPART = N/A ");
2919 sdram_reg = SDRAM_RTR;
2920 mfsdram(sdram_reg, sdram_data);
2921 printf(" SDRAM_RTR = 0x%08X\n", sdram_data);
2922 sdram_reg = SDRAM_MB0CF;
2923 mfsdram(sdram_reg, sdram_data);
2924 printf(" SDRAM_MB0CF = 0x%08X", sdram_data);
2925 sdram_reg = SDRAM_MB1CF;
2926 mfsdram(sdram_reg, sdram_data);
2927 printf(" SDRAM_MB1CF = 0x%08X\n", sdram_data);
2928 sdram_reg = SDRAM_MB2CF;
2929 mfsdram(sdram_reg, sdram_data);
2930 printf(" SDRAM_MB2CF = 0x%08X", sdram_data);
2931 sdram_reg = SDRAM_MB3CF;
2932 mfsdram(sdram_reg, sdram_data);
2933 printf(" SDRAM_MB3CF = 0x%08X\n", sdram_data);
2934 sdram_reg = SDRAM_INITPLR0;
2935 mfsdram(sdram_reg, sdram_data);
2936 printf(" SDRAM_INITPLR0 = 0x%08X", sdram_data);
2937 sdram_reg = SDRAM_INITPLR1;
2938 mfsdram(sdram_reg, sdram_data);
2939 printf(" SDRAM_INITPLR1 = 0x%08X\n", sdram_data);
2940 sdram_reg = SDRAM_INITPLR2;
2941 mfsdram(sdram_reg, sdram_data);
2942 printf(" SDRAM_INITPLR2 = 0x%08X", sdram_data);
2943 sdram_reg = SDRAM_INITPLR3;
2944 mfsdram(sdram_reg, sdram_data);
2945 printf(" SDRAM_INITPLR3 = 0x%08X\n", sdram_data);
2946 sdram_reg = SDRAM_INITPLR4;
2947 mfsdram(sdram_reg, sdram_data);
2948 printf(" SDRAM_INITPLR4 = 0x%08X", sdram_data);
2949 sdram_reg = SDRAM_INITPLR5;
2950 mfsdram(sdram_reg, sdram_data);
2951 printf(" SDRAM_INITPLR5 = 0x%08X\n", sdram_data);
2952 sdram_reg = SDRAM_INITPLR6;
2953 mfsdram(sdram_reg, sdram_data);
2954 printf(" SDRAM_INITPLR6 = 0x%08X", sdram_data);
2955 sdram_reg = SDRAM_INITPLR7;
2956 mfsdram(sdram_reg, sdram_data);
2957 printf(" SDRAM_INITPLR7 = 0x%08X\n", sdram_data);
2958 sdram_reg = SDRAM_INITPLR8;
2959 mfsdram(sdram_reg, sdram_data);
2960 printf(" SDRAM_INITPLR8 = 0x%08X", sdram_data);
2961 sdram_reg = SDRAM_INITPLR9;
2962 mfsdram(sdram_reg, sdram_data);
2963 printf(" SDRAM_INITPLR9 = 0x%08X\n", sdram_data);
2964 sdram_reg = SDRAM_INITPLR10;
2965 mfsdram(sdram_reg, sdram_data);
2966 printf(" SDRAM_INITPLR10 = 0x%08X", sdram_data);
2967 sdram_reg = SDRAM_INITPLR11;
2968 mfsdram(sdram_reg, sdram_data);
2969 printf(" SDRAM_INITPLR11 = 0x%08X\n", sdram_data);
2970 sdram_reg = SDRAM_INITPLR12;
2971 mfsdram(sdram_reg, sdram_data);
2972 printf(" SDRAM_INITPLR12 = 0x%08X", sdram_data);
2973 sdram_reg = SDRAM_INITPLR13;
2974 mfsdram(sdram_reg, sdram_data);
2975 printf(" SDRAM_INITPLR13 = 0x%08X\n", sdram_data);
2976 sdram_reg = SDRAM_INITPLR14;
2977 mfsdram(sdram_reg, sdram_data);
2978 printf(" SDRAM_INITPLR14 = 0x%08X", sdram_data);
2979 sdram_reg = SDRAM_INITPLR15;
2980 mfsdram(sdram_reg, sdram_data);
2981 printf(" SDRAM_INITPLR15 = 0x%08X\n", sdram_data);
2982 sdram_reg = SDRAM_RQDC;
2983 mfsdram(sdram_reg, sdram_data);
2984 printf(" SDRAM_RQDC = 0x%08X", sdram_data);
2985 sdram_reg = SDRAM_RFDC;
2986 mfsdram(sdram_reg, sdram_data);
2987 printf(" SDRAM_RFDC = 0x%08X\n", sdram_data);
2988 sdram_reg = SDRAM_RDCC;
2989 mfsdram(sdram_reg, sdram_data);
2990 printf(" SDRAM_RDCC = 0x%08X", sdram_data);
2991 sdram_reg = SDRAM_DLCR;
2992 mfsdram(sdram_reg, sdram_data);
2993 printf(" SDRAM_DLCR = 0x%08X\n", sdram_data);
2994 sdram_reg = SDRAM_CLKTR;
2995 mfsdram(sdram_reg, sdram_data);
2996 printf(" SDRAM_CLKTR = 0x%08X", sdram_data);
2997 sdram_reg = SDRAM_WRDTR;
2998 mfsdram(sdram_reg, sdram_data);
2999 printf(" SDRAM_WRDTR = 0x%08X\n", sdram_data);
3000 sdram_reg = SDRAM_SDTR1;
3001 mfsdram(sdram_reg, sdram_data);
3002 printf(" SDRAM_SDTR1 = 0x%08X", sdram_data);
3003 sdram_reg = SDRAM_SDTR2;
3004 mfsdram(sdram_reg, sdram_data);
3005 printf(" SDRAM_SDTR2 = 0x%08X\n", sdram_data);
3006 sdram_reg = SDRAM_SDTR3;
3007 mfsdram(sdram_reg, sdram_data);
3008 printf(" SDRAM_SDTR3 = 0x%08X", sdram_data);
3009 sdram_reg = SDRAM_MMODE;
3010 mfsdram(sdram_reg, sdram_data);
3011 printf(" SDRAM_MMODE = 0x%08X\n", sdram_data);
3012 sdram_reg = SDRAM_MEMODE;
3013 mfsdram(sdram_reg, sdram_data);
3014 printf(" SDRAM_MEMODE = 0x%08X", sdram_data);
3015 sdram_reg = SDRAM_ECCCR;
3016 mfsdram(sdram_reg, sdram_data);
3017 printf(" SDRAM_ECCCR = 0x%08X\n\n", sdram_data);
3019 dcr_data = mfdcr(SDRAM_R0BAS);
3020 printf(" MQ0_B0BAS = 0x%08X", dcr_data);
3021 dcr_data = mfdcr(SDRAM_R1BAS);
3022 printf(" MQ1_B0BAS = 0x%08X\n", dcr_data);
3023 dcr_data = mfdcr(SDRAM_R2BAS);
3024 printf(" MQ2_B0BAS = 0x%08X", dcr_data);
3025 dcr_data = mfdcr(SDRAM_R3BAS);
3026 printf(" MQ3_B0BAS = 0x%08X\n", dcr_data);
3029 #endif /* CONFIG_SPD_EEPROM */