1 /*-----------------------------------------------------------------------------+
3 * This source code has been made available to you by IBM on an AS-IS
4 * basis. Anyone receiving this source is licensed under IBM
5 * copyrights to use it in any way he or she deems fit, including
6 * copying it, modifying it, compiling it, and redistributing it either
7 * with or without modifications. No license under IBM patents or
8 * patent applications is to be implied by the copyright license.
10 * Any user of this software should understand that IBM cannot provide
11 * technical support for this software and will not be responsible for
12 * any consequences resulting from the use of this software.
14 * Any person who transfers this source code or any derivative work
15 * must include the IBM copyright notice, this paragraph, and the
16 * preceding two paragraphs in the transferred software.
18 * COPYRIGHT I B M CORPORATION 1995
19 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 *-----------------------------------------------------------------------------*/
21 /*-----------------------------------------------------------------------------+
23 * File Name: enetemac.c
25 * Function: Device driver for the ethernet EMAC3 macro on the 405GP.
31 * Date Description of Change BY
32 * --------- --------------------- ---
33 * 05-May-99 Created MKW
34 * 27-Jun-99 Clean up JWB
35 * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW
36 * 29-Jul-99 Added Full duplex support MKW
37 * 06-Aug-99 Changed names for Mal CR reg MKW
38 * 23-Aug-99 Turned off SYE when running at 10Mbs MKW
39 * 24-Aug-99 Marked descriptor empty after call_xlc MKW
40 * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG
41 * to avoid chaining maximum sized packets. Push starting
42 * RX descriptor address up to the next cache line boundary.
43 * 16-Jan-00 Added support for booting with IP of 0x0 MKW
44 * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the
45 * EMAC_RXM register. JWB
46 * 12-Mar-01 anne-sophie.harnois@nextream.fr
47 * - Variables are compatible with those already defined in
49 * - Receive buffer descriptor ring is used to send buffers
51 * - Info print about send/received/handled packet number if
52 * INFO_405_ENET is set
53 * 17-Apr-01 stefan.roese@esd-electronics.com
54 * - MAL reset in "eth_halt" included
55 * - Enet speed and duplex output now in one line
56 * 08-May-01 stefan.roese@esd-electronics.com
57 * - MAL error handling added (eth_init called again)
58 * 13-Nov-01 stefan.roese@esd-electronics.com
59 * - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex
60 * 04-Jan-02 stefan.roese@esd-electronics.com
61 * - Wait for PHY auto negotiation to complete added
62 * 06-Feb-02 stefan.roese@esd-electronics.com
63 * - Bug fixed in waiting for auto negotiation to complete
64 * 26-Feb-02 stefan.roese@esd-electronics.com
65 * - rx and tx buffer descriptors now allocated (no fixed address
67 * 17-Jun-02 stefan.roese@esd-electronics.com
68 * - MAL error debug printf 'M' removed (rx de interrupt may
69 * occur upon many incoming packets with only 4 rx buffers).
70 *-----------------------------------------------------------------------------*
71 * 17-Nov-03 travis.sawyer@sandburst.com
72 * - ported from 405gp_enet.c to utilized upto 4 EMAC ports
73 * in the 440GX. This port should work with the 440GP
75 * 15-Aug-05 sr@denx.de
76 * - merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c
77 now handling all 4xx cpu's.
78 *-----------------------------------------------------------------------------*/
83 #include <asm/processor.h>
86 #include <ppc4xx_enet.h>
93 * Only compile for platform with AMCC EMAC ethernet controller and
94 * network support enabled.
95 * Remark: CONFIG_405 describes Xilinx PPC405 FPGA without EMAC controller!
97 #if (CONFIG_COMMANDS & CFG_CMD_NET) && !defined(CONFIG_405) && !defined(CONFIG_IOP480)
99 #if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII))
100 #error "CONFIG_MII has to be defined!"
103 #define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
104 #define PHY_AUTONEGOTIATE_TIMEOUT 4000 /* 4000 ms autonegotiate timeout */
106 /* Ethernet Transmit and Receive Buffers */
108 * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
109 * PKTSIZE and PKTSIZE_ALIGN (include/net.h)
111 #define ENET_MAX_MTU PKTSIZE
112 #define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
114 /* define the number of channels implemented */
115 #define EMAC_RXCHL EMAC_NUM_DEV
116 #define EMAC_TXCHL EMAC_NUM_DEV
118 /*-----------------------------------------------------------------------------+
119 * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
120 * Interrupt Controller).
121 *-----------------------------------------------------------------------------*/
122 #define MAL_UIC_ERR ( UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)
123 #define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR)
124 #define EMAC_UIC_DEF UIC_ENET
125 #define EMAC_UIC_DEF1 UIC_ENET1
126 #define SEL_UIC_DEF(p) (p ? UIC_ENET1 : UIC_ENET )
130 #define BI_PHYMODE_NONE 0
131 #define BI_PHYMODE_ZMII 1
132 #define BI_PHYMODE_RGMII 2
135 /*-----------------------------------------------------------------------------+
136 * Global variables. TX and RX descriptors and buffers.
137 *-----------------------------------------------------------------------------*/
139 static uint32_t mal_ier;
141 #if !defined(CONFIG_NET_MULTI)
142 struct eth_device *emac0_dev = NULL;
146 /*-----------------------------------------------------------------------------+
147 * Prototypes and externals.
148 *-----------------------------------------------------------------------------*/
149 static void enet_rcv (struct eth_device *dev, unsigned long malisr);
151 int enetInt (struct eth_device *dev);
152 static void mal_err (struct eth_device *dev, unsigned long isr,
153 unsigned long uic, unsigned long maldef,
154 unsigned long mal_errr);
155 static void emac_err (struct eth_device *dev, unsigned long isr);
158 /*-----------------------------------------------------------------------------+
160 | Disable MAL channel, and EMACn
161 +-----------------------------------------------------------------------------*/
162 static void ppc_4xx_eth_halt (struct eth_device *dev)
164 EMAC_4XX_HW_PST hw_p = dev->priv;
165 uint32_t failsafe = 10000;
167 out32 (EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */
169 /* 1st reset MAL channel */
170 /* Note: writing a 0 to a channel has no effect */
171 #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
172 mtdcr (maltxcarr, (MAL_CR_MMSR >> (hw_p->devnum * 2)));
174 mtdcr (maltxcarr, (MAL_CR_MMSR >> hw_p->devnum));
176 mtdcr (malrxcarr, (MAL_CR_MMSR >> hw_p->devnum));
179 while (mfdcr (malrxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
180 udelay (1000); /* Delay 1 MS so as not to hammer the register */
187 out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
189 hw_p->print_speed = 1; /* print speed message again next time */
194 extern int phy_setup_aneg (unsigned char addr);
195 extern int miiphy_reset (unsigned char addr);
197 #if defined (CONFIG_440GX)
198 int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
201 unsigned long zmiifer;
202 unsigned long rmiifer;
204 mfsdr(sdr_pfc1, pfc1);
205 pfc1 = SDR0_PFC1_EPS_DECODE(pfc1);
212 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
213 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
214 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2);
215 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3);
216 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
217 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
218 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
219 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
222 zmiifer = ZMII_FER_SMII << ZMII_FER_V(0);
223 zmiifer = ZMII_FER_SMII << ZMII_FER_V(1);
224 zmiifer = ZMII_FER_SMII << ZMII_FER_V(2);
225 zmiifer = ZMII_FER_SMII << ZMII_FER_V(3);
226 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
227 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
228 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
229 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
232 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
233 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
234 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
235 bis->bi_phymode[1] = BI_PHYMODE_NONE;
236 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
237 bis->bi_phymode[3] = BI_PHYMODE_NONE;
240 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
241 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
242 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (2);
243 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (3);
244 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
245 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
246 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
247 bis->bi_phymode[3] = BI_PHYMODE_RGMII;
250 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
251 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
252 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (2);
253 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
254 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
255 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
256 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
257 bis->bi_phymode[3] = BI_PHYMODE_RGMII;
260 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
261 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
262 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
263 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
264 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
265 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
269 zmiifer = ZMII_FER_MII << ZMII_FER_V(devnum);
271 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
272 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
273 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
274 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
278 /* Ensure we setup mdio for this devnum and ONLY this devnum */
279 zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
281 out32 (ZMII_FER, zmiifer);
282 out32 (RGMII_FER, rmiifer);
289 static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
292 unsigned long reg = 0;
295 unsigned long duplex;
296 unsigned long failsafe;
298 unsigned short devnum;
299 unsigned short reg_short;
300 #if defined(CONFIG_440GX)
305 EMAC_4XX_HW_PST hw_p = dev->priv;
307 /* before doing anything, figure out if we have a MAC address */
309 if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0) {
310 printf("ERROR: ethaddr not set!\n");
314 #if defined(CONFIG_440GX)
315 /* Need to get the OPB frequency so we can access the PHY */
316 get_sys_info (&sysinfo);
320 mtmsr (msr & ~(MSR_EE)); /* disable interrupts */
322 devnum = hw_p->devnum;
327 * hw_p->stats.pkts_handled <= hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX
328 * In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it
329 * is possible that new packets (without relationship with
330 * current transfer) have got the time to arrived before
331 * netloop calls eth_halt
333 printf ("About preceeding transfer (eth%d):\n"
334 "- Sent packet number %d\n"
335 "- Received packet number %d\n"
336 "- Handled packet number %d\n",
339 hw_p->stats.pkts_rx, hw_p->stats.pkts_handled);
341 hw_p->stats.pkts_tx = 0;
342 hw_p->stats.pkts_rx = 0;
343 hw_p->stats.pkts_handled = 0;
346 hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */
347 hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */
349 hw_p->rx_slot = 0; /* MAL Receive Slot */
350 hw_p->rx_i_index = 0; /* Receive Interrupt Queue Index */
351 hw_p->rx_u_index = 0; /* Receive User Queue Index */
353 hw_p->tx_slot = 0; /* MAL Transmit Slot */
354 hw_p->tx_i_index = 0; /* Transmit Interrupt Queue Index */
355 hw_p->tx_u_index = 0; /* Transmit User Queue Index */
357 #if defined(CONFIG_440)
359 /* NOTE: 440GX spec states that mode is mutually exclusive */
360 /* NOTE: Therefore, disable all other EMACS, since we handle */
361 /* NOTE: only one emac at a time */
366 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
367 out32 (ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
368 #elif defined(CONFIG_440GX)
369 ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
370 #elif defined(CONFIG_440GP)
372 out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0);
374 if ((devnum == 0) || (devnum == 1)) {
375 out32 (ZMII_FER, (ZMII_FER_SMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
377 else { /* ((devnum == 2) || (devnum == 3)) */
378 out32 (ZMII_FER, ZMII_FER_MDI << ZMII_FER_V (devnum));
379 out32 (RGMII_FER, ((RGMII_FER_RGMII << RGMII_FER_V (2)) |
380 (RGMII_FER_RGMII << RGMII_FER_V (3))));
384 out32 (ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum));
385 #endif /* defined(CONFIG_440) */
387 __asm__ volatile ("eieio");
389 /* reset emac so we have access to the phy */
391 out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
392 __asm__ volatile ("eieio");
395 while ((in32 (EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) {
400 #if defined(CONFIG_440GX)
401 /* Whack the M1 register */
403 mode_reg &= ~0x00000038;
404 if (sysinfo.freqOPB <= 50000000);
405 else if (sysinfo.freqOPB <= 66666667)
406 mode_reg |= EMAC_M1_OBCI_66;
407 else if (sysinfo.freqOPB <= 83333333)
408 mode_reg |= EMAC_M1_OBCI_83;
409 else if (sysinfo.freqOPB <= 100000000)
410 mode_reg |= EMAC_M1_OBCI_100;
412 mode_reg |= EMAC_M1_OBCI_GT100;
414 out32 (EMAC_M1 + hw_p->hw_addr, mode_reg);
415 #endif /* defined(CONFIG_440GX) */
417 /* wait for PHY to complete auto negotiation */
419 #ifndef CONFIG_CS8952_PHY
422 reg = CONFIG_PHY_ADDR;
424 #if defined (CONFIG_PHY1_ADDR)
426 reg = CONFIG_PHY1_ADDR;
429 #if defined (CONFIG_440GX)
431 reg = CONFIG_PHY2_ADDR;
434 reg = CONFIG_PHY3_ADDR;
438 reg = CONFIG_PHY_ADDR;
442 bis->bi_phynum[devnum] = reg;
444 #if defined(CONFIG_PHY_RESET)
446 * Reset the phy, only if its the first time through
447 * otherwise, just check the speeds & feeds
449 if (hw_p->first_init == 0) {
452 #if defined(CONFIG_440GX)
453 #if defined(CONFIG_CIS8201_PHY)
455 * Cicada 8201 PHY needs to have an extended register whacked
458 if ( ((devnum == 2) || (devnum ==3)) && (4 == ethgroup) ) {
459 #if defined(CONFIG_CIS8201_SHORT_ETCH)
460 miiphy_write (reg, 23, 0x1300);
462 miiphy_write (reg, 23, 0x1000);
465 * Vitesse VSC8201/Cicada CIS8201 errata:
466 * Interoperability problem with Intel 82547EI phys
467 * This work around (provided by Vitesse) changes
468 * the default timer convergence from 8ms to 12ms
470 miiphy_write (reg, 0x1f, 0x2a30);
471 miiphy_write (reg, 0x08, 0x0200);
472 miiphy_write (reg, 0x1f, 0x52b5);
473 miiphy_write (reg, 0x02, 0x0004);
474 miiphy_write (reg, 0x01, 0x0671);
475 miiphy_write (reg, 0x00, 0x8fae);
476 miiphy_write (reg, 0x1f, 0x2a30);
477 miiphy_write (reg, 0x08, 0x0000);
478 miiphy_write (reg, 0x1f, 0x0000);
479 /* end Vitesse/Cicada errata */
483 /* Start/Restart autonegotiation */
484 phy_setup_aneg (reg);
487 #endif /* defined(CONFIG_PHY_RESET) */
489 miiphy_read (reg, PHY_BMSR, ®_short);
492 * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
494 if ((reg_short & PHY_BMSR_AUTN_ABLE)
495 && !(reg_short & PHY_BMSR_AUTN_COMP)) {
496 puts ("Waiting for PHY auto negotiation to complete");
498 while (!(reg_short & PHY_BMSR_AUTN_COMP)) {
502 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
503 puts (" TIMEOUT !\n");
507 if ((i++ % 1000) == 0) {
510 udelay (1000); /* 1 ms */
511 miiphy_read (reg, PHY_BMSR, ®_short);
515 udelay (500000); /* another 500 ms (results in faster booting) */
517 #endif /* #ifndef CONFIG_CS8952_PHY */
519 speed = miiphy_speed (reg);
520 duplex = miiphy_duplex (reg);
522 if (hw_p->print_speed) {
523 hw_p->print_speed = 0;
524 printf ("ENET Speed is %d Mbps - %s duplex connection\n",
525 (int) speed, (duplex == HALF) ? "HALF" : "FULL");
528 #if defined(CONFIG_440)
529 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
532 reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M;
534 reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
539 /* Set ZMII/RGMII speed according to the phy link speed */
540 reg = in32 (ZMII_SSR);
541 if ( (speed == 100) || (speed == 1000) )
542 out32 (ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum)));
544 out32 (ZMII_SSR, reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum))));
546 if ((devnum == 2) || (devnum == 3)) {
548 reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
549 else if (speed == 100)
550 reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
552 reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
554 out32 (RGMII_SSR, reg);
556 #endif /* defined(CONFIG_440) */
558 /* set the Mal configuration reg */
559 #if defined(CONFIG_440GX)
560 mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
561 MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
563 mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
564 /* Errata 1.12: MAL_1 -- Disable MAL bursting */
565 if (get_pvr() == PVR_440GP_RB) {
566 mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB);
570 /* Free "old" buffers */
571 if (hw_p->alloc_tx_buf)
572 free (hw_p->alloc_tx_buf);
573 if (hw_p->alloc_rx_buf)
574 free (hw_p->alloc_rx_buf);
577 * Malloc MAL buffer desciptors, make sure they are
578 * aligned on cache line boundary size
579 * (401/403/IOP480 = 16, 405 = 32)
580 * and doesn't cross cache block boundaries.
583 (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_TX_BUFF) +
584 ((2 * CFG_CACHELINE_SIZE) - 2));
585 if (NULL == hw_p->alloc_tx_buf)
587 if (((int) hw_p->alloc_tx_buf & CACHELINE_MASK) != 0) {
589 (mal_desc_t *) ((int) hw_p->alloc_tx_buf +
592 alloc_tx_buf & CACHELINE_MASK));
594 hw_p->tx = hw_p->alloc_tx_buf;
598 (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_RX_BUFF) +
599 ((2 * CFG_CACHELINE_SIZE) - 2));
600 if (NULL == hw_p->alloc_rx_buf) {
601 free(hw_p->alloc_tx_buf);
602 hw_p->alloc_tx_buf = NULL;
606 if (((int) hw_p->alloc_rx_buf & CACHELINE_MASK) != 0) {
608 (mal_desc_t *) ((int) hw_p->alloc_rx_buf +
611 alloc_rx_buf & CACHELINE_MASK));
613 hw_p->rx = hw_p->alloc_rx_buf;
616 for (i = 0; i < NUM_TX_BUFF; i++) {
617 hw_p->tx[i].ctrl = 0;
618 hw_p->tx[i].data_len = 0;
619 if (hw_p->first_init == 0) {
621 (char *) malloc (ENET_MAX_MTU_ALIGNED);
622 if (NULL == hw_p->txbuf_ptr) {
623 free(hw_p->alloc_rx_buf);
624 free(hw_p->alloc_tx_buf);
625 hw_p->alloc_rx_buf = NULL;
626 hw_p->alloc_tx_buf = NULL;
627 for(j = 0; j < i; j++) {
628 free(hw_p->tx[i].data_ptr);
629 hw_p->tx[i].data_ptr = NULL;
633 hw_p->tx[i].data_ptr = hw_p->txbuf_ptr;
634 if ((NUM_TX_BUFF - 1) == i)
635 hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP;
636 hw_p->tx_run[i] = -1;
638 printf ("TX_BUFF %d @ 0x%08lx\n", i,
639 (ulong) hw_p->tx[i].data_ptr);
643 for (i = 0; i < NUM_RX_BUFF; i++) {
644 hw_p->rx[i].ctrl = 0;
645 hw_p->rx[i].data_len = 0;
646 /* rx[i].data_ptr = (char *) &rx_buff[i]; */
647 hw_p->rx[i].data_ptr = (char *) NetRxPackets[i];
648 if ((NUM_RX_BUFF - 1) == i)
649 hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP;
650 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR;
651 hw_p->rx_ready[i] = -1;
653 printf ("RX_BUFF %d @ 0x%08lx\n", i, (ulong) rx[i].data_ptr);
659 reg |= dev->enetaddr[0]; /* set high address */
661 reg |= dev->enetaddr[1];
663 out32 (EMAC_IAH + hw_p->hw_addr, reg);
666 reg |= dev->enetaddr[2]; /* set low address */
668 reg |= dev->enetaddr[3];
670 reg |= dev->enetaddr[4];
672 reg |= dev->enetaddr[5];
674 out32 (EMAC_IAL + hw_p->hw_addr, reg);
678 /* setup MAL tx & rx channel pointers */
679 #if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR)
680 mtdcr (maltxctp2r, hw_p->tx);
682 mtdcr (maltxctp1r, hw_p->tx);
684 #if defined(CONFIG_440)
685 mtdcr (maltxbattr, 0x0);
686 mtdcr (malrxbattr, 0x0);
688 mtdcr (malrxctp1r, hw_p->rx);
689 /* set RX buffer size */
690 mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16);
692 #if defined (CONFIG_440GX)
694 /* setup MAL tx & rx channel pointers */
695 mtdcr (maltxbattr, 0x0);
696 mtdcr (malrxbattr, 0x0);
697 mtdcr (maltxctp2r, hw_p->tx);
698 mtdcr (malrxctp2r, hw_p->rx);
699 /* set RX buffer size */
700 mtdcr (malrcbs2, ENET_MAX_MTU_ALIGNED / 16);
703 /* setup MAL tx & rx channel pointers */
704 mtdcr (maltxbattr, 0x0);
705 mtdcr (maltxctp3r, hw_p->tx);
706 mtdcr (malrxbattr, 0x0);
707 mtdcr (malrxctp3r, hw_p->rx);
708 /* set RX buffer size */
709 mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16);
711 #endif /* CONFIG_440GX */
714 /* setup MAL tx & rx channel pointers */
715 #if defined(CONFIG_440)
716 mtdcr (maltxbattr, 0x0);
717 mtdcr (malrxbattr, 0x0);
719 mtdcr (maltxctp0r, hw_p->tx);
720 mtdcr (malrxctp0r, hw_p->rx);
721 /* set RX buffer size */
722 mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16);
726 /* Enable MAL transmit and receive channels */
727 #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
728 mtdcr (maltxcasr, (MAL_TXRX_CASR >> (hw_p->devnum*2)));
730 mtdcr (maltxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
732 mtdcr (malrxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
734 /* set transmit enable & receive enable */
735 out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);
737 /* set receive fifo to 4k and tx fifo to 2k */
738 mode_reg = in32 (EMAC_M1 + hw_p->hw_addr);
739 mode_reg |= EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K;
742 if (speed == _1000BASET)
743 mode_reg = mode_reg | EMAC_M1_MF_1000MBPS | EMAC_M1_IST;
744 else if (speed == _100BASET)
745 mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST;
747 mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */
749 mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST;
751 out32 (EMAC_M1 + hw_p->hw_addr, mode_reg);
753 /* Enable broadcast and indvidual address */
754 /* TBS: enabling runts as some misbehaved nics will send runts */
755 out32 (EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE);
757 /* we probably need to set the tx mode1 reg? maybe at tx time */
759 /* set transmit request threshold register */
760 out32 (EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */
762 /* set receive low/high water mark register */
763 #if defined(CONFIG_440)
764 /* 440GP has a 64 byte burst length */
765 out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000);
767 /* 405s have a 16 byte burst length */
768 out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000);
769 #endif /* defined(CONFIG_440) */
770 out32 (EMAC_TXM1 + hw_p->hw_addr, 0xf8640000);
772 /* Set fifo limit entry in tx mode 0 */
773 out32 (EMAC_TXM0 + hw_p->hw_addr, 0x00000003);
775 out32 (EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008);
778 hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE;
779 if (speed == _100BASET)
780 hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE;
782 out32 (EMAC_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */
783 out32 (EMAC_IER + hw_p->hw_addr, hw_p->emac_ier);
785 if (hw_p->first_init == 0) {
787 * Connect interrupt service routines
789 irq_install_handler (VECNUM_ETH0 + (hw_p->devnum * 2),
790 (interrupt_handler_t *) enetInt, dev);
793 mtmsr (msr); /* enable interrupts again */
796 hw_p->first_init = 1;
802 static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr,
805 struct enet_frame *ef_ptr;
806 ulong time_start, time_now;
807 unsigned long temp_txm0;
808 EMAC_4XX_HW_PST hw_p = dev->priv;
810 ef_ptr = (struct enet_frame *) ptr;
812 /*-----------------------------------------------------------------------+
813 * Copy in our address into the frame.
814 *-----------------------------------------------------------------------*/
815 (void) memcpy (ef_ptr->source_addr, dev->enetaddr, ENET_ADDR_LENGTH);
817 /*-----------------------------------------------------------------------+
818 * If frame is too long or too short, modify length.
819 *-----------------------------------------------------------------------*/
820 /* TBS: where does the fragment go???? */
821 if (len > ENET_MAX_MTU)
824 /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */
825 memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len);
827 /*-----------------------------------------------------------------------+
828 * set TX Buffer busy, and send it
829 *-----------------------------------------------------------------------*/
830 hw_p->tx[hw_p->tx_slot].ctrl = (MAL_TX_CTRL_LAST |
831 EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) &
832 ~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA);
833 if ((NUM_TX_BUFF - 1) == hw_p->tx_slot)
834 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_WRAP;
836 hw_p->tx[hw_p->tx_slot].data_len = (short) len;
837 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY;
839 __asm__ volatile ("eieio");
841 out32 (EMAC_TXM0 + hw_p->hw_addr,
842 in32 (EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0);
844 hw_p->stats.pkts_tx++;
847 /*-----------------------------------------------------------------------+
848 * poll unitl the packet is sent and then make sure it is OK
849 *-----------------------------------------------------------------------*/
850 time_start = get_timer (0);
852 temp_txm0 = in32 (EMAC_TXM0 + hw_p->hw_addr);
853 /* loop until either TINT turns on or 3 seconds elapse */
854 if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) {
855 /* transmit is done, so now check for errors
856 * If there is an error, an interrupt should
857 * happen when we return
859 time_now = get_timer (0);
860 if ((time_now - time_start) > 3000) {
869 #if defined (CONFIG_440)
871 int enetInt (struct eth_device *dev)
874 int rc = -1; /* default to not us */
875 unsigned long mal_isr;
876 unsigned long emac_isr = 0;
877 unsigned long mal_rx_eob;
878 unsigned long my_uic0msr, my_uic1msr;
880 #if defined(CONFIG_440GX)
881 unsigned long my_uic2msr;
883 EMAC_4XX_HW_PST hw_p;
886 * Because the mal is generic, we need to get the current
889 #if defined(CONFIG_NET_MULTI)
898 /* enter loop that stays in interrupt code until nothing to service */
902 my_uic0msr = mfdcr (uic0msr);
903 my_uic1msr = mfdcr (uic1msr);
904 #if defined(CONFIG_440GX)
905 my_uic2msr = mfdcr (uic2msr);
907 if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
909 (UIC_ETH0 | UIC_ETH1 | UIC_MS | UIC_MTDE |
914 #if defined (CONFIG_440GX)
915 if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
916 && !(my_uic2msr & (UIC_ETH2 | UIC_ETH3))) {
921 /* get and clear controller status interrupts */
922 /* look at Mal and EMAC interrupts */
923 if ((my_uic0msr & (UIC_MRE | UIC_MTE))
924 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
925 /* we have a MAL interrupt */
926 mal_isr = mfdcr (malesr);
927 /* look for mal error */
928 if (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) {
929 mal_err (dev, mal_isr, my_uic0msr,
930 MAL_UIC_DEF, MAL_UIC_ERR);
936 /* port by port dispatch of emac interrupts */
937 if (hw_p->devnum == 0) {
938 if (UIC_ETH0 & my_uic1msr) { /* look for EMAC errors */
939 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
940 if ((hw_p->emac_ier & emac_isr) != 0) {
941 emac_err (dev, emac_isr);
946 if ((hw_p->emac_ier & emac_isr)
947 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
948 mtdcr (uic0sr, UIC_MRE | UIC_MTE); /* Clear */
949 mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
950 return (rc); /* we had errors so get out */
954 if (hw_p->devnum == 1) {
955 if (UIC_ETH1 & my_uic1msr) { /* look for EMAC errors */
956 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
957 if ((hw_p->emac_ier & emac_isr) != 0) {
958 emac_err (dev, emac_isr);
963 if ((hw_p->emac_ier & emac_isr)
964 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
965 mtdcr (uic0sr, UIC_MRE | UIC_MTE); /* Clear */
966 mtdcr (uic1sr, UIC_ETH1 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
967 return (rc); /* we had errors so get out */
970 #if defined (CONFIG_440GX)
971 if (hw_p->devnum == 2) {
972 if (UIC_ETH2 & my_uic2msr) { /* look for EMAC errors */
973 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
974 if ((hw_p->emac_ier & emac_isr) != 0) {
975 emac_err (dev, emac_isr);
980 if ((hw_p->emac_ier & emac_isr)
981 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
982 mtdcr (uic0sr, UIC_MRE | UIC_MTE); /* Clear */
983 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
984 mtdcr (uic2sr, UIC_ETH2);
985 return (rc); /* we had errors so get out */
989 if (hw_p->devnum == 3) {
990 if (UIC_ETH3 & my_uic2msr) { /* look for EMAC errors */
991 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
992 if ((hw_p->emac_ier & emac_isr) != 0) {
993 emac_err (dev, emac_isr);
998 if ((hw_p->emac_ier & emac_isr)
999 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
1000 mtdcr (uic0sr, UIC_MRE | UIC_MTE); /* Clear */
1001 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1002 mtdcr (uic2sr, UIC_ETH3);
1003 return (rc); /* we had errors so get out */
1006 #endif /* CONFIG_440GX */
1007 /* handle MAX TX EOB interrupt from a tx */
1008 if (my_uic0msr & UIC_MTE) {
1009 mal_rx_eob = mfdcr (maltxeobisr);
1010 mtdcr (maltxeobisr, mal_rx_eob);
1011 mtdcr (uic0sr, UIC_MTE);
1013 /* handle MAL RX EOB interupt from a receive */
1014 /* check for EOB on valid channels */
1015 if (my_uic0msr & UIC_MRE) {
1016 mal_rx_eob = mfdcr (malrxeobisr);
1017 if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */
1019 mtdcr(malrxeobisr, mal_rx_eob); */
1020 enet_rcv (dev, emac_isr);
1021 /* indicate that we serviced an interrupt */
1026 mtdcr (uic0sr, UIC_MRE); /* Clear */
1027 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1028 switch (hw_p->devnum) {
1030 mtdcr (uic1sr, UIC_ETH0);
1033 mtdcr (uic1sr, UIC_ETH1);
1035 #if defined (CONFIG_440GX)
1037 mtdcr (uic2sr, UIC_ETH2);
1040 mtdcr (uic2sr, UIC_ETH3);
1042 #endif /* CONFIG_440GX */
1051 #else /* CONFIG_440 */
1053 int enetInt (struct eth_device *dev)
1056 int rc = -1; /* default to not us */
1057 unsigned long mal_isr;
1058 unsigned long emac_isr = 0;
1059 unsigned long mal_rx_eob;
1060 unsigned long my_uicmsr;
1062 EMAC_4XX_HW_PST hw_p;
1065 * Because the mal is generic, we need to get the current
1068 #if defined(CONFIG_NET_MULTI)
1069 dev = eth_get_dev();
1076 /* enter loop that stays in interrupt code until nothing to service */
1080 my_uicmsr = mfdcr (uicmsr);
1082 if ((my_uicmsr & (MAL_UIC_DEF | EMAC_UIC_DEF)) == 0) { /* not for us */
1085 /* get and clear controller status interrupts */
1086 /* look at Mal and EMAC interrupts */
1087 if ((MAL_UIC_DEF & my_uicmsr) != 0) { /* we have a MAL interrupt */
1088 mal_isr = mfdcr (malesr);
1089 /* look for mal error */
1090 if ((my_uicmsr & MAL_UIC_ERR) != 0) {
1091 mal_err (dev, mal_isr, my_uicmsr, MAL_UIC_DEF, MAL_UIC_ERR);
1097 /* port by port dispatch of emac interrupts */
1099 if ((SEL_UIC_DEF(hw_p->devnum) & my_uicmsr) != 0) { /* look for EMAC errors */
1100 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
1101 if ((hw_p->emac_ier & emac_isr) != 0) {
1102 emac_err (dev, emac_isr);
1107 if (((hw_p->emac_ier & emac_isr) != 0) || ((MAL_UIC_ERR & my_uicmsr) != 0)) {
1108 mtdcr (uicsr, MAL_UIC_DEF | SEL_UIC_DEF(hw_p->devnum)); /* Clear */
1109 return (rc); /* we had errors so get out */
1112 /* handle MAX TX EOB interrupt from a tx */
1113 if (my_uicmsr & UIC_MAL_TXEOB) {
1114 mal_rx_eob = mfdcr (maltxeobisr);
1115 mtdcr (maltxeobisr, mal_rx_eob);
1116 mtdcr (uicsr, UIC_MAL_TXEOB);
1118 /* handle MAL RX EOB interupt from a receive */
1119 /* check for EOB on valid channels */
1120 if (my_uicmsr & UIC_MAL_RXEOB)
1122 mal_rx_eob = mfdcr (malrxeobisr);
1123 if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */
1125 mtdcr(malrxeobisr, mal_rx_eob); */
1126 enet_rcv (dev, emac_isr);
1127 /* indicate that we serviced an interrupt */
1132 mtdcr (uicsr, MAL_UIC_DEF|EMAC_UIC_DEF|EMAC_UIC_DEF1); /* Clear */
1139 #endif /* CONFIG_440 */
1141 /*-----------------------------------------------------------------------------+
1143 *-----------------------------------------------------------------------------*/
1144 static void mal_err (struct eth_device *dev, unsigned long isr,
1145 unsigned long uic, unsigned long maldef,
1146 unsigned long mal_errr)
1148 EMAC_4XX_HW_PST hw_p = dev->priv;
1150 mtdcr (malesr, isr); /* clear interrupt */
1152 /* clear DE interrupt */
1153 mtdcr (maltxdeir, 0xC0000000);
1154 mtdcr (malrxdeir, 0x80000000);
1156 #ifdef INFO_4XX_ENET
1157 printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n", isr, uic, maldef, mal_errr);
1160 eth_init (hw_p->bis); /* start again... */
1163 /*-----------------------------------------------------------------------------+
1164 * EMAC Error Routine
1165 *-----------------------------------------------------------------------------*/
1166 static void emac_err (struct eth_device *dev, unsigned long isr)
1168 EMAC_4XX_HW_PST hw_p = dev->priv;
1170 printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr);
1171 out32 (EMAC_ISR + hw_p->hw_addr, isr);
1174 /*-----------------------------------------------------------------------------+
1175 * enet_rcv() handles the ethernet receive data
1176 *-----------------------------------------------------------------------------*/
1177 static void enet_rcv (struct eth_device *dev, unsigned long malisr)
1179 struct enet_frame *ef_ptr;
1180 unsigned long data_len;
1181 unsigned long rx_eob_isr;
1182 EMAC_4XX_HW_PST hw_p = dev->priv;
1188 rx_eob_isr = mfdcr (malrxeobisr);
1189 if ((0x80000000 >> hw_p->devnum) & rx_eob_isr) {
1191 mtdcr (malrxeobisr, rx_eob_isr);
1194 while (1) { /* do all */
1197 if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl)
1198 || (loop_count >= NUM_RX_BUFF))
1202 if (NUM_RX_BUFF == hw_p->rx_slot)
1205 data_len = (unsigned long) hw_p->rx[i].data_len; /* Get len */
1207 if (data_len > ENET_MAX_MTU) /* Check len */
1210 if (EMAC_RX_ERRORS & hw_p->rx[i].ctrl) { /* Check Errors */
1212 hw_p->stats.rx_err_log[hw_p->
1215 hw_p->rx_err_index++;
1216 if (hw_p->rx_err_index ==
1218 hw_p->rx_err_index =
1221 } /* data_len < max mtu */
1223 if (!data_len) { /* no data */
1224 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY; /* Free Recv Buffer */
1226 hw_p->stats.data_len_err++; /* Error at Rx */
1231 /* Check if user has already eaten buffer */
1232 /* if not => ERROR */
1233 else if (hw_p->rx_ready[hw_p->rx_i_index] != -1) {
1234 if (hw_p->is_receiving)
1235 printf ("ERROR : Receive buffers are full!\n");
1238 hw_p->stats.rx_frames++;
1239 hw_p->stats.rx += data_len;
1240 ef_ptr = (struct enet_frame *) hw_p->rx[i].
1242 #ifdef INFO_4XX_ENET
1243 hw_p->stats.pkts_rx++;
1248 hw_p->rx_ready[hw_p->rx_i_index] = i;
1250 if (NUM_RX_BUFF == hw_p->rx_i_index)
1251 hw_p->rx_i_index = 0;
1254 * free receive buffer only when
1255 * buffer has been handled (eth_rx)
1256 rx[i].ctrl |= MAL_RX_CTRL_EMPTY;
1260 } /* if EMACK_RXCHL */
1264 static int ppc_4xx_eth_rx (struct eth_device *dev)
1269 EMAC_4XX_HW_PST hw_p = dev->priv;
1271 hw_p->is_receiving = 1; /* tell driver */
1275 * use ring buffer and
1276 * get index from rx buffer desciptor queue
1278 user_index = hw_p->rx_ready[hw_p->rx_u_index];
1279 if (user_index == -1) {
1281 break; /* nothing received - leave for() loop */
1285 mtmsr (msr & ~(MSR_EE));
1287 length = hw_p->rx[user_index].data_len;
1289 /* Pass the packet up to the protocol layers. */
1290 /* NetReceive(NetRxPackets[rxIdx], length - 4); */
1291 /* NetReceive(NetRxPackets[i], length); */
1292 NetReceive (NetRxPackets[user_index], length - 4);
1293 /* Free Recv Buffer */
1294 hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY;
1295 /* Free rx buffer descriptor queue */
1296 hw_p->rx_ready[hw_p->rx_u_index] = -1;
1298 if (NUM_RX_BUFF == hw_p->rx_u_index)
1299 hw_p->rx_u_index = 0;
1301 #ifdef INFO_4XX_ENET
1302 hw_p->stats.pkts_handled++;
1305 mtmsr (msr); /* Enable IRQ's */
1308 hw_p->is_receiving = 0; /* tell driver */
1313 int ppc_4xx_eth_initialize (bd_t * bis)
1315 static int virgin = 0;
1316 struct eth_device *dev;
1318 EMAC_4XX_HW_PST hw = NULL;
1320 #if defined(CONFIG_440GX)
1323 mfsdr (sdr_pfc1, pfc1);
1324 pfc1 &= ~(0x01e00000);
1326 mtsdr (sdr_pfc1, pfc1);
1328 /* set phy num and mode */
1329 bis->bi_phynum[0] = CONFIG_PHY_ADDR;
1330 #if defined(CONFIG_PHY1_ADDR)
1331 bis->bi_phynum[1] = CONFIG_PHY1_ADDR;
1333 #if defined(CONFIG_440GX)
1334 bis->bi_phynum[2] = CONFIG_PHY2_ADDR;
1335 bis->bi_phynum[3] = CONFIG_PHY3_ADDR;
1336 bis->bi_phymode[0] = 0;
1337 bis->bi_phymode[1] = 0;
1338 bis->bi_phymode[2] = 2;
1339 bis->bi_phymode[3] = 2;
1341 #if defined (CONFIG_440GX)
1342 ppc_4xx_eth_setup_bridge(0, bis);
1346 for (eth_num = 0; eth_num < EMAC_NUM_DEV; eth_num++) {
1348 /* See if we can actually bring up the interface, otherwise, skip it */
1350 default: /* fall through */
1352 if (memcmp (bis->bi_enetaddr, "\0\0\0\0\0\0", 6) == 0) {
1353 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
1357 #ifdef CONFIG_HAS_ETH1
1359 if (memcmp (bis->bi_enet1addr, "\0\0\0\0\0\0", 6) == 0) {
1360 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
1365 #ifdef CONFIG_HAS_ETH2
1367 if (memcmp (bis->bi_enet2addr, "\0\0\0\0\0\0", 6) == 0) {
1368 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
1373 #ifdef CONFIG_HAS_ETH3
1375 if (memcmp (bis->bi_enet3addr, "\0\0\0\0\0\0", 6) == 0) {
1376 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
1383 /* Allocate device structure */
1384 dev = (struct eth_device *) malloc (sizeof (*dev));
1386 printf ("ppc_4xx_eth_initialize: "
1387 "Cannot allocate eth_device %d\n", eth_num);
1390 memset(dev, 0, sizeof(*dev));
1392 /* Allocate our private use data */
1393 hw = (EMAC_4XX_HW_PST) malloc (sizeof (*hw));
1395 printf ("ppc_4xx_eth_initialize: "
1396 "Cannot allocate private hw data for eth_device %d",
1401 memset(hw, 0, sizeof(*hw));
1404 default: /* fall through */
1407 memcpy (dev->enetaddr, bis->bi_enetaddr, 6);
1409 #ifdef CONFIG_HAS_ETH1
1411 hw->hw_addr = 0x100;
1412 memcpy (dev->enetaddr, bis->bi_enet1addr, 6);
1415 #ifdef CONFIG_HAS_ETH2
1417 hw->hw_addr = 0x400;
1418 memcpy (dev->enetaddr, bis->bi_enet2addr, 6);
1421 #ifdef CONFIG_HAS_ETH3
1423 hw->hw_addr = 0x600;
1424 memcpy (dev->enetaddr, bis->bi_enet3addr, 6);
1429 hw->devnum = eth_num;
1430 hw->print_speed = 1;
1432 sprintf (dev->name, "ppc_4xx_eth%d", eth_num);
1433 dev->priv = (void *) hw;
1434 dev->init = ppc_4xx_eth_init;
1435 dev->halt = ppc_4xx_eth_halt;
1436 dev->send = ppc_4xx_eth_send;
1437 dev->recv = ppc_4xx_eth_rx;
1440 /* set the MAL IER ??? names may change with new spec ??? */
1442 MAL_IER_DE | MAL_IER_NE | MAL_IER_TE |
1443 MAL_IER_OPBE | MAL_IER_PLBE;
1444 mtdcr (malesr, 0xffffffff); /* clear pending interrupts */
1445 mtdcr (maltxdeir, 0xffffffff); /* clear pending interrupts */
1446 mtdcr (malrxdeir, 0xffffffff); /* clear pending interrupts */
1447 mtdcr (malier, mal_ier);
1449 /* install MAL interrupt handler */
1450 irq_install_handler (VECNUM_MS,
1451 (interrupt_handler_t *) enetInt,
1453 irq_install_handler (VECNUM_MTE,
1454 (interrupt_handler_t *) enetInt,
1456 irq_install_handler (VECNUM_MRE,
1457 (interrupt_handler_t *) enetInt,
1459 irq_install_handler (VECNUM_TXDE,
1460 (interrupt_handler_t *) enetInt,
1462 irq_install_handler (VECNUM_RXDE,
1463 (interrupt_handler_t *) enetInt,
1468 #if defined(CONFIG_NET_MULTI)
1474 } /* end for each supported device */
1479 #if !defined(CONFIG_NET_MULTI)
1480 void eth_halt (void) {
1482 ppc_4xx_eth_halt(emac0_dev);
1488 int eth_init (bd_t *bis)
1490 ppc_4xx_eth_initialize(bis);
1492 return ppc_4xx_eth_init(emac0_dev, bis);
1494 printf("ERROR: ethaddr not set!\n");
1499 int eth_send(volatile void *packet, int length)
1501 return (ppc_4xx_eth_send(emac0_dev, packet, length));
1506 return (ppc_4xx_eth_rx(emac0_dev));
1508 #endif /* !defined(CONFIG_NET_MULTI) */
1510 #endif /* #if (CONFIG_COMMANDS & CFG_CMD_NET) */