1 /*-----------------------------------------------------------------------------+
3 * This source code has been made available to you by IBM on an AS-IS
4 * basis. Anyone receiving this source is licensed under IBM
5 * copyrights to use it in any way he or she deems fit, including
6 * copying it, modifying it, compiling it, and redistributing it either
7 * with or without modifications. No license under IBM patents or
8 * patent applications is to be implied by the copyright license.
10 * Any user of this software should understand that IBM cannot provide
11 * technical support for this software and will not be responsible for
12 * any consequences resulting from the use of this software.
14 * Any person who transfers this source code or any derivative work
15 * must include the IBM copyright notice, this paragraph, and the
16 * preceding two paragraphs in the transferred software.
18 * COPYRIGHT I B M CORPORATION 1995
19 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 *-----------------------------------------------------------------------------*/
21 /*-----------------------------------------------------------------------------+
23 * File Name: enetemac.c
25 * Function: Device driver for the ethernet EMAC3 macro on the 405GP.
31 * Date Description of Change BY
32 * --------- --------------------- ---
33 * 05-May-99 Created MKW
34 * 27-Jun-99 Clean up JWB
35 * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW
36 * 29-Jul-99 Added Full duplex support MKW
37 * 06-Aug-99 Changed names for Mal CR reg MKW
38 * 23-Aug-99 Turned off SYE when running at 10Mbs MKW
39 * 24-Aug-99 Marked descriptor empty after call_xlc MKW
40 * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG
41 * to avoid chaining maximum sized packets. Push starting
42 * RX descriptor address up to the next cache line boundary.
43 * 16-Jan-00 Added support for booting with IP of 0x0 MKW
44 * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the
45 * EMAC_RXM register. JWB
46 * 12-Mar-01 anne-sophie.harnois@nextream.fr
47 * - Variables are compatible with those already defined in
49 * - Receive buffer descriptor ring is used to send buffers
51 * - Info print about send/received/handled packet number if
52 * INFO_405_ENET is set
53 * 17-Apr-01 stefan.roese@esd-electronics.com
54 * - MAL reset in "eth_halt" included
55 * - Enet speed and duplex output now in one line
56 * 08-May-01 stefan.roese@esd-electronics.com
57 * - MAL error handling added (eth_init called again)
58 * 13-Nov-01 stefan.roese@esd-electronics.com
59 * - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex
60 * 04-Jan-02 stefan.roese@esd-electronics.com
61 * - Wait for PHY auto negotiation to complete added
62 * 06-Feb-02 stefan.roese@esd-electronics.com
63 * - Bug fixed in waiting for auto negotiation to complete
64 * 26-Feb-02 stefan.roese@esd-electronics.com
65 * - rx and tx buffer descriptors now allocated (no fixed address
67 * 17-Jun-02 stefan.roese@esd-electronics.com
68 * - MAL error debug printf 'M' removed (rx de interrupt may
69 * occur upon many incoming packets with only 4 rx buffers).
70 *-----------------------------------------------------------------------------*
71 * 17-Nov-03 travis.sawyer@sandburst.com
72 * - ported from 405gp_enet.c to utilized upto 4 EMAC ports
73 * in the 440GX. This port should work with the 440GP
75 * 15-Aug-05 sr@denx.de
76 * - merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c
77 now handling all 4xx cpu's.
78 *-----------------------------------------------------------------------------*/
83 #include <asm/processor.h>
85 #include <asm/cache.h>
89 #include <ppc4xx_enet.h>
93 #include <asm/ppc4xx-intvec.h>
96 * Only compile for platform with AMCC EMAC ethernet controller and
97 * network support enabled.
98 * Remark: CONFIG_405 describes Xilinx PPC405 FPGA without EMAC controller!
100 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_405) && !defined(CONFIG_IOP480)
102 #if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
103 #error "CONFIG_MII has to be defined!"
106 #if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_NET_MULTI)
107 #error "CONFIG_NET_MULTI has to be defined for NetConsole"
110 #define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
111 #define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* 5000 ms autonegotiate timeout */
113 /* Ethernet Transmit and Receive Buffers */
115 * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
116 * PKTSIZE and PKTSIZE_ALIGN (include/net.h)
118 #define ENET_MAX_MTU PKTSIZE
119 #define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
121 /*-----------------------------------------------------------------------------+
122 * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
123 * Interrupt Controller).
124 *-----------------------------------------------------------------------------*/
125 #define MAL_UIC_ERR ( UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)
126 #define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR)
127 #define EMAC_UIC_DEF UIC_ENET
128 #define EMAC_UIC_DEF1 UIC_ENET1
129 #define SEL_UIC_DEF(p) (p ? UIC_ENET1 : UIC_ENET )
133 #define BI_PHYMODE_NONE 0
134 #define BI_PHYMODE_ZMII 1
135 #define BI_PHYMODE_RGMII 2
136 #define BI_PHYMODE_GMII 3
137 #define BI_PHYMODE_RTBI 4
138 #define BI_PHYMODE_TBI 5
139 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
140 defined(CONFIG_405EX)
141 #define BI_PHYMODE_SMII 6
142 #define BI_PHYMODE_MII 7
145 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
146 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
147 defined(CONFIG_405EX)
148 #define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1))
151 /*-----------------------------------------------------------------------------+
152 * Global variables. TX and RX descriptors and buffers.
153 *-----------------------------------------------------------------------------*/
155 static uint32_t mal_ier;
157 #if !defined(CONFIG_NET_MULTI)
158 struct eth_device *emac0_dev = NULL;
162 * Get count of EMAC devices (doesn't have to be the max. possible number
163 * supported by the cpu)
165 * CONFIG_BOARD_EMAC_COUNT added so now a "dynamic" way to configure the
166 * EMAC count is possible. As it is needed for the Kilauea/Haleakala
167 * 405EX/405EXr eval board, using the same binary.
169 #if defined(CONFIG_BOARD_EMAC_COUNT)
170 #define LAST_EMAC_NUM board_emac_count()
171 #else /* CONFIG_BOARD_EMAC_COUNT */
172 #if defined(CONFIG_HAS_ETH3)
173 #define LAST_EMAC_NUM 4
174 #elif defined(CONFIG_HAS_ETH2)
175 #define LAST_EMAC_NUM 3
176 #elif defined(CONFIG_HAS_ETH1)
177 #define LAST_EMAC_NUM 2
179 #define LAST_EMAC_NUM 1
181 #endif /* CONFIG_BOARD_EMAC_COUNT */
183 /* normal boards start with EMAC0 */
184 #if !defined(CONFIG_EMAC_NR_START)
185 #define CONFIG_EMAC_NR_START 0
188 #if defined(CONFIG_405EX) || defined(CONFIG_440EPX)
189 #define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev)))
191 #define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev) * 2))
194 #define MAL_RX_DESC_SIZE 2048
195 #define MAL_TX_DESC_SIZE 2048
196 #define MAL_ALLOC_SIZE (MAL_TX_DESC_SIZE + MAL_RX_DESC_SIZE)
198 /*-----------------------------------------------------------------------------+
199 * Prototypes and externals.
200 *-----------------------------------------------------------------------------*/
201 static void enet_rcv (struct eth_device *dev, unsigned long malisr);
203 int enetInt (struct eth_device *dev);
204 static void mal_err (struct eth_device *dev, unsigned long isr,
205 unsigned long uic, unsigned long maldef,
206 unsigned long mal_errr);
207 static void emac_err (struct eth_device *dev, unsigned long isr);
209 extern int phy_setup_aneg (char *devname, unsigned char addr);
210 extern int emac4xx_miiphy_read (char *devname, unsigned char addr,
211 unsigned char reg, unsigned short *value);
212 extern int emac4xx_miiphy_write (char *devname, unsigned char addr,
213 unsigned char reg, unsigned short value);
215 int board_emac_count(void);
217 /*-----------------------------------------------------------------------------+
219 | Disable MAL channel, and EMACn
220 +-----------------------------------------------------------------------------*/
221 static void ppc_4xx_eth_halt (struct eth_device *dev)
223 EMAC_4XX_HW_PST hw_p = dev->priv;
224 uint32_t failsafe = 10000;
225 #if defined(CONFIG_440SPE) || \
226 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
227 defined(CONFIG_405EX)
231 out_be32((void *)EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */
233 /* 1st reset MAL channel */
234 /* Note: writing a 0 to a channel has no effect */
235 #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
236 mtdcr (maltxcarr, (MAL_CR_MMSR >> (hw_p->devnum * 2)));
238 mtdcr (maltxcarr, (MAL_CR_MMSR >> hw_p->devnum));
240 mtdcr (malrxcarr, (MAL_CR_MMSR >> hw_p->devnum));
243 while (mfdcr (malrxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
244 udelay (1000); /* Delay 1 MS so as not to hammer the register */
251 #if defined(CONFIG_440SPE) || \
252 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
253 defined(CONFIG_405EX)
254 /* provide clocks for EMAC internal loopback */
255 mfsdr (sdr_mfr, mfr);
256 mfr |= SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
260 out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
262 #if defined(CONFIG_440SPE) || \
263 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
264 defined(CONFIG_405EX)
265 /* remove clocks for EMAC internal loopback */
266 mfsdr (sdr_mfr, mfr);
267 mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
272 #ifndef CONFIG_NETCONSOLE
273 hw_p->print_speed = 1; /* print speed message again next time */
279 #if defined (CONFIG_440GX)
280 int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
283 unsigned long zmiifer;
284 unsigned long rmiifer;
286 mfsdr(sdr_pfc1, pfc1);
287 pfc1 = SDR0_PFC1_EPS_DECODE(pfc1);
294 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
295 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
296 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2);
297 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3);
298 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
299 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
300 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
301 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
304 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
305 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
306 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2);
307 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3);
308 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
309 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
310 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
311 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
314 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
315 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
316 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
317 bis->bi_phymode[1] = BI_PHYMODE_NONE;
318 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
319 bis->bi_phymode[3] = BI_PHYMODE_NONE;
322 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
323 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
324 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (2);
325 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (3);
326 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
327 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
328 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
329 bis->bi_phymode[3] = BI_PHYMODE_RGMII;
332 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
333 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
334 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (2);
335 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
336 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
337 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
338 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
339 bis->bi_phymode[3] = BI_PHYMODE_RGMII;
342 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
343 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
344 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
345 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
346 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
347 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
351 zmiifer = ZMII_FER_MII << ZMII_FER_V(devnum);
353 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
354 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
355 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
356 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
360 /* Ensure we setup mdio for this devnum and ONLY this devnum */
361 zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
363 out_be32((void *)ZMII_FER, zmiifer);
364 out_be32((void *)RGMII_FER, rmiifer);
368 #endif /* CONFIG_440_GX */
370 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
371 int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
373 unsigned long zmiifer=0x0;
376 mfsdr(sdr_pfc1, pfc1);
377 pfc1 &= SDR0_PFC1_SELECT_MASK;
380 case SDR0_PFC1_SELECT_CONFIG_2:
382 out_be32((void *)ZMII_FER, 0x00);
383 out_be32((void *)RGMII_FER, 0x00000037);
384 bis->bi_phymode[0] = BI_PHYMODE_GMII;
385 bis->bi_phymode[1] = BI_PHYMODE_NONE;
387 case SDR0_PFC1_SELECT_CONFIG_4:
388 /* 2 x RGMII ports */
389 out_be32((void *)ZMII_FER, 0x00);
390 out_be32((void *)RGMII_FER, 0x00000055);
391 bis->bi_phymode[0] = BI_PHYMODE_RGMII;
392 bis->bi_phymode[1] = BI_PHYMODE_RGMII;
394 case SDR0_PFC1_SELECT_CONFIG_6:
396 out_be32((void *)ZMII_FER,
397 ((ZMII_FER_SMII) << ZMII_FER_V(0)) |
398 ((ZMII_FER_SMII) << ZMII_FER_V(1)));
399 out_be32((void *)RGMII_FER, 0x00000000);
400 bis->bi_phymode[0] = BI_PHYMODE_SMII;
401 bis->bi_phymode[1] = BI_PHYMODE_SMII;
403 case SDR0_PFC1_SELECT_CONFIG_1_2:
404 /* only 1 x MII supported */
405 out_be32((void *)ZMII_FER, (ZMII_FER_MII) << ZMII_FER_V(0));
406 out_be32((void *)RGMII_FER, 0x00000000);
407 bis->bi_phymode[0] = BI_PHYMODE_MII;
408 bis->bi_phymode[1] = BI_PHYMODE_NONE;
414 /* Ensure we setup mdio for this devnum and ONLY this devnum */
415 zmiifer = in_be32((void *)ZMII_FER);
416 zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
417 out_be32((void *)ZMII_FER, zmiifer);
421 #endif /* CONFIG_440EPX */
423 #if defined(CONFIG_405EX)
424 int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
429 * Right now only 2*RGMII is supported. Please extend when needed.
434 /* 2 x RGMII ports */
435 out_be32((void *)RGMII_FER, 0x00000055);
436 bis->bi_phymode[0] = BI_PHYMODE_RGMII;
437 bis->bi_phymode[1] = BI_PHYMODE_RGMII;
446 /* Ensure we setup mdio for this devnum and ONLY this devnum */
447 gmiifer = in_be32((void *)RGMII_FER);
448 gmiifer |= (1 << (19-devnum));
449 out_be32((void *)RGMII_FER, gmiifer);
453 #endif /* CONFIG_405EX */
455 static inline void *malloc_aligned(u32 size, u32 align)
457 return (void *)(((u32)malloc(size + align) + align - 1) &
461 static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
464 unsigned long reg = 0;
467 unsigned long duplex;
468 unsigned long failsafe;
470 unsigned short devnum;
471 unsigned short reg_short;
472 #if defined(CONFIG_440GX) || \
473 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
474 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
475 defined(CONFIG_405EX)
477 #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
478 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
479 defined(CONFIG_405EX)
483 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
484 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
485 defined(CONFIG_405EX)
491 EMAC_4XX_HW_PST hw_p = dev->priv;
493 /* before doing anything, figure out if we have a MAC address */
495 if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0) {
496 printf("ERROR: ethaddr not set!\n");
500 #if defined(CONFIG_440GX) || \
501 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
502 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
503 defined(CONFIG_405EX)
504 /* Need to get the OPB frequency so we can access the PHY */
505 get_sys_info (&sysinfo);
509 mtmsr (msr & ~(MSR_EE)); /* disable interrupts */
511 devnum = hw_p->devnum;
516 * hw_p->stats.pkts_handled <= hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX
517 * In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it
518 * is possible that new packets (without relationship with
519 * current transfer) have got the time to arrived before
520 * netloop calls eth_halt
522 printf ("About preceeding transfer (eth%d):\n"
523 "- Sent packet number %d\n"
524 "- Received packet number %d\n"
525 "- Handled packet number %d\n",
528 hw_p->stats.pkts_rx, hw_p->stats.pkts_handled);
530 hw_p->stats.pkts_tx = 0;
531 hw_p->stats.pkts_rx = 0;
532 hw_p->stats.pkts_handled = 0;
533 hw_p->print_speed = 1; /* print speed message again next time */
536 hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */
537 hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */
539 hw_p->rx_slot = 0; /* MAL Receive Slot */
540 hw_p->rx_i_index = 0; /* Receive Interrupt Queue Index */
541 hw_p->rx_u_index = 0; /* Receive User Queue Index */
543 hw_p->tx_slot = 0; /* MAL Transmit Slot */
544 hw_p->tx_i_index = 0; /* Transmit Interrupt Queue Index */
545 hw_p->tx_u_index = 0; /* Transmit User Queue Index */
547 #if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
549 /* NOTE: 440GX spec states that mode is mutually exclusive */
550 /* NOTE: Therefore, disable all other EMACS, since we handle */
551 /* NOTE: only one emac at a time */
553 out_be32((void *)ZMII_FER, 0);
556 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
557 out_be32((void *)ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
558 #elif defined(CONFIG_440GX) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
559 ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
560 #elif defined(CONFIG_440GP)
562 out_be32((void *)ZMII_FER, ZMII_RMII | ZMII_MDI0);
564 if ((devnum == 0) || (devnum == 1)) {
565 out_be32((void *)ZMII_FER, (ZMII_FER_SMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
566 } else { /* ((devnum == 2) || (devnum == 3)) */
567 out_be32((void *)ZMII_FER, ZMII_FER_MDI << ZMII_FER_V (devnum));
568 out_be32((void *)RGMII_FER, ((RGMII_FER_RGMII << RGMII_FER_V (2)) |
569 (RGMII_FER_RGMII << RGMII_FER_V (3))));
573 out_be32((void *)ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum));
574 #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
575 #if defined(CONFIG_405EX)
576 ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
579 __asm__ volatile ("eieio");
581 /* reset emac so we have access to the phy */
582 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
583 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
584 defined(CONFIG_405EX)
585 /* provide clocks for EMAC internal loopback */
586 mfsdr (sdr_mfr, mfr);
587 mfr |= SDR0_MFR_ETH_CLK_SEL_V(devnum);
591 out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
594 while ((in_be32((void *)EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) {
599 printf("\nProblem resetting EMAC!\n");
601 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
602 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
603 defined(CONFIG_405EX)
604 /* remove clocks for EMAC internal loopback */
605 mfsdr (sdr_mfr, mfr);
606 mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(devnum);
610 #if defined(CONFIG_440GX) || \
611 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
612 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
613 defined(CONFIG_405EX)
614 /* Whack the M1 register */
616 mode_reg &= ~0x00000038;
617 if (sysinfo.freqOPB <= 50000000);
618 else if (sysinfo.freqOPB <= 66666667)
619 mode_reg |= EMAC_M1_OBCI_66;
620 else if (sysinfo.freqOPB <= 83333333)
621 mode_reg |= EMAC_M1_OBCI_83;
622 else if (sysinfo.freqOPB <= 100000000)
623 mode_reg |= EMAC_M1_OBCI_100;
625 mode_reg |= EMAC_M1_OBCI_GT100;
627 out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg);
628 #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
630 /* wait for PHY to complete auto negotiation */
632 #ifndef CONFIG_CS8952_PHY
635 reg = CONFIG_PHY_ADDR;
637 #if defined (CONFIG_PHY1_ADDR)
639 reg = CONFIG_PHY1_ADDR;
642 #if defined (CONFIG_440GX)
644 reg = CONFIG_PHY2_ADDR;
647 reg = CONFIG_PHY3_ADDR;
651 reg = CONFIG_PHY_ADDR;
655 bis->bi_phynum[devnum] = reg;
657 #if defined(CONFIG_PHY_RESET)
659 * Reset the phy, only if its the first time through
660 * otherwise, just check the speeds & feeds
662 if (hw_p->first_init == 0) {
663 #if defined(CONFIG_M88E1111_PHY)
664 miiphy_write (dev->name, reg, 0x14, 0x0ce3);
665 miiphy_write (dev->name, reg, 0x18, 0x4101);
666 miiphy_write (dev->name, reg, 0x09, 0x0e00);
667 miiphy_write (dev->name, reg, 0x04, 0x01e1);
669 miiphy_reset (dev->name, reg);
671 #if defined(CONFIG_440GX) || \
672 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
673 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
674 defined(CONFIG_405EX)
676 #if defined(CONFIG_CIS8201_PHY)
678 * Cicada 8201 PHY needs to have an extended register whacked
681 if (((devnum == 2) || (devnum == 3)) && (4 == ethgroup)) {
682 #if defined(CONFIG_CIS8201_SHORT_ETCH)
683 miiphy_write (dev->name, reg, 23, 0x1300);
685 miiphy_write (dev->name, reg, 23, 0x1000);
688 * Vitesse VSC8201/Cicada CIS8201 errata:
689 * Interoperability problem with Intel 82547EI phys
690 * This work around (provided by Vitesse) changes
691 * the default timer convergence from 8ms to 12ms
693 miiphy_write (dev->name, reg, 0x1f, 0x2a30);
694 miiphy_write (dev->name, reg, 0x08, 0x0200);
695 miiphy_write (dev->name, reg, 0x1f, 0x52b5);
696 miiphy_write (dev->name, reg, 0x02, 0x0004);
697 miiphy_write (dev->name, reg, 0x01, 0x0671);
698 miiphy_write (dev->name, reg, 0x00, 0x8fae);
699 miiphy_write (dev->name, reg, 0x1f, 0x2a30);
700 miiphy_write (dev->name, reg, 0x08, 0x0000);
701 miiphy_write (dev->name, reg, 0x1f, 0x0000);
702 /* end Vitesse/Cicada errata */
706 #if defined(CONFIG_ET1011C_PHY)
708 * Agere ET1011c PHY needs to have an extended register whacked
711 if (((devnum == 2) || (devnum ==3)) && (4 == ethgroup)) {
712 miiphy_read (dev->name, reg, 0x16, ®_short);
714 reg_short |= 0x6; /* RGMII DLL Delay*/
715 miiphy_write (dev->name, reg, 0x16, reg_short);
717 miiphy_read (dev->name, reg, 0x17, ®_short);
718 reg_short &= ~(0x40);
719 miiphy_write (dev->name, reg, 0x17, reg_short);
721 miiphy_write(dev->name, reg, 0x1c, 0x74f0);
726 /* Start/Restart autonegotiation */
727 phy_setup_aneg (dev->name, reg);
730 #endif /* defined(CONFIG_PHY_RESET) */
732 miiphy_read (dev->name, reg, PHY_BMSR, ®_short);
735 * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
737 if ((reg_short & PHY_BMSR_AUTN_ABLE)
738 && !(reg_short & PHY_BMSR_AUTN_COMP)) {
739 puts ("Waiting for PHY auto negotiation to complete");
741 while (!(reg_short & PHY_BMSR_AUTN_COMP)) {
745 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
746 puts (" TIMEOUT !\n");
750 if ((i++ % 1000) == 0) {
753 udelay (1000); /* 1 ms */
754 miiphy_read (dev->name, reg, PHY_BMSR, ®_short);
758 udelay (500000); /* another 500 ms (results in faster booting) */
760 #endif /* #ifndef CONFIG_CS8952_PHY */
762 speed = miiphy_speed (dev->name, reg);
763 duplex = miiphy_duplex (dev->name, reg);
765 if (hw_p->print_speed) {
766 hw_p->print_speed = 0;
767 printf ("ENET Speed is %d Mbps - %s duplex connection (EMAC%d)\n",
768 (int) speed, (duplex == HALF) ? "HALF" : "FULL",
772 #if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
773 !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
774 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
777 reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M;
779 reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
784 /* Set ZMII/RGMII speed according to the phy link speed */
785 reg = in_be32((void *)ZMII_SSR);
786 if ( (speed == 100) || (speed == 1000) )
787 out_be32((void *)ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum)));
789 out_be32((void *)ZMII_SSR, reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum))));
791 if ((devnum == 2) || (devnum == 3)) {
793 reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
794 else if (speed == 100)
795 reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
796 else if (speed == 10)
797 reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
799 printf("Error in RGMII Speed\n");
802 out_be32((void *)RGMII_SSR, reg);
804 #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
806 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
807 defined(CONFIG_405EX)
809 reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
810 else if (speed == 100)
811 reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
812 else if (speed == 10)
813 reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
815 printf("Error in RGMII Speed\n");
818 out_be32((void *)RGMII_SSR, reg);
821 /* set the Mal configuration reg */
822 #if defined(CONFIG_440GX) || \
823 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
824 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
825 defined(CONFIG_405EX)
826 mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
827 MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
829 mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
830 /* Errata 1.12: MAL_1 -- Disable MAL bursting */
831 if (get_pvr() == PVR_440GP_RB) {
832 mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB);
837 * Malloc MAL buffer desciptors, make sure they are
838 * aligned on cache line boundary size
839 * (401/403/IOP480 = 16, 405 = 32)
840 * and doesn't cross cache block boundaries.
842 if (hw_p->first_init == 0) {
843 debug("*** Allocating descriptor memory ***\n");
845 bd_cached = (u32)malloc_aligned(MAL_ALLOC_SIZE, 4096);
847 printf("%s: Error allocating MAL descriptor buffers!\n");
851 #ifdef CONFIG_4xx_DCACHE
852 flush_dcache_range(bd_cached, bd_cached + MAL_ALLOC_SIZE);
853 bd_uncached = bis->bi_memsize;
854 program_tlb(bd_cached, bd_uncached, MAL_ALLOC_SIZE,
857 bd_uncached = bd_cached;
859 hw_p->tx_phys = bd_cached;
860 hw_p->rx_phys = bd_cached + MAL_TX_DESC_SIZE;
861 hw_p->tx = (mal_desc_t *)(bd_uncached);
862 hw_p->rx = (mal_desc_t *)(bd_uncached + MAL_TX_DESC_SIZE);
863 debug("hw_p->tx=%08x, hw_p->rx=%08x\n", hw_p->tx, hw_p->rx);
866 for (i = 0; i < NUM_TX_BUFF; i++) {
867 hw_p->tx[i].ctrl = 0;
868 hw_p->tx[i].data_len = 0;
869 if (hw_p->first_init == 0)
870 hw_p->txbuf_ptr = malloc_aligned(MAL_ALLOC_SIZE,
872 hw_p->tx[i].data_ptr = hw_p->txbuf_ptr;
873 if ((NUM_TX_BUFF - 1) == i)
874 hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP;
875 hw_p->tx_run[i] = -1;
876 debug("TX_BUFF %d @ 0x%08lx\n", i, (u32)hw_p->tx[i].data_ptr);
879 for (i = 0; i < NUM_RX_BUFF; i++) {
880 hw_p->rx[i].ctrl = 0;
881 hw_p->rx[i].data_len = 0;
882 hw_p->rx[i].data_ptr = (char *)NetRxPackets[i];
883 if ((NUM_RX_BUFF - 1) == i)
884 hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP;
885 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR;
886 hw_p->rx_ready[i] = -1;
887 debug("RX_BUFF %d @ 0x%08lx\n", i, (u32)hw_p->rx[i].data_ptr);
892 reg |= dev->enetaddr[0]; /* set high address */
894 reg |= dev->enetaddr[1];
896 out_be32((void *)EMAC_IAH + hw_p->hw_addr, reg);
899 reg |= dev->enetaddr[2]; /* set low address */
901 reg |= dev->enetaddr[3];
903 reg |= dev->enetaddr[4];
905 reg |= dev->enetaddr[5];
907 out_be32((void *)EMAC_IAL + hw_p->hw_addr, reg);
911 /* setup MAL tx & rx channel pointers */
912 #if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR)
913 mtdcr (maltxctp2r, hw_p->tx_phys);
915 mtdcr (maltxctp1r, hw_p->tx_phys);
917 #if defined(CONFIG_440)
918 mtdcr (maltxbattr, 0x0);
919 mtdcr (malrxbattr, 0x0);
921 mtdcr (malrxctp1r, hw_p->rx_phys);
922 /* set RX buffer size */
923 mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16);
925 #if defined (CONFIG_440GX)
927 /* setup MAL tx & rx channel pointers */
928 mtdcr (maltxbattr, 0x0);
929 mtdcr (malrxbattr, 0x0);
930 mtdcr (maltxctp2r, hw_p->tx_phys);
931 mtdcr (malrxctp2r, hw_p->rx_phys);
932 /* set RX buffer size */
933 mtdcr (malrcbs2, ENET_MAX_MTU_ALIGNED / 16);
936 /* setup MAL tx & rx channel pointers */
937 mtdcr (maltxbattr, 0x0);
938 mtdcr (maltxctp3r, hw_p->tx_phys);
939 mtdcr (malrxbattr, 0x0);
940 mtdcr (malrxctp3r, hw_p->rx_phys);
941 /* set RX buffer size */
942 mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16);
944 #endif /* CONFIG_440GX */
947 /* setup MAL tx & rx channel pointers */
948 #if defined(CONFIG_440)
949 mtdcr (maltxbattr, 0x0);
950 mtdcr (malrxbattr, 0x0);
952 mtdcr (maltxctp0r, hw_p->tx_phys);
953 mtdcr (malrxctp0r, hw_p->rx_phys);
954 /* set RX buffer size */
955 mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16);
959 /* Enable MAL transmit and receive channels */
960 #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
961 mtdcr (maltxcasr, (MAL_TXRX_CASR >> (hw_p->devnum*2)));
963 mtdcr (maltxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
965 mtdcr (malrxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
967 /* set transmit enable & receive enable */
968 out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);
970 /* set receive fifo to 4k and tx fifo to 2k */
971 mode_reg = in_be32((void *)EMAC_M1 + hw_p->hw_addr);
972 mode_reg |= EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K;
975 if (speed == _1000BASET) {
976 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
977 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
980 mfsdr (sdr_pfc1, pfc1);
981 pfc1 |= SDR0_PFC1_EM_1000;
982 mtsdr (sdr_pfc1, pfc1);
984 mode_reg = mode_reg | EMAC_M1_MF_1000MBPS | EMAC_M1_IST;
985 } else if (speed == _100BASET)
986 mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST;
988 mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */
990 mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST;
992 out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg);
994 /* Enable broadcast and indvidual address */
995 /* TBS: enabling runts as some misbehaved nics will send runts */
996 out_be32((void *)EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE);
998 /* we probably need to set the tx mode1 reg? maybe at tx time */
1000 /* set transmit request threshold register */
1001 out_be32((void *)EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */
1003 /* set receive low/high water mark register */
1004 #if defined(CONFIG_440)
1005 /* 440s has a 64 byte burst length */
1006 out_be32((void *)EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000);
1008 /* 405s have a 16 byte burst length */
1009 out_be32((void *)EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000);
1010 #endif /* defined(CONFIG_440) */
1011 out_be32((void *)EMAC_TXM1 + hw_p->hw_addr, 0xf8640000);
1013 /* Set fifo limit entry in tx mode 0 */
1014 out_be32((void *)EMAC_TXM0 + hw_p->hw_addr, 0x00000003);
1016 out_be32((void *)EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008);
1019 hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE;
1020 if (speed == _100BASET)
1021 hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE;
1023 out_be32((void *)EMAC_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */
1024 out_be32((void *)EMAC_IER + hw_p->hw_addr, hw_p->emac_ier);
1026 if (hw_p->first_init == 0) {
1028 * Connect interrupt service routines
1030 irq_install_handler(ETH_IRQ_NUM(hw_p->devnum),
1031 (interrupt_handler_t *) enetInt, dev);
1034 mtmsr (msr); /* enable interrupts again */
1037 hw_p->first_init = 1;
1043 static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr,
1046 struct enet_frame *ef_ptr;
1047 ulong time_start, time_now;
1048 unsigned long temp_txm0;
1049 EMAC_4XX_HW_PST hw_p = dev->priv;
1051 ef_ptr = (struct enet_frame *) ptr;
1053 /*-----------------------------------------------------------------------+
1054 * Copy in our address into the frame.
1055 *-----------------------------------------------------------------------*/
1056 (void) memcpy (ef_ptr->source_addr, dev->enetaddr, ENET_ADDR_LENGTH);
1058 /*-----------------------------------------------------------------------+
1059 * If frame is too long or too short, modify length.
1060 *-----------------------------------------------------------------------*/
1061 /* TBS: where does the fragment go???? */
1062 if (len > ENET_MAX_MTU)
1065 /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */
1066 memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len);
1067 flush_dcache_range((u32)hw_p->txbuf_ptr, (u32)hw_p->txbuf_ptr + len);
1069 /*-----------------------------------------------------------------------+
1070 * set TX Buffer busy, and send it
1071 *-----------------------------------------------------------------------*/
1072 hw_p->tx[hw_p->tx_slot].ctrl = (MAL_TX_CTRL_LAST |
1073 EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) &
1074 ~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA);
1075 if ((NUM_TX_BUFF - 1) == hw_p->tx_slot)
1076 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_WRAP;
1078 hw_p->tx[hw_p->tx_slot].data_len = (short) len;
1079 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY;
1081 __asm__ volatile ("eieio");
1083 out_be32((void *)EMAC_TXM0 + hw_p->hw_addr,
1084 in_be32((void *)EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0);
1085 #ifdef INFO_4XX_ENET
1086 hw_p->stats.pkts_tx++;
1089 /*-----------------------------------------------------------------------+
1090 * poll unitl the packet is sent and then make sure it is OK
1091 *-----------------------------------------------------------------------*/
1092 time_start = get_timer (0);
1094 temp_txm0 = in_be32((void *)EMAC_TXM0 + hw_p->hw_addr);
1095 /* loop until either TINT turns on or 3 seconds elapse */
1096 if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) {
1097 /* transmit is done, so now check for errors
1098 * If there is an error, an interrupt should
1099 * happen when we return
1101 time_now = get_timer (0);
1102 if ((time_now - time_start) > 3000) {
1112 #if defined (CONFIG_440) || defined(CONFIG_405EX)
1114 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
1116 * Hack: On 440SP all enet irq sources are located on UIC1
1117 * Needs some cleanup. --sr
1119 #define UIC0MSR uic1msr
1120 #define UIC0SR uic1sr
1122 #define UIC0MSR uic0msr
1123 #define UIC0SR uic0sr
1126 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1127 defined(CONFIG_405EX)
1128 #define UICMSR_ETHX uic0msr
1129 #define UICSR_ETHX uic0sr
1131 #define UICMSR_ETHX uic1msr
1132 #define UICSR_ETHX uic1sr
1135 int enetInt (struct eth_device *dev)
1138 int rc = -1; /* default to not us */
1139 unsigned long mal_isr;
1140 unsigned long emac_isr = 0;
1141 unsigned long mal_rx_eob;
1142 unsigned long my_uic0msr, my_uic1msr;
1143 unsigned long my_uicmsr_ethx;
1145 #if defined(CONFIG_440GX)
1146 unsigned long my_uic2msr;
1148 EMAC_4XX_HW_PST hw_p;
1151 * Because the mal is generic, we need to get the current
1154 #if defined(CONFIG_NET_MULTI)
1155 dev = eth_get_dev();
1162 /* enter loop that stays in interrupt code until nothing to service */
1166 my_uic0msr = mfdcr (UIC0MSR);
1167 my_uic1msr = mfdcr (uic1msr);
1168 #if defined(CONFIG_440GX)
1169 my_uic2msr = mfdcr (uic2msr);
1171 my_uicmsr_ethx = mfdcr (UICMSR_ETHX);
1173 if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
1174 && !(my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))
1175 && !(my_uicmsr_ethx & (UIC_ETH0 | UIC_ETH1))) {
1179 #if defined (CONFIG_440GX)
1180 if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
1181 && !(my_uic2msr & (UIC_ETH2 | UIC_ETH3))) {
1186 /* get and clear controller status interrupts */
1187 /* look at Mal and EMAC interrupts */
1188 if ((my_uic0msr & (UIC_MRE | UIC_MTE))
1189 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
1190 /* we have a MAL interrupt */
1191 mal_isr = mfdcr (malesr);
1192 /* look for mal error */
1193 if (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) {
1194 mal_err (dev, mal_isr, my_uic1msr, MAL_UIC_DEF, MAL_UIC_ERR);
1200 /* port by port dispatch of emac interrupts */
1201 if (hw_p->devnum == 0) {
1202 if (UIC_ETH0 & my_uicmsr_ethx) { /* look for EMAC errors */
1203 emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr);
1204 if ((hw_p->emac_ier & emac_isr) != 0) {
1205 emac_err (dev, emac_isr);
1210 if ((hw_p->emac_ier & emac_isr)
1211 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
1212 mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
1213 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1214 mtdcr (UICSR_ETHX, UIC_ETH0); /* Clear */
1215 return (rc); /* we had errors so get out */
1219 #if !defined(CONFIG_440SP)
1220 if (hw_p->devnum == 1) {
1221 if (UIC_ETH1 & my_uicmsr_ethx) { /* look for EMAC errors */
1222 emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr);
1223 if ((hw_p->emac_ier & emac_isr) != 0) {
1224 emac_err (dev, emac_isr);
1229 if ((hw_p->emac_ier & emac_isr)
1230 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
1231 mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
1232 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1233 mtdcr (UICSR_ETHX, UIC_ETH1); /* Clear */
1234 return (rc); /* we had errors so get out */
1237 #if defined (CONFIG_440GX)
1238 if (hw_p->devnum == 2) {
1239 if (UIC_ETH2 & my_uic2msr) { /* look for EMAC errors */
1240 emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr);
1241 if ((hw_p->emac_ier & emac_isr) != 0) {
1242 emac_err (dev, emac_isr);
1247 if ((hw_p->emac_ier & emac_isr)
1248 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
1249 mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
1250 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1251 mtdcr (uic2sr, UIC_ETH2);
1252 return (rc); /* we had errors so get out */
1256 if (hw_p->devnum == 3) {
1257 if (UIC_ETH3 & my_uic2msr) { /* look for EMAC errors */
1258 emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr);
1259 if ((hw_p->emac_ier & emac_isr) != 0) {
1260 emac_err (dev, emac_isr);
1265 if ((hw_p->emac_ier & emac_isr)
1266 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
1267 mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
1268 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1269 mtdcr (uic2sr, UIC_ETH3);
1270 return (rc); /* we had errors so get out */
1273 #endif /* CONFIG_440GX */
1274 #endif /* !CONFIG_440SP */
1276 /* handle MAX TX EOB interrupt from a tx */
1277 if (my_uic0msr & UIC_MTE) {
1278 mal_rx_eob = mfdcr (maltxeobisr);
1279 mtdcr (maltxeobisr, mal_rx_eob);
1280 mtdcr (UIC0SR, UIC_MTE);
1282 /* handle MAL RX EOB interupt from a receive */
1283 /* check for EOB on valid channels */
1284 if (my_uic0msr & UIC_MRE) {
1285 mal_rx_eob = mfdcr (malrxeobisr);
1286 if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */
1288 mtdcr(malrxeobisr, mal_rx_eob); */
1289 enet_rcv (dev, emac_isr);
1290 /* indicate that we serviced an interrupt */
1296 mtdcr (UIC0SR, UIC_MRE); /* Clear */
1297 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1298 switch (hw_p->devnum) {
1300 mtdcr (UICSR_ETHX, UIC_ETH0);
1303 mtdcr (UICSR_ETHX, UIC_ETH1);
1305 #if defined (CONFIG_440GX)
1307 mtdcr (uic2sr, UIC_ETH2);
1310 mtdcr (uic2sr, UIC_ETH3);
1312 #endif /* CONFIG_440GX */
1321 #else /* CONFIG_440 */
1323 int enetInt (struct eth_device *dev)
1326 int rc = -1; /* default to not us */
1327 unsigned long mal_isr;
1328 unsigned long emac_isr = 0;
1329 unsigned long mal_rx_eob;
1330 unsigned long my_uicmsr;
1332 EMAC_4XX_HW_PST hw_p;
1335 * Because the mal is generic, we need to get the current
1338 #if defined(CONFIG_NET_MULTI)
1339 dev = eth_get_dev();
1346 /* enter loop that stays in interrupt code until nothing to service */
1350 my_uicmsr = mfdcr (uicmsr);
1352 if ((my_uicmsr & (MAL_UIC_DEF | EMAC_UIC_DEF)) == 0) { /* not for us */
1355 /* get and clear controller status interrupts */
1356 /* look at Mal and EMAC interrupts */
1357 if ((MAL_UIC_DEF & my_uicmsr) != 0) { /* we have a MAL interrupt */
1358 mal_isr = mfdcr (malesr);
1359 /* look for mal error */
1360 if ((my_uicmsr & MAL_UIC_ERR) != 0) {
1361 mal_err (dev, mal_isr, my_uicmsr, MAL_UIC_DEF, MAL_UIC_ERR);
1367 /* port by port dispatch of emac interrupts */
1369 if ((SEL_UIC_DEF(hw_p->devnum) & my_uicmsr) != 0) { /* look for EMAC errors */
1370 emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr);
1371 if ((hw_p->emac_ier & emac_isr) != 0) {
1372 emac_err (dev, emac_isr);
1377 if (((hw_p->emac_ier & emac_isr) != 0) || ((MAL_UIC_ERR & my_uicmsr) != 0)) {
1378 mtdcr (uicsr, MAL_UIC_DEF | SEL_UIC_DEF(hw_p->devnum)); /* Clear */
1379 return (rc); /* we had errors so get out */
1382 /* handle MAX TX EOB interrupt from a tx */
1383 if (my_uicmsr & UIC_MAL_TXEOB) {
1384 mal_rx_eob = mfdcr (maltxeobisr);
1385 mtdcr (maltxeobisr, mal_rx_eob);
1386 mtdcr (uicsr, UIC_MAL_TXEOB);
1388 /* handle MAL RX EOB interupt from a receive */
1389 /* check for EOB on valid channels */
1390 if (my_uicmsr & UIC_MAL_RXEOB)
1392 mal_rx_eob = mfdcr (malrxeobisr);
1393 if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */
1395 mtdcr(malrxeobisr, mal_rx_eob); */
1396 enet_rcv (dev, emac_isr);
1397 /* indicate that we serviced an interrupt */
1402 mtdcr (uicsr, MAL_UIC_DEF|EMAC_UIC_DEF|EMAC_UIC_DEF1); /* Clear */
1403 #if defined(CONFIG_405EZ)
1404 mtsdr (sdricintstat, SDR_ICRX_STAT | SDR_ICTX0_STAT | SDR_ICTX1_STAT);
1405 #endif /* defined(CONFIG_405EZ) */
1412 #endif /* CONFIG_440 */
1414 /*-----------------------------------------------------------------------------+
1416 *-----------------------------------------------------------------------------*/
1417 static void mal_err (struct eth_device *dev, unsigned long isr,
1418 unsigned long uic, unsigned long maldef,
1419 unsigned long mal_errr)
1421 EMAC_4XX_HW_PST hw_p = dev->priv;
1423 mtdcr (malesr, isr); /* clear interrupt */
1425 /* clear DE interrupt */
1426 mtdcr (maltxdeir, 0xC0000000);
1427 mtdcr (malrxdeir, 0x80000000);
1429 #ifdef INFO_4XX_ENET
1430 printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n", isr, uic, maldef, mal_errr);
1433 eth_init (hw_p->bis); /* start again... */
1436 /*-----------------------------------------------------------------------------+
1437 * EMAC Error Routine
1438 *-----------------------------------------------------------------------------*/
1439 static void emac_err (struct eth_device *dev, unsigned long isr)
1441 EMAC_4XX_HW_PST hw_p = dev->priv;
1443 printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr);
1444 out_be32((void *)EMAC_ISR + hw_p->hw_addr, isr);
1447 /*-----------------------------------------------------------------------------+
1448 * enet_rcv() handles the ethernet receive data
1449 *-----------------------------------------------------------------------------*/
1450 static void enet_rcv (struct eth_device *dev, unsigned long malisr)
1452 struct enet_frame *ef_ptr;
1453 unsigned long data_len;
1454 unsigned long rx_eob_isr;
1455 EMAC_4XX_HW_PST hw_p = dev->priv;
1461 rx_eob_isr = mfdcr (malrxeobisr);
1462 if ((0x80000000 >> hw_p->devnum) & rx_eob_isr) {
1464 mtdcr (malrxeobisr, rx_eob_isr);
1467 while (1) { /* do all */
1470 if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl)
1471 || (loop_count >= NUM_RX_BUFF))
1476 data_len = (unsigned long) hw_p->rx[i].data_len; /* Get len */
1478 if (data_len > ENET_MAX_MTU) /* Check len */
1481 if (EMAC_RX_ERRORS & hw_p->rx[i].ctrl) { /* Check Errors */
1483 hw_p->stats.rx_err_log[hw_p->
1486 hw_p->rx_err_index++;
1487 if (hw_p->rx_err_index ==
1489 hw_p->rx_err_index =
1492 } /* data_len < max mtu */
1494 if (!data_len) { /* no data */
1495 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY; /* Free Recv Buffer */
1497 hw_p->stats.data_len_err++; /* Error at Rx */
1502 /* Check if user has already eaten buffer */
1503 /* if not => ERROR */
1504 else if (hw_p->rx_ready[hw_p->rx_i_index] != -1) {
1505 if (hw_p->is_receiving)
1506 printf ("ERROR : Receive buffers are full!\n");
1509 hw_p->stats.rx_frames++;
1510 hw_p->stats.rx += data_len;
1511 ef_ptr = (struct enet_frame *) hw_p->rx[i].
1513 #ifdef INFO_4XX_ENET
1514 hw_p->stats.pkts_rx++;
1519 hw_p->rx_ready[hw_p->rx_i_index] = i;
1521 if (NUM_RX_BUFF == hw_p->rx_i_index)
1522 hw_p->rx_i_index = 0;
1525 if (NUM_RX_BUFF == hw_p->rx_slot)
1529 * free receive buffer only when
1530 * buffer has been handled (eth_rx)
1531 rx[i].ctrl |= MAL_RX_CTRL_EMPTY;
1535 } /* if EMACK_RXCHL */
1539 static int ppc_4xx_eth_rx (struct eth_device *dev)
1544 EMAC_4XX_HW_PST hw_p = dev->priv;
1546 hw_p->is_receiving = 1; /* tell driver */
1550 * use ring buffer and
1551 * get index from rx buffer desciptor queue
1553 user_index = hw_p->rx_ready[hw_p->rx_u_index];
1554 if (user_index == -1) {
1556 break; /* nothing received - leave for() loop */
1560 mtmsr (msr & ~(MSR_EE));
1562 length = hw_p->rx[user_index].data_len;
1564 /* Pass the packet up to the protocol layers. */
1565 /* NetReceive(NetRxPackets[rxIdx], length - 4); */
1566 /* NetReceive(NetRxPackets[i], length); */
1567 invalidate_dcache_range((u32)hw_p->rx[user_index].data_ptr,
1568 (u32)hw_p->rx[user_index].data_ptr +
1570 NetReceive (NetRxPackets[user_index], length - 4);
1571 /* Free Recv Buffer */
1572 hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY;
1573 /* Free rx buffer descriptor queue */
1574 hw_p->rx_ready[hw_p->rx_u_index] = -1;
1576 if (NUM_RX_BUFF == hw_p->rx_u_index)
1577 hw_p->rx_u_index = 0;
1579 #ifdef INFO_4XX_ENET
1580 hw_p->stats.pkts_handled++;
1583 mtmsr (msr); /* Enable IRQ's */
1586 hw_p->is_receiving = 0; /* tell driver */
1591 int ppc_4xx_eth_initialize (bd_t * bis)
1593 static int virgin = 0;
1594 struct eth_device *dev;
1596 EMAC_4XX_HW_PST hw = NULL;
1597 u8 ethaddr[4 + CONFIG_EMAC_NR_START][6];
1600 #if defined(CONFIG_440GX)
1603 mfsdr (sdr_pfc1, pfc1);
1604 pfc1 &= ~(0x01e00000);
1606 mtsdr (sdr_pfc1, pfc1);
1609 /* first clear all mac-addresses */
1610 for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++)
1611 memcpy(ethaddr[eth_num], "\0\0\0\0\0\0", 6);
1613 for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
1615 default: /* fall through */
1617 memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
1618 bis->bi_enetaddr, 6);
1619 hw_addr[eth_num] = 0x0;
1621 #ifdef CONFIG_HAS_ETH1
1623 memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
1624 bis->bi_enet1addr, 6);
1625 hw_addr[eth_num] = 0x100;
1628 #ifdef CONFIG_HAS_ETH2
1630 memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
1631 bis->bi_enet2addr, 6);
1632 hw_addr[eth_num] = 0x400;
1635 #ifdef CONFIG_HAS_ETH3
1637 memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
1638 bis->bi_enet3addr, 6);
1639 hw_addr[eth_num] = 0x600;
1645 /* set phy num and mode */
1646 bis->bi_phynum[0] = CONFIG_PHY_ADDR;
1647 bis->bi_phymode[0] = 0;
1649 #if defined(CONFIG_PHY1_ADDR)
1650 bis->bi_phynum[1] = CONFIG_PHY1_ADDR;
1651 bis->bi_phymode[1] = 0;
1653 #if defined(CONFIG_440GX)
1654 bis->bi_phynum[2] = CONFIG_PHY2_ADDR;
1655 bis->bi_phynum[3] = CONFIG_PHY3_ADDR;
1656 bis->bi_phymode[2] = 2;
1657 bis->bi_phymode[3] = 2;
1660 #if defined(CONFIG_440GX) || \
1661 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1662 defined(CONFIG_405EX)
1663 ppc_4xx_eth_setup_bridge(0, bis);
1666 for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
1668 * See if we can actually bring up the interface,
1669 * otherwise, skip it
1671 if (memcmp (ethaddr[eth_num], "\0\0\0\0\0\0", 6) == 0) {
1672 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
1676 /* Allocate device structure */
1677 dev = (struct eth_device *) malloc (sizeof (*dev));
1679 printf ("ppc_4xx_eth_initialize: "
1680 "Cannot allocate eth_device %d\n", eth_num);
1683 memset(dev, 0, sizeof(*dev));
1685 /* Allocate our private use data */
1686 hw = (EMAC_4XX_HW_PST) malloc (sizeof (*hw));
1688 printf ("ppc_4xx_eth_initialize: "
1689 "Cannot allocate private hw data for eth_device %d",
1694 memset(hw, 0, sizeof(*hw));
1696 hw->hw_addr = hw_addr[eth_num];
1697 memcpy (dev->enetaddr, ethaddr[eth_num], 6);
1698 hw->devnum = eth_num;
1699 hw->print_speed = 1;
1701 sprintf (dev->name, "ppc_4xx_eth%d", eth_num - CONFIG_EMAC_NR_START);
1702 dev->priv = (void *) hw;
1703 dev->init = ppc_4xx_eth_init;
1704 dev->halt = ppc_4xx_eth_halt;
1705 dev->send = ppc_4xx_eth_send;
1706 dev->recv = ppc_4xx_eth_rx;
1709 /* set the MAL IER ??? names may change with new spec ??? */
1710 #if defined(CONFIG_440SPE) || \
1711 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1712 defined(CONFIG_405EX)
1714 MAL_IER_PT | MAL_IER_PRE | MAL_IER_PWE |
1715 MAL_IER_DE | MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE ;
1718 MAL_IER_DE | MAL_IER_NE | MAL_IER_TE |
1719 MAL_IER_OPBE | MAL_IER_PLBE;
1721 mtdcr (malesr, 0xffffffff); /* clear pending interrupts */
1722 mtdcr (maltxdeir, 0xffffffff); /* clear pending interrupts */
1723 mtdcr (malrxdeir, 0xffffffff); /* clear pending interrupts */
1724 mtdcr (malier, mal_ier);
1726 /* install MAL interrupt handler */
1727 irq_install_handler (VECNUM_MS,
1728 (interrupt_handler_t *) enetInt,
1730 irq_install_handler (VECNUM_MTE,
1731 (interrupt_handler_t *) enetInt,
1733 irq_install_handler (VECNUM_MRE,
1734 (interrupt_handler_t *) enetInt,
1736 irq_install_handler (VECNUM_TXDE,
1737 (interrupt_handler_t *) enetInt,
1739 irq_install_handler (VECNUM_RXDE,
1740 (interrupt_handler_t *) enetInt,
1745 #if defined(CONFIG_NET_MULTI)
1751 #if defined(CONFIG_NET_MULTI)
1752 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
1753 miiphy_register (dev->name,
1754 emac4xx_miiphy_read, emac4xx_miiphy_write);
1757 } /* end for each supported device */
1762 #if !defined(CONFIG_NET_MULTI)
1763 void eth_halt (void) {
1765 ppc_4xx_eth_halt(emac0_dev);
1771 int eth_init (bd_t *bis)
1773 ppc_4xx_eth_initialize(bis);
1775 return ppc_4xx_eth_init(emac0_dev, bis);
1777 printf("ERROR: ethaddr not set!\n");
1782 int eth_send(volatile void *packet, int length)
1784 return (ppc_4xx_eth_send(emac0_dev, packet, length));
1789 return (ppc_4xx_eth_rx(emac0_dev));
1792 int emac4xx_miiphy_initialize (bd_t * bis)
1794 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
1795 miiphy_register ("ppc_4xx_eth0",
1796 emac4xx_miiphy_read, emac4xx_miiphy_write);
1801 #endif /* !defined(CONFIG_NET_MULTI) */