1 /*-----------------------------------------------------------------------------+
3 * This source code has been made available to you by IBM on an AS-IS
4 * basis. Anyone receiving this source is licensed under IBM
5 * copyrights to use it in any way he or she deems fit, including
6 * copying it, modifying it, compiling it, and redistributing it either
7 * with or without modifications. No license under IBM patents or
8 * patent applications is to be implied by the copyright license.
10 * Any user of this software should understand that IBM cannot provide
11 * technical support for this software and will not be responsible for
12 * any consequences resulting from the use of this software.
14 * Any person who transfers this source code or any derivative work
15 * must include the IBM copyright notice, this paragraph, and the
16 * preceding two paragraphs in the transferred software.
18 * COPYRIGHT I B M CORPORATION 1995
19 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 *-----------------------------------------------------------------------------*/
21 /*----------------------------------------------------------------------------+
23 * File Name: 405gp_pci.c
25 * Function: Initialization code for the 405GP PCI Configuration regs.
31 * Date Description of Change BY
32 * --------- --------------------- ---
33 * 09-Sep-98 Created MCG
34 * 02-Nov-98 Removed External arbiter selected message JWB
35 * 27-Nov-98 Zero out PTMBAR2 and disable in PTM2MS JWB
36 * 04-Jan-99 Zero out other unused PMM and PTM regs. Change bus scan MCG
37 * from (0 to n) to (1 to n).
38 * 17-May-99 Port to Walnut JWB
39 * 17-Jun-99 Updated for VGA support JWB
40 * 21-Jun-99 Updated to allow SRAM region to be a target from PCI bus JWB
41 * 19-Jul-99 Updated for 405GP pass 1 errata #26 (Low PCI subsequent MCG
42 * target latency timer values are not supported).
43 * Should be fixed in pass 2.
44 * 09-Sep-99 Removed use of PTM2 since the SRAM region no longer needs JWB
45 * to be a PCI target. Zero out PTMBAR2 and disable in PTM2MS.
46 * 10-Dec-99 Updated PCI_Write_CFG_Reg for pass2 errata #6 JWB
47 * 11-Jan-00 Ensure PMMxMAs disabled before setting PMMxLAs. This is not
48 * really required after a reset since PMMxMAs are already
49 * disabled but is a good practice nonetheless. JWB
50 * 12-Jun-01 stefan.roese@esd-electronics.com
51 * - PCI host/adapter handling reworked
52 * 09-Jul-01 stefan.roese@esd-electronics.com
53 * - PCI host now configures from device 0 (not 1) to max_dev,
54 * (host configures itself)
55 * - On CPCI-405 pci base address and size is generated from
56 * SDRAM and FLASH size (CFG regs not used anymore)
57 * - Some minor changes for CPCI-405-A (adapter version)
58 * 14-Sep-01 stefan.roese@esd-electronics.com
59 * - CONFIG_PCI_SCAN_SHOW added to print pci devices upon startup
60 * 28-Sep-01 stefan.roese@esd-electronics.com
61 * - Changed pci master configuration for linux compatibility
62 * (no need for bios_fixup() anymore)
63 * 26-Feb-02 stefan.roese@esd-electronics.com
64 * - Bug fixed in pci configuration (Andrew May)
65 * - Removed pci class code init for CPCI405 board
66 * 15-May-02 stefan.roese@esd-electronics.com
67 * - New vga device handling
68 * 29-May-02 stefan.roese@esd-electronics.com
69 * - PCI class code init added (if defined)
70 *----------------------------------------------------------------------------*/
74 #if !defined(CONFIG_440)
75 #include <asm/4xx_pci.h>
77 #include <asm/processor.h>
82 DECLARE_GLOBAL_DATA_PTR;
85 * Board-specific pci initialization
86 * Platform code can reimplement pci_pre_init() if needed
88 int __pci_pre_init(struct pci_controller *hose)
92 int pci_pre_init(struct pci_controller *hose) __attribute__((weak, alias("__pci_pre_init")));
94 #if defined(CONFIG_405GP) || defined(CONFIG_405EP)
96 #if defined(CONFIG_PMC405)
97 ushort pmc405_pci_subsys_deviceid(void);
102 int __is_pci_host(struct pci_controller *hose)
104 #if defined(CONFIG_405GP)
105 if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
107 #elif defined (CONFIG_405EP)
108 if (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN)
113 int is_pci_host(struct pci_controller *hose) __attribute__((weak, alias("__is_pci_host")));
115 /*-----------------------------------------------------------------------------+
116 * pci_init. Initializes the 405GP PCI Configuration regs.
117 *-----------------------------------------------------------------------------*/
118 void pci_405gp_init(struct pci_controller *hose)
123 unsigned short temp_short;
124 unsigned long ptmpcila[2] = {CONFIG_SYS_PCI_PTM1PCI, CONFIG_SYS_PCI_PTM2PCI};
125 #if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405)
126 char *ptmla_str, *ptmms_str;
128 unsigned long ptmla[2] = {CONFIG_SYS_PCI_PTM1LA, CONFIG_SYS_PCI_PTM2LA};
129 unsigned long ptmms[2] = {CONFIG_SYS_PCI_PTM1MS, CONFIG_SYS_PCI_PTM2MS};
130 #if defined(CONFIG_PIP405) || defined (CONFIG_MIP405)
131 unsigned long pmmla[3] = {0x80000000, 0xA0000000, 0};
132 unsigned long pmmma[3] = {0xE0000001, 0xE0000001, 0};
133 unsigned long pmmpcila[3] = {0x80000000, 0x00000000, 0};
134 unsigned long pmmpciha[3] = {0x00000000, 0x00000000, 0};
136 unsigned long pmmla[3] = {0x80000000, 0,0};
137 unsigned long pmmma[3] = {0xC0000001, 0,0};
138 unsigned long pmmpcila[3] = {0x80000000, 0,0};
139 unsigned long pmmpciha[3] = {0x00000000, 0,0};
141 #ifdef CONFIG_PCI_PNP
142 #if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
147 #if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405)
148 ptmla_str = getenv("ptm1la");
149 ptmms_str = getenv("ptm1ms");
150 if(NULL != ptmla_str && NULL != ptmms_str ) {
151 ptmla[0] = simple_strtoul (ptmla_str, NULL, 16);
152 ptmms[0] = simple_strtoul (ptmms_str, NULL, 16);
155 ptmla_str = getenv("ptm2la");
156 ptmms_str = getenv("ptm2ms");
157 if(NULL != ptmla_str && NULL != ptmms_str ) {
158 ptmla[1] = simple_strtoul (ptmla_str, NULL, 16);
159 ptmms[1] = simple_strtoul (ptmms_str, NULL, 16);
166 hose->first_busno = 0;
167 hose->last_busno = 0xff;
169 /* ISA/PCI I/O space */
170 pci_set_region(hose->regions + reg_num++,
177 pci_set_region(hose->regions + reg_num++,
189 if (!i) hose->pci_fb = hose->regions + reg_num;
191 pci_set_region(hose->regions + reg_num++,
192 ptmpcila[i], ptmla[i],
193 ~(ptmms[i] & 0xfffff000) + 1,
195 PCI_REGION_SYS_MEMORY);
198 /* PCI memory spaces */
202 pci_set_region(hose->regions + reg_num++,
203 pmmpcila[i], pmmla[i],
204 ~(pmmma[i] & 0xfffff000) + 1,
208 hose->region_count = reg_num;
210 pci_setup_indirect(hose,
215 pciauto_region_init(hose->pci_fb);
217 /* Let board change/modify hose & do initial checks */
218 if (pci_pre_init (hose) == 0) {
219 printf("PCI: Board-specific initialization failed.\n");
220 printf("PCI: Configuration aborted.\n");
224 pci_register_hose(hose);
226 /*--------------------------------------------------------------------------+
227 * 405GP PCI Master configuration.
228 * Map one 512 MB range of PLB/processor addresses to PCI memory space.
229 * PLB address 0x80000000-0xBFFFFFFF ==> PCI address 0x80000000-0xBFFFFFFF
230 * Use byte reversed out routines to handle endianess.
231 *--------------------------------------------------------------------------*/
232 out32r(PMM0MA, (pmmma[0]&~0x1)); /* disable, configure PMMxLA, PMMxPCILA first */
233 out32r(PMM0LA, pmmla[0]);
234 out32r(PMM0PCILA, pmmpcila[0]);
235 out32r(PMM0PCIHA, pmmpciha[0]);
236 out32r(PMM0MA, pmmma[0]);
238 /*--------------------------------------------------------------------------+
239 * PMM1 is not used. Initialize them to zero.
240 *--------------------------------------------------------------------------*/
241 out32r(PMM1MA, (pmmma[1]&~0x1));
242 out32r(PMM1LA, pmmla[1]);
243 out32r(PMM1PCILA, pmmpcila[1]);
244 out32r(PMM1PCIHA, pmmpciha[1]);
245 out32r(PMM1MA, pmmma[1]);
247 /*--------------------------------------------------------------------------+
248 * PMM2 is not used. Initialize them to zero.
249 *--------------------------------------------------------------------------*/
250 out32r(PMM2MA, (pmmma[2]&~0x1));
251 out32r(PMM2LA, pmmla[2]);
252 out32r(PMM2PCILA, pmmpcila[2]);
253 out32r(PMM2PCIHA, pmmpciha[2]);
254 out32r(PMM2MA, pmmma[2]);
256 /*--------------------------------------------------------------------------+
257 * 405GP PCI Target configuration. (PTM1)
258 * Note: PTM1MS is hardwire enabled but we set the enable bit anyway.
259 *--------------------------------------------------------------------------*/
260 out32r(PTM1LA, ptmla[0]); /* insert address */
261 out32r(PTM1MS, ptmms[0]); /* insert size, enable bit is 1 */
262 pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_1, ptmpcila[0]);
264 /*--------------------------------------------------------------------------+
265 * 405GP PCI Target configuration. (PTM2)
266 *--------------------------------------------------------------------------*/
267 out32r(PTM2LA, ptmla[1]); /* insert address */
268 pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, ptmpcila[1]);
272 out32r(PTM2MS, 0x00000001); /* set enable bit */
273 pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, 0x00000000);
274 out32r(PTM2MS, 0x00000000); /* disable */
278 out32r(PTM2MS, ptmms[1]); /* insert size, enable bit is 1 */
282 * Insert Subsystem Vendor and Device ID
284 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_VENDOR_ID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
285 #ifdef CONFIG_CPCI405
286 if (is_pci_host(hose))
287 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
289 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID2);
291 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
297 #ifdef CONFIG_SYS_PCI_CLASSCODE
298 pci_write_config_word(PCIDEVID_405GP, PCI_CLASS_SUB_CODE, CONFIG_SYS_PCI_CLASSCODE);
299 #endif /* CONFIG_SYS_PCI_CLASSCODE */
301 /*--------------------------------------------------------------------------+
302 * If PCI speed = 66MHz, set 66MHz capable bit.
303 *--------------------------------------------------------------------------*/
304 if (bd->bi_pci_busfreq >= 66000000) {
305 pci_read_config_word(PCIDEVID_405GP, PCI_STATUS, &temp_short);
306 pci_write_config_word(PCIDEVID_405GP,PCI_STATUS,(temp_short|PCI_STATUS_66MHZ));
309 #if (CONFIG_PCI_HOST != PCI_HOST_ADAPTER)
310 #if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
311 if (is_pci_host(hose) ||
312 (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0)))
315 /*--------------------------------------------------------------------------+
316 * Write the 405GP PCI Configuration regs.
317 * Enable 405GP to be a master on the PCI bus (PMM).
318 * Enable 405GP to act as a PCI memory target (PTM).
319 *--------------------------------------------------------------------------*/
320 pci_read_config_word(PCIDEVID_405GP, PCI_COMMAND, &temp_short);
321 pci_write_config_word(PCIDEVID_405GP, PCI_COMMAND, temp_short |
322 PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
326 #if defined(CONFIG_405EP) /* on ppc405ep vendor id is not set */
327 pci_write_config_word(PCIDEVID_405GP, PCI_VENDOR_ID, 0x1014); /* IBM */
331 * Set HCE bit (Host Configuration Enabled)
333 pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &temp_short);
334 pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (temp_short | 0x0001));
336 #ifdef CONFIG_PCI_PNP
337 /*--------------------------------------------------------------------------+
338 * Scan the PCI bus and configure devices found.
339 *--------------------------------------------------------------------------*/
340 #if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
341 if (is_pci_host(hose) ||
342 (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0)))
345 #ifdef CONFIG_PCI_SCAN_SHOW
346 printf("PCI: Bus Dev VenId DevId Class Int\n");
348 hose->last_busno = pci_hose_scan(hose);
350 #endif /* CONFIG_PCI_PNP */
355 * drivers/pci/pci.c skips every host bridge but the 405GP since it could
356 * be set as an Adapter.
358 * I (Andrew May) don't know what we should do here, but I don't want
359 * the auto setup of a PCI device disabling what is done pci_405gp_init
360 * as has happened before.
362 void pci_405gp_setup_bridge(struct pci_controller *hose, pci_dev_t dev,
363 struct pci_config_table *entry)
366 printf("405gp_setup_bridge\n");
374 void pci_405gp_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
376 unsigned char int_line = 0xff;
379 * Write pci interrupt line register (cpci405 specific)
381 switch (PCI_DEV(dev) & 0x03)
397 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
400 void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev,
401 struct pci_config_table *entry)
403 unsigned int cmdstat = 0;
405 pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
407 /* always enable io space on vga boards */
408 pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
409 cmdstat |= PCI_COMMAND_IO;
410 pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
413 #if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405)) && !(defined (CONFIG_SC3))
416 *As is these functs get called out of flash Not a horrible
417 *thing, but something to keep in mind. (no statics?)
419 static struct pci_config_table pci_405gp_config_table[] = {
420 /*if VendID is 0 it terminates the table search (ie Walnut)*/
421 #ifdef CONFIG_SYS_PCI_SUBSYS_VENDORID
422 {CONFIG_SYS_PCI_SUBSYS_VENDORID, PCI_ANY_ID, PCI_CLASS_BRIDGE_HOST,
423 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_bridge},
425 {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA,
426 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga},
428 {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NOT_DEFINED_VGA,
429 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga},
434 static struct pci_controller hose = {
435 fixup_irq: pci_405gp_fixup_irq,
436 config_table: pci_405gp_config_table,
439 void pci_init_board(void)
441 /*we want the ptrs to RAM not flash (ie don't use init list)*/
442 hose.fixup_irq = pci_405gp_fixup_irq;
443 hose.config_table = pci_405gp_config_table;
444 pci_405gp_init(&hose);
449 #endif /* CONFIG_405GP */
451 /*-----------------------------------------------------------------------------+
453 *-----------------------------------------------------------------------------*/
454 #if defined(CONFIG_440)
456 static struct pci_controller ppc440_hose = {0};
459 int pci_440_init (struct pci_controller *hose)
463 #ifndef CONFIG_DISABLE_PISE_TEST
464 /*--------------------------------------------------------------------------+
465 * The PCI initialization sequence enable bit must be set ... if not abort
466 * pci setup since updating the bit requires chip reset.
467 *--------------------------------------------------------------------------*/
468 #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
471 mfsdr(sdr_sdstp1,strap);
472 if ((strap & SDR0_SDSTP1_PISE_MASK) == 0) {
473 printf("PCI: SDR0_STRP1[PISE] not set.\n");
474 printf("PCI: Configuration aborted.\n");
477 #elif defined(CONFIG_440GP)
480 strap = mfdcr(cpc0_strp1);
481 if ((strap & CPC0_STRP1_PISE_MASK) == 0) {
482 printf("PCI: CPC0_STRP1[PISE] not set.\n");
483 printf("PCI: Configuration aborted.\n");
487 #endif /* CONFIG_DISABLE_PISE_TEST */
489 /*--------------------------------------------------------------------------+
490 * PCI controller init
491 *--------------------------------------------------------------------------*/
492 hose->first_busno = 0;
493 hose->last_busno = 0;
496 pci_set_region(hose->regions + reg_num++,
502 /* PCI memory space */
503 pci_set_region(hose->regions + reg_num++,
504 CONFIG_SYS_PCI_TARGBASE,
505 CONFIG_SYS_PCI_MEMBASE,
506 #ifdef CONFIG_SYS_PCI_MEMSIZE
507 CONFIG_SYS_PCI_MEMSIZE,
513 #if defined(CONFIG_PCI_SYS_MEM_BUS) && defined(CONFIG_PCI_SYS_MEM_PHYS) && \
514 defined(CONFIG_PCI_SYS_MEM_SIZE)
515 /* System memory space */
516 pci_set_region(hose->regions + reg_num++,
517 CONFIG_PCI_SYS_MEM_BUS,
518 CONFIG_PCI_SYS_MEM_PHYS,
519 CONFIG_PCI_SYS_MEM_SIZE,
520 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY );
523 hose->region_count = reg_num;
525 pci_setup_indirect(hose, PCIX0_CFGADR, PCIX0_CFGDATA);
527 /* Let board change/modify hose & do initial checks */
528 if (pci_pre_init (hose) == 0) {
529 printf("PCI: Board-specific initialization failed.\n");
530 printf("PCI: Configuration aborted.\n");
534 pci_register_hose( hose );
536 /*--------------------------------------------------------------------------+
538 *--------------------------------------------------------------------------*/
539 #if defined(CONFIG_SYS_PCI_TARGET_INIT)
540 pci_target_init(hose); /* Let board setup pci target */
542 out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
543 out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_ID );
544 out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */
547 #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
548 defined(CONFIG_460EX) || defined(CONFIG_460GT)
549 out32r( PCIX0_BRDGOPT1, 0x04000060 ); /* PLB Rq pri highest */
550 out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1 */
551 #elif defined(PCIX0_BRDGOPT1)
552 out32r( PCIX0_BRDGOPT1, 0x10000060 ); /* PLB Rq pri highest */
553 out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 1 ); /* Enable host config */
556 /*--------------------------------------------------------------------------+
557 * PCI master init: default is one 256MB region for PCI memory:
558 * 0x3_00000000 - 0x3_0FFFFFFF ==> CONFIG_SYS_PCI_MEMBASE
559 *--------------------------------------------------------------------------*/
560 #if defined(CONFIG_SYS_PCI_MASTER_INIT)
561 pci_master_init(hose); /* Let board setup pci master */
563 out32r( PCIX0_POM0SA, 0 ); /* disable */
564 out32r( PCIX0_POM1SA, 0 ); /* disable */
565 out32r( PCIX0_POM2SA, 0 ); /* disable */
566 #if defined(CONFIG_440SPE)
567 out32r( PCIX0_POM0LAL, 0x10000000 );
568 out32r( PCIX0_POM0LAH, 0x0000000c );
569 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
570 out32r( PCIX0_POM0LAL, 0x20000000 );
571 out32r( PCIX0_POM0LAH, 0x0000000c );
573 out32r( PCIX0_POM0LAL, 0x00000000 );
574 out32r( PCIX0_POM0LAH, 0x00000003 );
576 out32r( PCIX0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE );
577 out32r( PCIX0_POM0PCIAH, 0x00000000 );
578 out32r( PCIX0_POM0SA, 0xf0000001 ); /* 256MB, enabled */
579 out32r( PCIX0_STS, in32r( PCIX0_STS ) & ~0x0000fff8 );
582 /*--------------------------------------------------------------------------+
583 * PCI host configuration -- we don't make any assumptions here ... the
584 * _board_must_indicate_ what to do -- there's just too many runtime
585 * scenarios in environments like cPCI, PPMC, etc. to make a determination
586 * based on hard-coded values or state of arbiter enable.
587 *--------------------------------------------------------------------------*/
588 if (is_pci_host(hose)) {
589 #ifdef CONFIG_PCI_SCAN_SHOW
590 printf("PCI: Bus Dev VenId DevId Class Int\n");
592 #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \
593 !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
594 out16r( PCIX0_CMD, in16r( PCIX0_CMD ) | PCI_COMMAND_MASTER);
596 hose->last_busno = pci_hose_scan(hose);
598 return hose->last_busno;
601 void pci_init_board(void)
605 busno = pci_440_init (&ppc440_hose);
606 #if (defined(CONFIG_440SPE) || \
607 defined(CONFIG_460EX) || defined(CONFIG_460GT)) && \
608 !defined(CONFIG_PCI_DISABLE_PCIE)
609 pcie_setup_hoses(busno + 1);
613 #endif /* CONFIG_440 */
615 #if defined(CONFIG_405EX)
616 void pci_init_board(void)
618 #ifdef CONFIG_PCI_SCAN_SHOW
619 printf("PCI: Bus Dev VenId DevId Class Int\n");
623 #endif /* CONFIG_405EX */
625 #endif /* CONFIG_PCI */