2 * (C) Copyright 2006 - 2008
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Copyright (c) 2005 Cisco Systems. All rights reserved.
6 * Roland Dreier <rolandd@cisco.com>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 /* define DEBUG for debugging output (obviously ;-)) */
31 #include <asm/processor.h>
32 #include <asm-ppc/io.h>
34 #if (defined(CONFIG_440SPE) || defined(CONFIG_405EX) || \
35 defined(CONFIG_460EX) || defined(CONFIG_460GT)) && \
36 defined(CONFIG_PCI) && !defined(CONFIG_PCI_DISABLE_PCIE)
38 #include <asm/4xx_pcie.h>
42 PTYPE_LEGACY_ENDPOINT = 0x1,
43 PTYPE_ROOT_PORT = 0x4,
50 static int validate_endpoint(struct pci_controller *hose)
52 if (hose->cfg_data == (u8 *)CONFIG_SYS_PCIE0_CFGBASE)
53 return (is_end_point(0));
54 else if (hose->cfg_data == (u8 *)CONFIG_SYS_PCIE1_CFGBASE)
55 return (is_end_point(1));
56 #if CONFIG_SYS_PCIE_NR_PORTS > 2
57 else if (hose->cfg_data == (u8 *)CONFIG_SYS_PCIE2_CFGBASE)
58 return (is_end_point(2));
64 static u8* pcie_get_base(struct pci_controller *hose, unsigned int devfn)
66 u8 *base = (u8*)hose->cfg_data;
68 /* use local configuration space for the first bus */
69 if (PCI_BUS(devfn) == 0) {
70 if (hose->cfg_data == (u8*)CONFIG_SYS_PCIE0_CFGBASE)
71 base = (u8*)CONFIG_SYS_PCIE0_XCFGBASE;
72 if (hose->cfg_data == (u8*)CONFIG_SYS_PCIE1_CFGBASE)
73 base = (u8*)CONFIG_SYS_PCIE1_XCFGBASE;
74 #if CONFIG_SYS_PCIE_NR_PORTS > 2
75 if (hose->cfg_data == (u8*)CONFIG_SYS_PCIE2_CFGBASE)
76 base = (u8*)CONFIG_SYS_PCIE2_XCFGBASE;
83 static void pcie_dmer_disable(void)
85 mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE),
86 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) | GPL_DMER_MASK_DISA);
87 mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE),
88 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) | GPL_DMER_MASK_DISA);
89 #if CONFIG_SYS_PCIE_NR_PORTS > 2
90 mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE),
91 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) | GPL_DMER_MASK_DISA);
95 static void pcie_dmer_enable(void)
97 mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE0_BASE),
98 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) & ~GPL_DMER_MASK_DISA);
99 mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE1_BASE),
100 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) & ~GPL_DMER_MASK_DISA);
101 #if CONFIG_SYS_PCIE_NR_PORTS > 2
102 mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE2_BASE),
103 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) & ~GPL_DMER_MASK_DISA);
107 static int pcie_read_config(struct pci_controller *hose, unsigned int devfn,
108 int offset, int len, u32 *val) {
113 if (validate_endpoint(hose))
114 return 0; /* No upstream config access */
117 * Bus numbers are relative to hose->first_busno
119 devfn -= PCI_BDF(hose->first_busno, 0, 0);
122 * NOTICE: configuration space ranges are currenlty mapped only for
123 * the first 16 buses, so such limit must be imposed. In case more
124 * buses are required the TLB settings in board/amcc/<board>/init.S
125 * need to be altered accordingly (one bus takes 1 MB of memory space).
127 if (PCI_BUS(devfn) >= 16)
131 * Only single device/single function is supported for the primary and
132 * secondary buses of the 440SPe host bridge.
134 if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) &&
135 ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1)))
138 address = pcie_get_base(hose, devfn);
139 offset += devfn << 4;
142 * Reading from configuration space of non-existing device can
143 * generate transaction errors. For the read duration we suppress
144 * assertion of machine check exceptions to avoid those.
146 pcie_dmer_disable ();
148 debug("%s: cfg_data=%08x offset=%08x\n", __func__, hose->cfg_data, offset);
151 *val = in_8(hose->cfg_data + offset);
154 *val = in_le16((u16 *)(hose->cfg_data + offset));
157 *val = in_le32((u32*)(hose->cfg_data + offset));
166 static int pcie_write_config(struct pci_controller *hose, unsigned int devfn,
167 int offset, int len, u32 val) {
171 if (validate_endpoint(hose))
172 return 0; /* No upstream config access */
175 * Bus numbers are relative to hose->first_busno
177 devfn -= PCI_BDF(hose->first_busno, 0, 0);
180 * Same constraints as in pcie_read_config().
182 if (PCI_BUS(devfn) >= 16)
185 if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) &&
186 ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1)))
189 address = pcie_get_base(hose, devfn);
190 offset += devfn << 4;
193 * Suppress MCK exceptions, similar to pcie_read_config()
195 pcie_dmer_disable ();
199 out_8(hose->cfg_data + offset, val);
202 out_le16((u16 *)(hose->cfg_data + offset), val);
205 out_le32((u32 *)(hose->cfg_data + offset), val);
214 int pcie_read_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 *val)
219 rv = pcie_read_config(hose, dev, offset, 1, &v);
224 int pcie_read_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 *val)
229 rv = pcie_read_config(hose, dev, offset, 2, &v);
234 int pcie_read_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 *val)
239 rv = pcie_read_config(hose, dev, offset, 3, &v);
244 int pcie_write_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 val)
246 return pcie_write_config(hose,(u32)dev,offset,1,val);
249 int pcie_write_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 val)
251 return pcie_write_config(hose,(u32)dev,offset,2,(u32 )val);
254 int pcie_write_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 val)
256 return pcie_write_config(hose,(u32)dev,offset,3,(u32 )val);
259 #if defined(CONFIG_440SPE)
260 static void ppc4xx_setup_utl(u32 port) {
262 volatile void *utl_base = NULL;
269 mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x0000000c);
270 mtdcr(DCRN_PEGPL_REGBAL(PCIE0), 0x20000000);
271 mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001);
272 mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0x68782800);
276 mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x0000000c);
277 mtdcr(DCRN_PEGPL_REGBAL(PCIE1), 0x20001000);
278 mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001);
279 mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0x68782800);
283 mtdcr(DCRN_PEGPL_REGBAH(PCIE2), 0x0000000c);
284 mtdcr(DCRN_PEGPL_REGBAL(PCIE2), 0x20002000);
285 mtdcr(DCRN_PEGPL_REGMSK(PCIE2), 0x00007001);
286 mtdcr(DCRN_PEGPL_SPECIAL(PCIE2), 0x68782800);
289 utl_base = (unsigned int *)(CONFIG_SYS_PCIE_BASE + 0x1000 * port);
292 * Set buffer allocations and then assert VRB and TXE.
294 out_be32(utl_base + PEUTL_OUTTR, 0x08000000);
295 out_be32(utl_base + PEUTL_INTR, 0x02000000);
296 out_be32(utl_base + PEUTL_OPDBSZ, 0x10000000);
297 out_be32(utl_base + PEUTL_PBBSZ, 0x53000000);
298 out_be32(utl_base + PEUTL_IPHBSZ, 0x08000000);
299 out_be32(utl_base + PEUTL_IPDBSZ, 0x10000000);
300 out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000);
301 out_be32(utl_base + PEUTL_PCTL, 0x80800066);
304 static int check_error(void)
306 u32 valPE0, valPE1, valPE2;
309 /* SDR0_PEGPLLLCT1 reset */
310 if (!(valPE0 = SDR_READ(PESDR0_PLLLCT1) & 0x01000000))
311 printf("PCIE: SDR0_PEGPLLLCT1 reset error 0x%x\n", valPE0);
313 valPE0 = SDR_READ(PESDR0_RCSSET);
314 valPE1 = SDR_READ(PESDR1_RCSSET);
315 valPE2 = SDR_READ(PESDR2_RCSSET);
317 /* SDR0_PExRCSSET rstgu */
318 if (!(valPE0 & 0x01000000) ||
319 !(valPE1 & 0x01000000) ||
320 !(valPE2 & 0x01000000)) {
321 printf("PCIE: SDR0_PExRCSSET rstgu error\n");
325 /* SDR0_PExRCSSET rstdl */
326 if (!(valPE0 & 0x00010000) ||
327 !(valPE1 & 0x00010000) ||
328 !(valPE2 & 0x00010000)) {
329 printf("PCIE: SDR0_PExRCSSET rstdl error\n");
333 /* SDR0_PExRCSSET rstpyn */
334 if ((valPE0 & 0x00001000) ||
335 (valPE1 & 0x00001000) ||
336 (valPE2 & 0x00001000)) {
337 printf("PCIE: SDR0_PExRCSSET rstpyn error\n");
341 /* SDR0_PExRCSSET hldplb */
342 if ((valPE0 & 0x10000000) ||
343 (valPE1 & 0x10000000) ||
344 (valPE2 & 0x10000000)) {
345 printf("PCIE: SDR0_PExRCSSET hldplb error\n");
349 /* SDR0_PExRCSSET rdy */
350 if ((valPE0 & 0x00100000) ||
351 (valPE1 & 0x00100000) ||
352 (valPE2 & 0x00100000)) {
353 printf("PCIE: SDR0_PExRCSSET rdy error\n");
357 /* SDR0_PExRCSSET shutdown */
358 if ((valPE0 & 0x00000100) ||
359 (valPE1 & 0x00000100) ||
360 (valPE2 & 0x00000100)) {
361 printf("PCIE: SDR0_PExRCSSET shutdown error\n");
368 * Initialize PCI Express core
370 int ppc4xx_init_pcie(void)
374 /* Set PLL clock receiver to LVPECL */
375 SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) | 1 << 28);
378 printf("ERROR: failed to set PCIe reference clock receiver --"
379 "PESDR0_PLLLCT1 = 0x%08x\n", SDR_READ(PESDR0_PLLLCT1));
384 /* Did resistance calibration work? */
385 if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000)) {
386 printf("ERROR: PCIe resistance calibration failed --"
387 "PESDR0_PLLLCT2 = 0x%08x\n", SDR_READ(PESDR0_PLLLCT2));
391 /* De-assert reset of PCIe PLL, wait for lock */
392 SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 << 24));
393 udelay(300); /* 300 uS is maximum time lock should take */
396 if (!(SDR_READ(PESDR0_PLLLCT3) & 0x10000000)) {
398 udelay(20); /* Wait 20 uS more if needed */
403 printf("ERROR: PCIe PLL VCO output not locked to ref clock --"
404 "PESDR0_PLLLCTS=0x%08x\n", SDR_READ(PESDR0_PLLLCT3));
412 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
413 static void ppc4xx_setup_utl(u32 port)
415 volatile void *utl_base = NULL;
418 * Map UTL registers at 0x0801_n000 (4K 0xfff mask) PEGPLn_REGMSK
422 mtdcr(DCRN_PEGPL_REGBAH(PCIE0), U64_TO_U32_HIGH(CONFIG_SYS_PCIE0_UTLBASE));
423 mtdcr(DCRN_PEGPL_REGBAL(PCIE0), U64_TO_U32_LOW(CONFIG_SYS_PCIE0_UTLBASE));
424 mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); /* BAM 11100000=4KB */
425 mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0);
429 mtdcr(DCRN_PEGPL_REGBAH(PCIE1), U64_TO_U32_HIGH(CONFIG_SYS_PCIE0_UTLBASE));
430 mtdcr(DCRN_PEGPL_REGBAL(PCIE1), U64_TO_U32_LOW(CONFIG_SYS_PCIE0_UTLBASE)
432 mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); /* BAM 11100000=4KB */
433 mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0);
436 utl_base = (unsigned int *)(CONFIG_SYS_PCIE_BASE + 0x1000 * port);
439 * Set buffer allocations and then assert VRB and TXE.
441 out_be32(utl_base + PEUTL_PBCTL, 0x0800000c); /* PLBME, CRRE */
442 out_be32(utl_base + PEUTL_OUTTR, 0x08000000);
443 out_be32(utl_base + PEUTL_INTR, 0x02000000);
444 out_be32(utl_base + PEUTL_OPDBSZ, 0x04000000); /* OPD = 512 Bytes */
445 out_be32(utl_base + PEUTL_PBBSZ, 0x00000000); /* Max 512 Bytes */
446 out_be32(utl_base + PEUTL_IPHBSZ, 0x02000000);
447 out_be32(utl_base + PEUTL_IPDBSZ, 0x04000000); /* IPD = 512 Bytes */
448 out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000);
449 out_be32(utl_base + PEUTL_PCTL, 0x80800066); /* VRB,TXE,timeout=default */
453 * TODO: double check PCI express SDR based on the latest user manual
454 * Some registers specified here no longer exist.. has to be
455 * updated based on the final EAS spec.
457 static int check_error(void)
462 valPE0 = SDR_READ(SDRN_PESDR_RCSSET(0));
463 valPE1 = SDR_READ(SDRN_PESDR_RCSSET(1));
465 /* SDR0_PExRCSSET rstgu */
466 if (!(valPE0 & PESDRx_RCSSET_RSTGU) || !(valPE1 & PESDRx_RCSSET_RSTGU)) {
467 printf("PCIE: SDR0_PExRCSSET rstgu error\n");
471 /* SDR0_PExRCSSET rstdl */
472 if (!(valPE0 & PESDRx_RCSSET_RSTDL) || !(valPE1 & PESDRx_RCSSET_RSTDL)) {
473 printf("PCIE: SDR0_PExRCSSET rstdl error\n");
477 /* SDR0_PExRCSSET rstpyn */
478 if ((valPE0 & PESDRx_RCSSET_RSTPYN) || (valPE1 & PESDRx_RCSSET_RSTPYN)) {
479 printf("PCIE: SDR0_PExRCSSET rstpyn error\n");
483 /* SDR0_PExRCSSET hldplb */
484 if ((valPE0 & PESDRx_RCSSET_HLDPLB) || (valPE1 & PESDRx_RCSSET_HLDPLB)) {
485 printf("PCIE: SDR0_PExRCSSET hldplb error\n");
489 /* SDR0_PExRCSSET rdy */
490 if ((valPE0 & PESDRx_RCSSET_RDY) || (valPE1 & PESDRx_RCSSET_RDY)) {
491 printf("PCIE: SDR0_PExRCSSET rdy error\n");
499 * Initialize PCI Express core as described in User Manual
500 * TODO: double check PE SDR PLL Register with the updated user manual.
502 int ppc4xx_init_pcie(void)
509 #endif /* CONFIG_460EX */
511 #if defined(CONFIG_405EX)
512 static void ppc4xx_setup_utl(u32 port)
517 * Map UTL registers at 0xef4f_n000 (4K 0xfff mask) PEGPLn_REGMSK
521 mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x00000000);
522 mtdcr(DCRN_PEGPL_REGBAL(PCIE0), CONFIG_SYS_PCIE0_UTLBASE);
523 mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); /* 4k region, valid */
524 mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0);
528 mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x00000000);
529 mtdcr(DCRN_PEGPL_REGBAL(PCIE1), CONFIG_SYS_PCIE1_UTLBASE);
530 mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); /* 4k region, valid */
531 mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0);
535 utl_base = (port==0) ? CONFIG_SYS_PCIE0_UTLBASE : CONFIG_SYS_PCIE1_UTLBASE;
538 * Set buffer allocations and then assert VRB and TXE.
540 out_be32((u32 *)(utl_base + PEUTL_OUTTR), 0x02000000);
541 out_be32((u32 *)(utl_base + PEUTL_INTR), 0x02000000);
542 out_be32((u32 *)(utl_base + PEUTL_OPDBSZ), 0x04000000);
543 out_be32((u32 *)(utl_base + PEUTL_PBBSZ), 0x21000000);
544 out_be32((u32 *)(utl_base + PEUTL_IPHBSZ), 0x02000000);
545 out_be32((u32 *)(utl_base + PEUTL_IPDBSZ), 0x04000000);
546 out_be32((u32 *)(utl_base + PEUTL_RCIRQEN), 0x00f00000);
547 out_be32((u32 *)(utl_base + PEUTL_PCTL), 0x80800066);
549 out_be32((u32 *)(utl_base + PEUTL_PBCTL), 0x0800000c);
550 out_be32((u32 *)(utl_base + PEUTL_RCSTA),
551 in_be32((u32 *)(utl_base + PEUTL_RCSTA)) | 0x000040000);
554 int ppc4xx_init_pcie(void)
557 * Nothing to do on 405EX
561 #endif /* CONFIG_405EX */
564 * Board-specific pcie initialization
565 * Platform code can reimplement ppc4xx_init_pcie_port_hw() if needed
569 * Initialize various parts of the PCI Express core for our port:
571 * - Set as a root port and enable max width
572 * (PXIE0 -> X8, PCIE1 and PCIE2 -> X4).
573 * - Set up UTL configuration.
574 * - Increase SERDES drive strength to levels suggested by AMCC.
575 * - De-assert RSTPYN, RSTDL and RSTGU.
577 * NOTICE for 440SPE revB chip: PESDRn_UTLSET2 is not set - we leave it
578 * with default setting 0x11310000. The register has new fields,
579 * PESDRn_UTLSET2[LKINE] in particular: clearing it leads to PCIE core
582 #if defined(CONFIG_440SPE)
583 int __ppc4xx_init_pcie_port_hw(int port, int rootport)
589 val = PTYPE_ROOT_PORT << 20;
590 utlset1 = 0x21222222;
592 val = PTYPE_LEGACY_ENDPOINT << 20;
593 utlset1 = 0x20222222;
597 val |= LNKW_X8 << 12;
599 val |= LNKW_X4 << 12;
601 SDR_WRITE(SDRN_PESDR_DLPSET(port), val);
602 SDR_WRITE(SDRN_PESDR_UTLSET1(port), utlset1);
603 if (!ppc440spe_revB())
604 SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x11000000);
605 SDR_WRITE(SDRN_PESDR_HSSL0SET1(port), 0x35000000);
606 SDR_WRITE(SDRN_PESDR_HSSL1SET1(port), 0x35000000);
607 SDR_WRITE(SDRN_PESDR_HSSL2SET1(port), 0x35000000);
608 SDR_WRITE(SDRN_PESDR_HSSL3SET1(port), 0x35000000);
610 SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000);
611 SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000);
612 SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000);
613 SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000);
615 SDR_WRITE(SDRN_PESDR_RCSSET(port), (SDR_READ(SDRN_PESDR_RCSSET(port)) &
616 ~(1 << 24 | 1 << 16)) | 1 << 12);
620 #endif /* CONFIG_440SPE */
622 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
623 int __ppc4xx_init_pcie_port_hw(int port, int rootport)
629 val = PTYPE_ROOT_PORT << 20;
631 val = PTYPE_LEGACY_ENDPOINT << 20;
634 val |= LNKW_X1 << 12;
635 utlset1 = 0x20000000;
637 val |= LNKW_X4 << 12;
638 utlset1 = 0x20101101;
641 SDR_WRITE(SDRN_PESDR_DLPSET(port), val);
642 SDR_WRITE(SDRN_PESDR_UTLSET1(port), utlset1);
643 SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x01210000);
647 SDR_WRITE(PESDR0_L0CDRCTL, 0x00003230);
648 SDR_WRITE(PESDR0_L0DRV, 0x00000130);
649 SDR_WRITE(PESDR0_L0CLK, 0x00000006);
651 SDR_WRITE(PESDR0_PHY_CTL_RST,0x10000000);
655 SDR_WRITE(PESDR1_L0CDRCTL, 0x00003230);
656 SDR_WRITE(PESDR1_L1CDRCTL, 0x00003230);
657 SDR_WRITE(PESDR1_L2CDRCTL, 0x00003230);
658 SDR_WRITE(PESDR1_L3CDRCTL, 0x00003230);
659 SDR_WRITE(PESDR1_L0DRV, 0x00000130);
660 SDR_WRITE(PESDR1_L1DRV, 0x00000130);
661 SDR_WRITE(PESDR1_L2DRV, 0x00000130);
662 SDR_WRITE(PESDR1_L3DRV, 0x00000130);
663 SDR_WRITE(PESDR1_L0CLK, 0x00000006);
664 SDR_WRITE(PESDR1_L1CLK, 0x00000006);
665 SDR_WRITE(PESDR1_L2CLK, 0x00000006);
666 SDR_WRITE(PESDR1_L3CLK, 0x00000006);
668 SDR_WRITE(PESDR1_PHY_CTL_RST,0x10000000);
672 SDR_WRITE(SDRN_PESDR_RCSSET(port), SDR_READ(SDRN_PESDR_RCSSET(port)) |
673 (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTPYN));
675 /* Poll for PHY reset */
678 while (!(SDR_READ(PESDR0_RSTSTA) & 0x1))
682 while (!(SDR_READ(PESDR1_RSTSTA) & 0x1))
687 SDR_WRITE(SDRN_PESDR_RCSSET(port),
688 (SDR_READ(SDRN_PESDR_RCSSET(port)) &
689 ~(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL)) |
690 PESDRx_RCSSET_RSTPYN);
694 #endif /* CONFIG_440SPE */
696 #if defined(CONFIG_405EX)
697 int __ppc4xx_init_pcie_port_hw(int port, int rootport)
706 SDR_WRITE(SDRN_PESDR_DLPSET(port), val);
707 SDR_WRITE(SDRN_PESDR_UTLSET1(port), 0x00000000);
708 SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x01010000);
709 SDR_WRITE(SDRN_PESDR_PHYSET1(port), 0x720F0000);
710 SDR_WRITE(SDRN_PESDR_PHYSET2(port), 0x70600003);
712 /* Assert the PE0_PHY reset */
713 SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01010000);
716 /* deassert the PE0_hotreset */
717 if (is_end_point(port))
718 SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01111000);
720 SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01101000);
722 /* poll for phy !reset */
723 while (!(SDR_READ(SDRN_PESDR_PHYSTA(port)) & 0x00001000))
726 /* deassert the PE0_gpl_utl_reset */
727 SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x00101000);
730 mtdcr(DCRN_PEGPL_CFG(PCIE0), 0x10000000); /* guarded on */
732 mtdcr(DCRN_PEGPL_CFG(PCIE1), 0x10000000); /* guarded on */
736 #endif /* CONFIG_405EX */
738 int ppc4xx_init_pcie_port_hw(int port, int rootport)
739 __attribute__((weak, alias("__ppc4xx_init_pcie_port_hw")));
742 * We map PCI Express configuration access into the 512MB regions
744 * NOTICE: revB is very strict about PLB real addressess and ranges to
745 * be mapped for config space; it seems to only work with d_nnnn_nnnn
746 * range (hangs the core upon config transaction attempts when set
747 * otherwise) while revA uses c_nnnn_nnnn.
750 * PCIE0: 0xc_4000_0000
751 * PCIE1: 0xc_8000_0000
752 * PCIE2: 0xc_c000_0000
755 * PCIE0: 0xd_0000_0000
756 * PCIE1: 0xd_2000_0000
757 * PCIE2: 0xd_4000_0000
764 * PCIE0: 0xd_0000_0000
765 * PCIE1: 0xd_2000_0000
767 static inline u64 ppc4xx_get_cfgaddr(int port)
769 #if defined(CONFIG_405EX)
771 return (u64)CONFIG_SYS_PCIE0_CFGBASE;
773 return (u64)CONFIG_SYS_PCIE1_CFGBASE;
775 #if defined(CONFIG_440SPE)
776 if (ppc440spe_revB()) {
778 default: /* to satisfy compiler */
780 return 0x0000000d00000000ULL;
782 return 0x0000000d20000000ULL;
784 return 0x0000000d40000000ULL;
788 default: /* to satisfy compiler */
790 return 0x0000000c40000000ULL;
792 return 0x0000000c80000000ULL;
794 return 0x0000000cc0000000ULL;
798 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
800 return 0x0000000d00000000ULL;
802 return 0x0000000d20000000ULL;
807 * 4xx boards as end point and root point setup
809 * testing inbound and out bound windows
811 * 4xx boards can be plugged into another 4xx boards or you can get PCI-E
812 * cable which can be used to setup loop back from one port to another port.
813 * Please rememeber that unless there is a endpoint plugged in to root port it
814 * will not initialize. It is the same in case of endpoint , unless there is
815 * root port attached it will not initialize.
817 * In this release of software all the PCI-E ports are configured as either
818 * endpoint or rootpoint.In future we will have support for selective ports
819 * setup as endpoint and root point in single board.
821 * Once your board came up as root point , you can verify by reading
822 * /proc/bus/pci/devices. Where you can see the configuration registers
823 * of end point device attached to the port.
825 * Enpoint cofiguration can be verified by connecting 4xx board to any
826 * host or another 4xx board. Then try to scan the device. In case of
827 * linux use "lspci" or appripriate os command.
829 * How do I verify the inbound and out bound windows ? (4xx to 4xx)
830 * in this configuration inbound and outbound windows are setup to access
831 * sram memroy area. SRAM is at 0x4 0000 0000 , on PLB bus. This address
832 * is mapped at 0x90000000. From u-boot prompt write data 0xb000 0000,
833 * This is waere your POM(PLB out bound memory window) mapped. then
834 * read the data from other 4xx board's u-boot prompt at address
835 * 0x9000 0000(SRAM). Data should match.
836 * In case of inbound , write data to u-boot command prompt at 0xb000 0000
837 * which is mapped to 0x4 0000 0000. Now on rootpoint yucca u-boot prompt check
838 * data at 0x9000 0000(SRAM).Data should match.
840 int ppc4xx_init_pcie_port(int port, int rootport)
842 static int core_init;
843 volatile u32 val = 0;
849 if (ppc4xx_init_pcie())
855 * Initialize various parts of the PCI Express core for our port
857 ppc4xx_init_pcie_port_hw(port, rootport);
860 * Notice: the following delay has critical impact on device
861 * initialization - if too short (<50ms) the link doesn't get up.
865 val = SDR_READ(SDRN_PESDR_RCSSTS(port));
866 if (val & (1 << 20)) {
867 printf("PCIE%d: PGRST failed %08x\n", port, val);
874 val = SDR_READ(SDRN_PESDR_LOOP(port));
875 if (!(val & 0x00001000)) {
876 printf("PCIE%d: link is not up.\n", port);
881 * Setup UTL registers - but only on revA!
882 * We use default settings for revB chip.
884 if (!ppc440spe_revB())
885 ppc4xx_setup_utl(port);
888 * We map PCI Express configuration access into the 512MB regions
890 addr = ppc4xx_get_cfgaddr(port);
891 low = U64_TO_U32_LOW(addr);
892 high = U64_TO_U32_HIGH(addr);
896 mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), high);
897 mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), low);
898 mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */
901 mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), high);
902 mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), low);
903 mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */
905 #if CONFIG_SYS_PCIE_NR_PORTS > 2
907 mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), high);
908 mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), low);
909 mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */
915 * Check for VC0 active and assert RDY.
918 while(!(SDR_READ(SDRN_PESDR_RCSSTS(port)) & (1 << 16))) {
920 printf("PCIE%d: VC0 not active\n", port);
925 SDR_WRITE(SDRN_PESDR_RCSSET(port),
926 SDR_READ(SDRN_PESDR_RCSSET(port)) | 1 << 20);
932 int ppc4xx_init_pcie_rootport(int port)
934 return ppc4xx_init_pcie_port(port, 1);
937 int ppc4xx_init_pcie_endport(int port)
939 return ppc4xx_init_pcie_port(port, 0);
942 void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port)
944 volatile void *mbase = NULL;
945 volatile void *rmbase = NULL;
948 pcie_read_config_byte,
949 pcie_read_config_word,
950 pcie_read_config_dword,
951 pcie_write_config_byte,
952 pcie_write_config_word,
953 pcie_write_config_dword);
957 mbase = (u32 *)CONFIG_SYS_PCIE0_XCFGBASE;
958 rmbase = (u32 *)CONFIG_SYS_PCIE0_CFGBASE;
959 hose->cfg_data = (u8 *)CONFIG_SYS_PCIE0_CFGBASE;
962 mbase = (u32 *)CONFIG_SYS_PCIE1_XCFGBASE;
963 rmbase = (u32 *)CONFIG_SYS_PCIE1_CFGBASE;
964 hose->cfg_data = (u8 *)CONFIG_SYS_PCIE1_CFGBASE;
966 #if CONFIG_SYS_PCIE_NR_PORTS > 2
968 mbase = (u32 *)CONFIG_SYS_PCIE2_XCFGBASE;
969 rmbase = (u32 *)CONFIG_SYS_PCIE2_CFGBASE;
970 hose->cfg_data = (u8 *)CONFIG_SYS_PCIE2_CFGBASE;
976 * Set bus numbers on our root port
978 out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
979 out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1);
980 out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1);
983 * Set up outbound translation to hose->mem_space from PLB
984 * addresses at an offset of 0xd_0000_0000. We set the low
985 * bits of the mask to 11 to turn off splitting into 8
986 * subregions and to enable the outbound translation.
988 out_le32(mbase + PECFG_POM0LAH, 0x00000000);
989 out_le32(mbase + PECFG_POM0LAL, CONFIG_SYS_PCIE_MEMBASE +
990 port * CONFIG_SYS_PCIE_MEMSIZE);
991 debug("PECFG_POM0LA=%08x.%08x\n", in_le32(mbase + PECFG_POM0LAH),
992 in_le32(mbase + PECFG_POM0LAL));
996 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CONFIG_SYS_PCIE_ADDR_HIGH);
997 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CONFIG_SYS_PCIE_MEMBASE +
998 port * CONFIG_SYS_PCIE_MEMSIZE);
999 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
1000 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
1001 ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
1002 debug("0:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n",
1003 mfdcr(DCRN_PEGPL_OMR1BAH(PCIE0)),
1004 mfdcr(DCRN_PEGPL_OMR1BAL(PCIE0)),
1005 mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE0)),
1006 mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE0)));
1009 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CONFIG_SYS_PCIE_ADDR_HIGH);
1010 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CONFIG_SYS_PCIE_MEMBASE +
1011 port * CONFIG_SYS_PCIE_MEMSIZE);
1012 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
1013 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
1014 ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
1015 debug("1:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n",
1016 mfdcr(DCRN_PEGPL_OMR1BAH(PCIE1)),
1017 mfdcr(DCRN_PEGPL_OMR1BAL(PCIE1)),
1018 mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE1)),
1019 mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE1)));
1021 #if CONFIG_SYS_PCIE_NR_PORTS > 2
1023 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CONFIG_SYS_PCIE_ADDR_HIGH);
1024 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CONFIG_SYS_PCIE_MEMBASE +
1025 port * CONFIG_SYS_PCIE_MEMSIZE);
1026 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
1027 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
1028 ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
1029 debug("2:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n",
1030 mfdcr(DCRN_PEGPL_OMR1BAH(PCIE2)),
1031 mfdcr(DCRN_PEGPL_OMR1BAL(PCIE2)),
1032 mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE2)),
1033 mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE2)));
1038 /* Set up 4GB inbound memory window at 0 */
1039 out_le32(mbase + PCI_BASE_ADDRESS_0, 0);
1040 out_le32(mbase + PCI_BASE_ADDRESS_1, 0);
1041 out_le32(mbase + PECFG_BAR0HMPA, 0x7ffffff);
1042 out_le32(mbase + PECFG_BAR0LMPA, 0);
1044 out_le32(mbase + PECFG_PIM01SAH, 0xffff0000);
1045 out_le32(mbase + PECFG_PIM01SAL, 0x00000000);
1046 out_le32(mbase + PECFG_PIM0LAL, 0);
1047 out_le32(mbase + PECFG_PIM0LAH, 0);
1048 out_le32(mbase + PECFG_PIM1LAL, 0x00000000);
1049 out_le32(mbase + PECFG_PIM1LAH, 0x00000004);
1050 out_le32(mbase + PECFG_PIMEN, 0x1);
1052 /* Enable I/O, Mem, and Busmaster cycles */
1053 out_le16((u16 *)(mbase + PCI_COMMAND),
1054 in_le16((u16 *)(mbase + PCI_COMMAND)) |
1055 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
1057 /* Set Device and Vendor Id */
1058 out_le16(mbase + 0x200, 0xaaa0 + port);
1059 out_le16(mbase + 0x202, 0xbed0 + port);
1061 /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */
1062 out_le32(mbase + 0x208, 0x06040001);
1064 printf("PCIE%d: successfully set as root-complex\n", port);
1067 int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port)
1069 volatile void *mbase = NULL;
1073 pcie_read_config_byte,
1074 pcie_read_config_word,
1075 pcie_read_config_dword,
1076 pcie_write_config_byte,
1077 pcie_write_config_word,
1078 pcie_write_config_dword);
1082 mbase = (u32 *)CONFIG_SYS_PCIE0_XCFGBASE;
1083 hose->cfg_data = (u8 *)CONFIG_SYS_PCIE0_CFGBASE;
1086 mbase = (u32 *)CONFIG_SYS_PCIE1_XCFGBASE;
1087 hose->cfg_data = (u8 *)CONFIG_SYS_PCIE1_CFGBASE;
1089 #if defined(CONFIG_SYS_PCIE2_CFGBASE)
1091 mbase = (u32 *)CONFIG_SYS_PCIE2_XCFGBASE;
1092 hose->cfg_data = (u8 *)CONFIG_SYS_PCIE2_CFGBASE;
1098 * Set up outbound translation to hose->mem_space from PLB
1099 * addresses at an offset of 0xd_0000_0000. We set the low
1100 * bits of the mask to 11 to turn off splitting into 8
1101 * subregions and to enable the outbound translation.
1103 out_le32(mbase + PECFG_POM0LAH, 0x00001ff8);
1104 out_le32(mbase + PECFG_POM0LAL, 0x00001000);
1108 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CONFIG_SYS_PCIE_ADDR_HIGH);
1109 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CONFIG_SYS_PCIE_MEMBASE +
1110 port * CONFIG_SYS_PCIE_MEMSIZE);
1111 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
1112 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
1113 ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
1116 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CONFIG_SYS_PCIE_ADDR_HIGH);
1117 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CONFIG_SYS_PCIE_MEMBASE +
1118 port * CONFIG_SYS_PCIE_MEMSIZE);
1119 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
1120 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
1121 ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
1123 #if CONFIG_SYS_PCIE_NR_PORTS > 2
1125 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CONFIG_SYS_PCIE_ADDR_HIGH);
1126 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CONFIG_SYS_PCIE_MEMBASE +
1127 port * CONFIG_SYS_PCIE_MEMSIZE);
1128 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
1129 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
1130 ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
1135 /* Set up 64MB inbound memory window at 0 */
1136 out_le32(mbase + PCI_BASE_ADDRESS_0, 0);
1137 out_le32(mbase + PCI_BASE_ADDRESS_1, 0);
1139 out_le32(mbase + PECFG_PIM01SAH, 0xffffffff);
1140 out_le32(mbase + PECFG_PIM01SAL, 0xfc000000);
1143 out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffff);
1144 out_le32(mbase + PECFG_BAR0LMPA, 0xfc000000 | PCI_BASE_ADDRESS_MEM_TYPE_64);
1146 /* Disable BAR1 & BAR2 */
1147 out_le32(mbase + PECFG_BAR1MPA, 0);
1148 out_le32(mbase + PECFG_BAR2HMPA, 0);
1149 out_le32(mbase + PECFG_BAR2LMPA, 0);
1151 out_le32(mbase + PECFG_PIM0LAL, U64_TO_U32_LOW(CONFIG_SYS_PCIE_INBOUND_BASE));
1152 out_le32(mbase + PECFG_PIM0LAH, U64_TO_U32_HIGH(CONFIG_SYS_PCIE_INBOUND_BASE));
1153 out_le32(mbase + PECFG_PIMEN, 0x1);
1155 /* Enable I/O, Mem, and Busmaster cycles */
1156 out_le16((u16 *)(mbase + PCI_COMMAND),
1157 in_le16((u16 *)(mbase + PCI_COMMAND)) |
1158 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
1159 out_le16(mbase + 0x200, 0xcaad); /* Setting vendor ID */
1160 out_le16(mbase + 0x202, 0xfeed); /* Setting device ID */
1162 /* Set Class Code to Processor/PPC */
1163 out_le32(mbase + 0x208, 0x0b200001);
1166 while(!(SDR_READ(SDRN_PESDR_RCSSTS(port)) & (1 << 8))) {
1167 if (!(attempts--)) {
1168 printf("PCIE%d: BME not active\n", port);
1174 printf("PCIE%d: successfully set as endpoint\n", port);
1178 #endif /* CONFIG_440SPE && CONFIG_PCI */