2 * (C) Copyright 2000-2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * written or collected and sometimes rewritten by
28 * Magnus Damm <damm@bitsmart.com>
30 * minor modifications by
31 * Wolfgang Denk <wd@denx.de>
37 #include <asm/cache.h>
40 #if !defined(CONFIG_405)
41 DECLARE_GLOBAL_DATA_PTR;
44 #if defined(CONFIG_BOARD_RESET)
45 void board_reset(void);
48 #if defined(CONFIG_440)
49 #define FREQ_EBC (sys_info.freqEPB)
51 #define FREQ_EBC (sys_info.freqPLB / sys_info.pllExtBusDiv)
54 #if defined(CONFIG_405GP) || \
55 defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
56 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
60 int pci_async_enabled(void)
62 #if defined(CONFIG_405GP)
63 return (mfdcr(strap) & PSR_PCI_ASYNC_EN);
66 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
67 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
70 mfsdr(sdr_sdstp1, val);
71 return (val & SDR0_SDSTP1_PAME_MASK);
76 #if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && !defined(CONFIG_405)
77 int pci_arbiter_enabled(void)
79 #if defined(CONFIG_405GP)
80 return (mfdcr(strap) & PSR_PCI_ARBIT_EN);
83 #if defined(CONFIG_405EP)
84 return (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN);
87 #if defined(CONFIG_440GP)
88 return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK);
91 #if defined(CONFIG_440GX) || \
92 defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
93 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
94 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
97 mfsdr(sdr_sdstp1, val);
98 return (val & SDR0_SDSTP1_PAE_MASK);
103 #if defined(CONFIG_405EP) || defined(CONFIG_440GX) || \
104 defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
105 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
106 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
110 int i2c_bootrom_enabled(void)
112 #if defined(CONFIG_405EP)
113 return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP);
117 mfsdr(sdr_sdcs, val);
118 return (val & SDR0_SDCS_SDD);
122 #if defined(CONFIG_440GX)
123 #define SDR0_PINSTP_SHIFT 29
124 static char *bootstrap_str[] = {
136 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
137 #define SDR0_PINSTP_SHIFT 30
138 static char *bootstrap_str[] = {
146 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
147 #define SDR0_PINSTP_SHIFT 29
148 static char *bootstrap_str[] = {
160 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
161 #define SDR0_PINSTP_SHIFT 29
162 static char *bootstrap_str[] = {
174 #if defined(SDR0_PINSTP_SHIFT)
175 static int bootstrap_option(void)
179 mfsdr(sdr_pinstp, val);
180 return ((val & 0xe0000000) >> SDR0_PINSTP_SHIFT);
182 #endif /* SDR0_PINSTP_SHIFT */
186 #if defined(CONFIG_440)
187 static int do_chip_reset(unsigned long sys0, unsigned long sys1);
193 #if !defined(CONFIG_405) /* not used on Xilinx 405 FPGA implementations */
194 uint pvr = get_pvr();
195 ulong clock = gd->cpu_clk;
198 #if !defined(CONFIG_IOP480)
199 char addstr[64] = "";
204 get_sys_info(&sys_info);
206 puts("AMCC PowerPC 4");
208 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP)
211 #if defined(CONFIG_440)
229 case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */
243 case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */
256 #if defined(CONFIG_440)
259 /* See errata 1.12: CHIP_4 */
260 if ((mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0)) ||
261 (mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1)) ){
262 puts ( "\n\t CPC0_SYSx DCRs corrupted. "
263 "Resetting chip ...\n");
264 udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
265 do_chip_reset ( mfdcr(cpc0_strp0),
295 case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */
299 case PVR_440EP_RC: /* 440EP rev C and 440GR rev B have same PVR */
302 #endif /* CONFIG_440EP */
305 case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */
309 case PVR_440GR_RB: /* 440EP rev C and 440GR rev B have same PVR */
312 #endif /* CONFIG_440GR */
313 #endif /* CONFIG_440 */
317 strcpy(addstr, "Security/Kasumi support");
322 strcpy(addstr, "No Security/Kasumi support");
327 strcpy(addstr, "Security/Kasumi support");
332 strcpy(addstr, "No Security/Kasumi support");
335 case PVR_440SP_6_RAB:
337 strcpy(addstr, "RAID 6 support");
342 strcpy(addstr, "No RAID 6 support");
347 strcpy(addstr, "RAID 6 support");
352 strcpy(addstr, "No RAID 6 support");
355 case PVR_440SPe_6_RA:
357 strcpy(addstr, "RAID 6 support");
362 strcpy(addstr, "No RAID 6 support");
365 case PVR_440SPe_6_RB:
367 strcpy(addstr, "RAID 6 support");
372 strcpy(addstr, "No RAID 6 support");
376 printf (" UNKNOWN (PVR=%08x)", pvr);
380 printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock),
381 sys_info.freqPLB / 1000000,
382 sys_info.freqPLB / sys_info.pllOpbDiv / 1000000,
386 printf(" %s\n", addstr);
388 #if defined(I2C_BOOTROM)
389 printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
390 #if defined(SDR0_PINSTP_SHIFT)
391 printf (" Bootstrap Option %c - ", (char)bootstrap_option() + 'A');
392 printf ("Boot ROM Location %s\n", bootstrap_str[bootstrap_option()]);
393 #endif /* SDR0_PINSTP_SHIFT */
394 #endif /* I2C_BOOTROM */
396 #if defined(CONFIG_PCI)
397 printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
400 #if defined(PCI_ASYNC)
401 if (pci_async_enabled()) {
402 printf (", PCI async ext clock used");
404 printf (", PCI sync clock at %lu MHz",
405 sys_info.freqPLB / sys_info.pllPciDiv / 1000000);
409 #if defined(CONFIG_PCI)
413 #if defined(CONFIG_405EP)
414 printf (" 16 kB I-Cache 16 kB D-Cache");
415 #elif defined(CONFIG_440)
416 printf (" 32 kB I-Cache 32 kB D-Cache");
418 printf (" 16 kB I-Cache %d kB D-Cache",
419 ((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
421 #endif /* !defined(CONFIG_IOP480) */
423 #if defined(CONFIG_IOP480)
424 printf ("PLX IOP480 (PVR=%08x)", pvr);
425 printf (" at %s MHz:", strmhz(buf, clock));
426 printf (" %u kB I-Cache", 4);
427 printf (" %u kB D-Cache", 2);
430 #endif /* !defined(CONFIG_405) */
437 #if defined (CONFIG_440SPE)
438 int ppc440spe_revB() {
442 if ((pvr == PVR_440SPe_6_RB) || (pvr == PVR_440SPe_RB))
449 /* ------------------------------------------------------------------------- */
451 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
453 #if defined(CONFIG_BOARD_RESET)
456 #if defined(CFG_4xx_RESET_TYPE)
457 mtspr(dbcr0, CFG_4xx_RESET_TYPE << 28);
460 * Initiate system reset in debug control register DBCR
462 mtspr(dbcr0, 0x30000000);
463 #endif /* defined(CFG_4xx_RESET_TYPE) */
464 #endif /* defined(CONFIG_BOARD_RESET) */
469 #if defined(CONFIG_440)
470 static int do_chip_reset (unsigned long sys0, unsigned long sys1)
472 /* Changes to cpc0_sys0 and cpc0_sys1 require chip
475 mtdcr (cntrl0, mfdcr (cntrl0) | 0x80000000); /* Set SWE */
476 mtdcr (cpc0_sys0, sys0);
477 mtdcr (cpc0_sys1, sys1);
478 mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000); /* Clr SWE */
479 mtspr (dbcr0, 0x20000000); /* Reset the chip */
487 * Get timebase clock frequency
489 unsigned long get_tbclk (void)
491 #if !defined(CONFIG_IOP480)
494 get_sys_info(&sys_info);
495 return (sys_info.freqProcessor);
503 #if defined(CONFIG_WATCHDOG)
507 int re_enable = disable_interrupts();
508 reset_4xx_watchdog();
509 if (re_enable) enable_interrupts();
513 reset_4xx_watchdog(void)
518 mtspr(tsr, 0x40000000);
520 #endif /* CONFIG_WATCHDOG */