2 * (C) Copyright 2000-2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <ppc4xx_enet.h>
27 #include <asm/processor.h>
30 #if defined(CONFIG_405GP) || defined(CONFIG_405EP)
31 DECLARE_GLOBAL_DATA_PTR;
35 #define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
37 #ifdef CFG_INIT_DCACHE_CS
38 # if (CFG_INIT_DCACHE_CS == 0)
41 # if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
42 # define PBxAP_VAL CFG_EBC_PB0AP
43 # define PBxCR_VAL CFG_EBC_PB0CR
46 # if (CFG_INIT_DCACHE_CS == 1)
49 # if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR))
50 # define PBxAP_VAL CFG_EBC_PB1AP
51 # define PBxCR_VAL CFG_EBC_PB1CR
54 # if (CFG_INIT_DCACHE_CS == 2)
57 # if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR))
58 # define PBxAP_VAL CFG_EBC_PB2AP
59 # define PBxCR_VAL CFG_EBC_PB2CR
62 # if (CFG_INIT_DCACHE_CS == 3)
65 # if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR))
66 # define PBxAP_VAL CFG_EBC_PB3AP
67 # define PBxCR_VAL CFG_EBC_PB3CR
70 # if (CFG_INIT_DCACHE_CS == 4)
73 # if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR))
74 # define PBxAP_VAL CFG_EBC_PB4AP
75 # define PBxCR_VAL CFG_EBC_PB4CR
78 # if (CFG_INIT_DCACHE_CS == 5)
81 # if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR))
82 # define PBxAP_VAL CFG_EBC_PB5AP
83 # define PBxCR_VAL CFG_EBC_PB5CR
86 # if (CFG_INIT_DCACHE_CS == 6)
89 # if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR))
90 # define PBxAP_VAL CFG_EBC_PB6AP
91 # define PBxCR_VAL CFG_EBC_PB6CR
94 # if (CFG_INIT_DCACHE_CS == 7)
97 # if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR))
98 # define PBxAP_VAL CFG_EBC_PB7AP
99 # define PBxCR_VAL CFG_EBC_PB7CR
102 #endif /* CFG_INIT_DCACHE_CS */
104 #if defined(CFG_440_GPIO_TABLE)
105 gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CFG_440_GPIO_TABLE;
107 void set_chip_gpio_configuration(gpio_param_s (*gpio_tab)[GPIO_GROUP_MAX][GPIO_MAX])
109 unsigned char i=0, j=0, reg_offset = 0, gpio_core;
110 unsigned long gpio_reg, gpio_core_add;
112 for (gpio_core=0; gpio_core<GPIO_GROUP_MAX; gpio_core++) {
115 /* GPIO config of the GPIOs 0 to 31 */
116 for (i=0; i<GPIO_MAX; i++, j++) {
117 if (i == GPIO_MAX/2) {
122 gpio_core_add = (*gpio_tab)[gpio_core][i].add;
124 if (((*gpio_tab)[gpio_core][i].in_out == GPIO_IN) ||
125 ((*gpio_tab)[gpio_core][i].in_out == GPIO_BI)) {
127 switch ((*gpio_tab)[gpio_core][i].alt_nb) {
132 gpio_reg = in32(GPIO_IS1(gpio_core_add+reg_offset))
133 & ~(GPIO_MASK >> (j*2));
134 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
135 out32(GPIO_IS1(gpio_core_add+reg_offset), gpio_reg);
139 gpio_reg = in32(GPIO_IS2(gpio_core_add+reg_offset))
140 & ~(GPIO_MASK >> (j*2));
141 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
142 out32(GPIO_IS2(gpio_core_add+reg_offset), gpio_reg);
146 gpio_reg = in32(GPIO_IS3(gpio_core_add+reg_offset))
147 & ~(GPIO_MASK >> (j*2));
148 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
149 out32(GPIO_IS3(gpio_core_add+reg_offset), gpio_reg);
154 if (((*gpio_tab)[gpio_core][i].in_out == GPIO_OUT) ||
155 ((*gpio_tab)[gpio_core][i].in_out == GPIO_BI)) {
157 switch ((*gpio_tab)[gpio_core][i].alt_nb) {
159 if (gpio_core == GPIO0) {
160 gpio_reg = in32(GPIO0_TCR) | (0x80000000 >> (j));
161 out32(GPIO0_TCR, gpio_reg);
164 if (gpio_core == GPIO1) {
165 gpio_reg = in32(GPIO1_TCR) | (0x80000000 >> (j));
166 out32(GPIO1_TCR, gpio_reg);
169 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset))
170 & ~(GPIO_MASK >> (j*2));
171 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
172 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset))
173 & ~(GPIO_MASK >> (j*2));
174 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
178 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset))
179 & ~(GPIO_MASK >> (j*2));
180 gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
181 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
182 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset))
183 & ~(GPIO_MASK >> (j*2));
184 gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
185 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
189 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset))
190 & ~(GPIO_MASK >> (j*2));
191 gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
192 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
193 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset))
194 & ~(GPIO_MASK >> (j*2));
195 gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
196 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
200 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset))
201 & ~(GPIO_MASK >> (j*2));
202 gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
203 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
204 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset))
205 & ~(GPIO_MASK >> (j*2));
206 gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
207 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
214 #endif /* CFG_440_GPIO_TABLE */
217 * Breath some life into the CPU...
219 * Set up the memory map,
220 * initialize a bunch of registers
225 #if defined(CONFIG_405EP)
227 * GPIO0 setup (select GPIO or alternate function)
229 #if defined(CFG_GPIO0_OR)
230 out32(GPIO0_OR, CFG_GPIO0_OR); /* set initial state of output pins */
232 #if defined(CFG_GPIO0_ODR)
233 out32(GPIO0_ODR, CFG_GPIO0_ODR); /* open-drain select */
235 out32(GPIO0_OSRH, CFG_GPIO0_OSRH); /* output select */
236 out32(GPIO0_OSRL, CFG_GPIO0_OSRL);
237 out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */
238 out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
239 out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */
240 out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
241 out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */
244 * Set EMAC noise filter bits
246 mtdcr(cpc0_epctl, CPC0_EPRCSR_E0NFE | CPC0_EPRCSR_E1NFE);
247 #endif /* CONFIG_405EP */
249 #if defined(CFG_440_GPIO_TABLE)
250 set_chip_gpio_configuration(&gpio_tab);
251 #endif /* CFG_440_GPIO_TABLE */
254 * External Bus Controller (EBC) Setup
256 #if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
257 #if (defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
258 defined(CONFIG_405EP) || defined(CONFIG_405))
260 * Move the next instructions into icache, since these modify the flash
261 * we are running from!
263 asm volatile(" bl 0f" ::: "lr");
264 asm volatile("0: mflr 3" ::: "r3");
265 asm volatile(" addi 4, 0, 14" ::: "r4");
266 asm volatile(" mtctr 4" ::: "ctr");
267 asm volatile("1: icbt 0, 3");
268 asm volatile(" addi 3, 3, 32" ::: "r3");
269 asm volatile(" bdnz 1b" ::: "ctr", "cr0");
270 asm volatile(" addis 3, 0, 0x0" ::: "r3");
271 asm volatile(" ori 3, 3, 0xA000" ::: "r3");
272 asm volatile(" mtctr 3" ::: "ctr");
273 asm volatile("2: bdnz 2b" ::: "ctr", "cr0");
276 mtebc(pb0ap, CFG_EBC_PB0AP);
277 mtebc(pb0cr, CFG_EBC_PB0CR);
280 #if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR) && !(CFG_INIT_DCACHE_CS == 1))
281 mtebc(pb1ap, CFG_EBC_PB1AP);
282 mtebc(pb1cr, CFG_EBC_PB1CR);
285 #if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR) && !(CFG_INIT_DCACHE_CS == 2))
286 mtebc(pb2ap, CFG_EBC_PB2AP);
287 mtebc(pb2cr, CFG_EBC_PB2CR);
290 #if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR) && !(CFG_INIT_DCACHE_CS == 3))
291 mtebc(pb3ap, CFG_EBC_PB3AP);
292 mtebc(pb3cr, CFG_EBC_PB3CR);
295 #if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR) && !(CFG_INIT_DCACHE_CS == 4))
296 mtebc(pb4ap, CFG_EBC_PB4AP);
297 mtebc(pb4cr, CFG_EBC_PB4CR);
300 #if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR) && !(CFG_INIT_DCACHE_CS == 5))
301 mtebc(pb5ap, CFG_EBC_PB5AP);
302 mtebc(pb5cr, CFG_EBC_PB5CR);
305 #if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR) && !(CFG_INIT_DCACHE_CS == 6))
306 mtebc(pb6ap, CFG_EBC_PB6AP);
307 mtebc(pb6cr, CFG_EBC_PB6CR);
310 #if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR) && !(CFG_INIT_DCACHE_CS == 7))
311 mtebc(pb7ap, CFG_EBC_PB7AP);
312 mtebc(pb7cr, CFG_EBC_PB7CR);
315 #if defined(CONFIG_WATCHDOG)
319 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
320 val |= 0xb8000000; /* generate system reset after 1.34 seconds */
322 val |= 0xf0000000; /* generate system reset after 2.684 seconds */
324 #if defined(CFG_4xx_RESET_TYPE)
325 val &= ~0x30000000; /* clear WRC bits */
326 val |= CFG_4xx_RESET_TYPE << 28; /* set board specific WRC type */
331 val |= 0x80000000; /* enable watchdog timer */
334 reset_4xx_watchdog();
335 #endif /* CONFIG_WATCHDOG */
339 * initialize higher level parts of CPU like time base and timers
341 int cpu_init_r (void)
343 #if defined(CONFIG_405GP) || defined(CONFIG_405EP)
346 #if defined(CONFIG_405GP)
347 uint pvr = get_pvr();
350 #ifdef CFG_INIT_DCACHE_CS
352 * Flush and invalidate dcache, then disable CS for temporary stack.
353 * Afterwards, this CS can be used for other purposes
355 dcache_disable(); /* flush and invalidate dcache */
357 mtebc(PBxCR, 0); /* disable CS for temporary stack */
359 #if (defined(PBxAP_VAL) && defined(PBxCR_VAL))
361 * Write new value into CS register
363 mtebc(PBxAP, PBxAP_VAL);
364 mtebc(PBxCR, PBxCR_VAL);
366 #endif /* CFG_INIT_DCACHE_CS */
369 * Write Ethernetaddress into on-chip register
372 reg |= bd->bi_enetaddr[0]; /* set high address */
374 reg |= bd->bi_enetaddr[1];
375 out32 (EMAC_IAH, reg);
378 reg |= bd->bi_enetaddr[2]; /* set low address */
380 reg |= bd->bi_enetaddr[3];
382 reg |= bd->bi_enetaddr[4];
384 reg |= bd->bi_enetaddr[5];
385 out32 (EMAC_IAL, reg);
387 #if defined(CONFIG_405GP)
389 * Set edge conditioning circuitry on PPC405GPr
390 * for compatibility to existing PPC405GP designs.
392 if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) {
393 mtdcr(ecr, 0x60606000);
395 #endif /* defined(CONFIG_405GP) */
396 #endif /* defined(CONFIG_405GP) || defined(CONFIG_405EP) */