1 /*-----------------------------------------------------------------------------+
3 | This source code has been made available to you by IBM on an AS-IS
4 | basis. Anyone receiving this source is licensed under IBM
5 | copyrights to use it in any way he or she deems fit, including
6 | copying it, modifying it, compiling it, and redistributing it either
7 | with or without modifications. No license under IBM patents or
8 | patent applications is to be implied by the copyright license.
10 | Any user of this software should understand that IBM cannot provide
11 | technical support for this software and will not be responsible for
12 | any consequences resulting from the use of this software.
14 | Any person who transfers this source code or any derivative work
15 | must include the IBM copyright notice, this paragraph, and the
16 | preceding two paragraphs in the transferred software.
18 | COPYRIGHT I B M CORPORATION 1995
19 | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 +-----------------------------------------------------------------------------*/
21 /*-----------------------------------------------------------------------------+
25 | Function: This module has utilities for accessing the MII PHY through
32 | Date Description of Change BY
33 | --------- --------------------- ---
34 | 05-May-99 Created MKW
35 | 01-Jul-99 Changed clock setting of sta_reg from 66Mhz to 50Mhz to
36 | better match OPB speed. Also modified delay times. JWB
37 | 29-Jul-99 Added Full duplex support MKW
38 | 24-Aug-99 Removed printf from dp83843_duplex() JWB
39 | 19-Jul-00 Ported to esd cpci405 sr
41 +-----------------------------------------------------------------------------*/
44 #include <asm/processor.h>
45 #include <ppc_asm.tmpl>
47 #include <405gp_enet.h>
51 #if defined(CONFIG_405GP) || defined(CONFIG_440) || defined(CONFIG_405EP)
54 /***********************************************************/
55 /* Dump out to the screen PHY regs */
56 /***********************************************************/
58 void miiphy_dump (unsigned char addr)
64 for (i = 0; i < 0x1A; i++) {
65 if (miiphy_read (addr, i, &data)) {
66 printf ("read error for reg %lx\n", i);
69 printf ("Phy reg %lx ==> %4x\n", i, data);
71 /* jump to the next set of regs */
79 /***********************************************************/
80 /* read a phy reg and return the value with a rc */
81 /***********************************************************/
83 int miiphy_read (unsigned char addr, unsigned char reg,
84 unsigned short *value)
86 unsigned long sta_reg; /* STA scratch area */
89 /* see if it is ready for 1000 nsec */
92 /* see if it is ready for sec */
93 while ((in32 (EMAC_STACR) & EMAC_STACR_OC) == 0) {
96 printf ("read err 1\n");
101 sta_reg = reg; /* reg address */
102 /* set clock (50Mhz) and read flags */
103 sta_reg = (sta_reg | EMAC_STACR_READ) & ~EMAC_STACR_CLK_100MHZ;
104 sta_reg = sta_reg | (addr << 5); /* Phy address */
106 out32 (EMAC_STACR, sta_reg);
107 #if 0 /* test-only */
108 printf ("a2: write: EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
111 sta_reg = in32 (EMAC_STACR);
113 while ((sta_reg & EMAC_STACR_OC) == 0) {
116 printf ("read err 2\n");
120 sta_reg = in32 (EMAC_STACR);
122 if ((sta_reg & EMAC_STACR_PHYE) != 0) {
123 printf ("read err 3\n");
124 printf ("a2: read: EMAC_STACR=0x%0lx, i=%d\n",
125 sta_reg, (int) i); /* test-only */
129 *value = *(short *) (&sta_reg);
136 /***********************************************************/
137 /* write a phy reg and return the value with a rc */
138 /***********************************************************/
140 int miiphy_write (unsigned char addr, unsigned char reg,
141 unsigned short value)
143 unsigned long sta_reg; /* STA scratch area */
146 /* see if it is ready for 1000 nsec */
149 while ((in32 (EMAC_STACR) & EMAC_STACR_OC) == 0) {
156 sta_reg = reg; /* reg address */
157 /* set clock (50Mhz) and read flags */
158 sta_reg = (sta_reg | EMAC_STACR_WRITE) & ~EMAC_STACR_CLK_100MHZ;
159 sta_reg = sta_reg | ((unsigned long) addr << 5); /* Phy address */
160 memcpy (&sta_reg, &value, 2); /* put in data */
162 out32 (EMAC_STACR, sta_reg);
164 /* wait for completion */
166 sta_reg = in32 (EMAC_STACR);
167 while ((sta_reg & EMAC_STACR_OC) == 0) {
172 sta_reg = in32 (EMAC_STACR);
175 if ((sta_reg & EMAC_STACR_PHYE) != 0)
181 #endif /* CONFIG_405GP */