3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
7 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
8 * Alex Zuepke <azu@sysgo.de>
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
35 #include <asm/arch/pxa-regs.h>
36 #include <asm/system.h>
39 DECLARE_GLOBAL_DATA_PTR;
45 * setup up stacks if necessary
48 IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
49 FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
54 int cleanup_before_linux (void)
57 * this function is called just before we call linux
58 * it prepares the processor for linux
60 * just disable everything that can disturb booting linux
65 disable_interrupts ();
67 /* turn off I-cache */
68 asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
70 asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
73 asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
78 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
80 printf ("resetting ...\n");
82 udelay (50000); /* wait 50 ms */
83 disable_interrupts ();
90 /* cache_bit must be either CR_I or CR_C */
91 static void cache_enable(uint32_t cache_bit)
95 reg = get_cr(); /* get control reg. */
97 set_cr(reg | cache_bit);
100 /* cache_bit must be either CR_I or CR_C */
101 static void cache_disable(uint32_t cache_bit)
107 set_cr(reg & ~cache_bit);
110 void icache_enable(void)
115 void icache_disable(void)
120 int icache_status(void)
122 return (get_cr() & CR_I) != 0;
125 /* we will never enable dcache, because we have to setup MMU first */
126 void dcache_enable (void)
131 void dcache_disable (void)
136 int dcache_status (void)
138 return 0; /* always off */
141 #ifndef CONFIG_CPU_MONAHANS
142 void set_GPIO_mode(int gpio_mode)
144 int gpio = gpio_mode & GPIO_MD_MASK_NR;
145 int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8;
148 if (gpio_mode & GPIO_MD_MASK_DIR)
150 GPDR(gpio) |= GPIO_bit(gpio);
154 GPDR(gpio) &= ~GPIO_bit(gpio);
156 gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2));
157 GAFR(gpio) = gafr | (fn << (((gpio) & 0xf)*2));
159 #endif /* CONFIG_CPU_MONAHANS */