2 * armboot - Startup Code for XScale
4 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
5 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
6 * Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
7 * Copyright (C) 2001 Alex Zuepke <azu@sysgo.de>
8 * Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net>
9 * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
10 * Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
36 ldr pc, _undefined_instruction
37 ldr pc, _software_interrupt
38 ldr pc, _prefetch_abort
44 _undefined_instruction: .word undefined_instruction
45 _software_interrupt: .word software_interrupt
46 _prefetch_abort: .word prefetch_abort
47 _data_abort: .word data_abort
48 _not_used: .word not_used
52 .balignl 16,0xdeadbeef
56 * Startup Code (reset vector)
58 * do important init only if we don't start from RAM!
59 * - relocate armboot to ram
61 * - jump to second stage
72 * These are defined in the board-specific linker script.
83 /* IRQ stack memory (calculated at run-time) */
84 .globl IRQ_STACK_START
88 /* IRQ stack memory (calculated at run-time) */
89 .globl FIQ_STACK_START
95 /****************************************************************************/
97 /* the actual reset code */
99 /****************************************************************************/
102 mrs r0,cpsr /* set the cpu to SVC32 mode */
103 bic r0,r0,#0x1f /* (superviser mode, M=10011) */
108 * we do sys-critical inits only at reboot,
109 * not when booting from ram!
111 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
112 bl cpu_init_crit /* we do sys-critical inits */
115 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
116 relocate: /* relocate U-Boot to RAM */
117 adr r0, _start /* r0 <- current position of code */
118 ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
119 cmp r0, r1 /* don't reloc during debug */
122 ldr r2, _armboot_start
124 sub r2, r3, r2 /* r2 <- size of armboot */
125 add r2, r0, r2 /* r2 <- source end address */
128 ldmia r0!, {r3-r10} /* copy from source address [r0] */
129 stmia r1!, {r3-r10} /* copy to target address [r1] */
130 cmp r0, r2 /* until source end addreee [r2] */
132 #endif /* CONFIG_SKIP_RELOCATE_UBOOT */
134 /* Set up the stack */
136 ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
137 sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
138 sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
139 #ifdef CONFIG_USE_IRQ
140 sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
142 sub sp, r0, #12 /* leave 3 words for abort-stack */
145 ldr r0, _bss_start /* find start of bss segment */
146 ldr r1, _bss_end /* stop here */
147 mov r2, #0x00000000 /* clear */
149 clbss_l:str r2, [r0] /* clear loop... */
154 ldr pc, _start_armboot
156 _start_armboot: .word start_armboot
159 /****************************************************************************/
161 /* CPU_init_critical registers */
163 /* - setup important registers */
164 /* - setup memory timing */
166 /****************************************************************************/
168 /* Interrupt-Controller base address */
169 IC_BASE: .word 0x40d00000
172 /* Reset-Controller */
173 RST_BASE: .word 0x40f00030
176 /* Operating System Timer */
177 OSTIMER_BASE: .word 0x40a00000
183 /* Clock Manager Registers */
185 CC_BASE: .word 0x41300000
187 cpuspeed: .word CFG_CPUSPEED
189 #error "You have to define CFG_CPUSPEED!!"
193 /* takes care the CP15 update has taken place */
195 mrc p15,0,\reg,c2,c0,0
204 #ifndef CONFIG_CPU_MONAHANS
210 /* Step 1 - Enable CP6 permission */
211 mrc p15, 0, r1, c15, c1, 0 @ read CPAR
213 mcr p15, 0, r1, c15, c1, 0
216 /* Step 2 - Mask ICMR & ICMR2 */
218 mcr p6, 0, r1, c1, c0, 0 @ ICMR
219 mcr p6, 0, r1, c7, c0, 0 @ ICMR2
222 #ifndef CONFIG_CPU_MONAHANS
225 /* set clock speed tbd@mk: required for monahans? */
230 mcr p14, 0, r0, c6, c0, 0
234 #endif /* CFG_CPUSPEED */
235 #endif /* CONFIG_CPU_MONAHANS */
239 * before relocating, we have to setup RAM timing
240 * because memory timing is board-dependend, you will
241 * find a lowlevel_init.S in your board directory.
247 /* Memory interfaces are working. Disable MMU and enable I-cache. */
248 /* mk: hmm, this is not in the monahans docs, leave it now but
249 * check here if it doesn't work :-) */
251 ldr r0, =0x2001 /* enable access to all coproc. */
252 mcr p15, 0, r0, c15, c1, 0
255 mcr p15, 0, r0, c7, c10, 4 /* drain the write & fill buffers */
258 mcr p15, 0, r0, c7, c7, 0 /* flush Icache, Dcache and BTB */
261 mcr p15, 0, r0, c8, c7, 0 /* flush instuction and data TLBs */
264 /* Enable the Icache */
266 mrc p15, 0, r0, c1, c0, 0
268 mcr p15, 0, r0, c1, c0, 0
274 /****************************************************************************/
276 /* Interrupt handling */
278 /****************************************************************************/
280 /* IRQ stack frame */
282 #define S_FRAME_SIZE 72
304 #define MODE_SVC 0x13
306 /* use bad_save_user_regs for abort/prefetch/undef/swi ... */
308 .macro bad_save_user_regs
309 sub sp, sp, #S_FRAME_SIZE
310 stmia sp, {r0 - r12} /* Calling r0-r12 */
313 ldr r2, _armboot_start
314 sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
315 sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
316 ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */
317 add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */
321 stmia r5, {r0 - r4} /* save sp_SVC, lr_SVC, pc, cpsr, old_r */
326 /* use irq_save_user_regs / irq_restore_user_regs for */
327 /* IRQ/FIQ handling */
329 .macro irq_save_user_regs
330 sub sp, sp, #S_FRAME_SIZE
331 stmia sp, {r0 - r12} /* Calling r0-r12 */
333 stmdb r8, {sp, lr}^ /* Calling SP, LR */
334 str lr, [r8, #0] /* Save calling PC */
336 str r6, [r8, #4] /* Save CPSR */
337 str r0, [r8, #8] /* Save OLD_R0 */
341 .macro irq_restore_user_regs
342 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
344 ldr lr, [sp, #S_PC] @ Get PC
345 add sp, sp, #S_FRAME_SIZE
346 subs pc, lr, #4 @ return & move spsr_svc into cpsr
350 ldr r13, _armboot_start @ setup our mode stack
351 sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
352 sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
354 str lr, [r13] @ save caller lr / spsr
358 mov r13, #MODE_SVC @ prepare SVC-Mode
364 .macro get_irq_stack @ setup IRQ stack
365 ldr sp, IRQ_STACK_START
368 .macro get_fiq_stack @ setup FIQ stack
369 ldr sp, FIQ_STACK_START
373 /****************************************************************************/
375 /* exception handlers */
377 /****************************************************************************/
380 undefined_instruction:
383 bl do_undefined_instruction
389 bl do_software_interrupt
409 #ifdef CONFIG_USE_IRQ
416 irq_restore_user_regs
421 irq_save_user_regs /* someone ought to write a more */
422 bl do_fiq /* effiction fiq_save_user_regs */
423 irq_restore_user_regs
441 /****************************************************************************/
443 /* Reset function: the PXA250 doesn't have a reset function, so we have to */
444 /* perform a watchdog timeout for a soft reset. */
446 /****************************************************************************/
451 /* FIXME: this code is PXA250 specific. How is this handled on */
452 /* other XScale processors? */
456 /* We set OWE:WME (watchdog enable) and wait until timeout happens */
460 orr r1, r1, #0x0001 /* bit0: WME */
463 /* OS timer does only wrap every 1165 seconds, so we have to set */
464 /* the match register as well. */
466 ldr r1, [r0, #OSCR] /* read OS timer */
467 add r1, r1, #0x800 /* let OSMR3 match after */
468 add r1, r1, #0x800 /* 4096*(1/3.6864MHz)=1ms */