2 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
3 * Copyright (C) 2007-2009 DENX Software Engineering
5 * SPDX-License-Identifier: GPL-2.0+
7 * Derived from the MPC83xx code.
12 #include <asm/mpc512x.h>
13 #include <asm/processor.h>
15 DECLARE_GLOBAL_DATA_PTR;
18 * Set up the memory map, initialize registers,
20 void cpu_init_f (volatile immap_t * im)
24 /* Pointer is writable since we allocated a register for it */
25 gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
27 /* Clear initial global data */
28 memset ((void *) gd, 0, sizeof (gd_t));
30 /* Local Window and chip select configuration */
31 #if defined(CONFIG_SYS_CS0_START) && defined(CONFIG_SYS_CS0_SIZE)
32 out_be32(&im->sysconf.lpcs0aw,
33 CSAW_START(CONFIG_SYS_CS0_START) |
34 CSAW_STOP(CONFIG_SYS_CS0_START, CONFIG_SYS_CS0_SIZE));
35 sync_law(&im->sysconf.lpcs0aw);
37 #if defined(CONFIG_SYS_CS0_CFG)
38 out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG);
41 #if defined(CONFIG_SYS_CS1_START) && defined(CONFIG_SYS_CS1_SIZE)
42 out_be32(&im->sysconf.lpcs1aw,
43 CSAW_START(CONFIG_SYS_CS1_START) |
44 CSAW_STOP(CONFIG_SYS_CS1_START, CONFIG_SYS_CS1_SIZE));
45 sync_law(&im->sysconf.lpcs1aw);
47 #if defined(CONFIG_SYS_CS1_CFG)
48 out_be32(&im->lpc.cs_cfg[1], CONFIG_SYS_CS1_CFG);
51 #if defined(CONFIG_SYS_CS2_START) && (defined CONFIG_SYS_CS2_SIZE)
52 out_be32(&im->sysconf.lpcs2aw,
53 CSAW_START(CONFIG_SYS_CS2_START) |
54 CSAW_STOP(CONFIG_SYS_CS2_START, CONFIG_SYS_CS2_SIZE));
55 sync_law(&im->sysconf.lpcs2aw);
57 #if defined(CONFIG_SYS_CS2_CFG)
58 out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG);
61 #if defined(CONFIG_SYS_CS3_START) && defined(CONFIG_SYS_CS3_SIZE)
62 out_be32(&im->sysconf.lpcs3aw,
63 CSAW_START(CONFIG_SYS_CS3_START) |
64 CSAW_STOP(CONFIG_SYS_CS3_START, CONFIG_SYS_CS3_SIZE));
65 sync_law(&im->sysconf.lpcs3aw);
67 #if defined(CONFIG_SYS_CS3_CFG)
68 out_be32(&im->lpc.cs_cfg[3], CONFIG_SYS_CS3_CFG);
71 #if defined(CONFIG_SYS_CS4_START) && defined(CONFIG_SYS_CS4_SIZE)
72 out_be32(&im->sysconf.lpcs4aw,
73 CSAW_START(CONFIG_SYS_CS4_START) |
74 CSAW_STOP(CONFIG_SYS_CS4_START, CONFIG_SYS_CS4_SIZE));
75 sync_law(&im->sysconf.lpcs4aw);
77 #if defined(CONFIG_SYS_CS4_CFG)
78 out_be32(&im->lpc.cs_cfg[4], CONFIG_SYS_CS4_CFG);
81 #if defined(CONFIG_SYS_CS5_START) && defined(CONFIG_SYS_CS5_SIZE)
82 out_be32(&im->sysconf.lpcs5aw,
83 CSAW_START(CONFIG_SYS_CS5_START) |
84 CSAW_STOP(CONFIG_SYS_CS5_START, CONFIG_SYS_CS5_SIZE));
85 sync_law(&im->sysconf.lpcs5aw);
87 #if defined(CONFIG_SYS_CS5_CFG)
88 out_be32(&im->lpc.cs_cfg[5], CONFIG_SYS_CS5_CFG);
91 #if defined(CONFIG_SYS_CS6_START) && defined(CONFIG_SYS_CS6_SIZE)
92 out_be32(&im->sysconf.lpcs6aw,
93 CSAW_START(CONFIG_SYS_CS6_START) |
94 CSAW_STOP(CONFIG_SYS_CS6_START, CONFIG_SYS_CS6_SIZE));
95 sync_law(&im->sysconf.lpcs6aw);
97 #if defined(CONFIG_SYS_CS6_CFG)
98 out_be32(&im->lpc.cs_cfg[6], CONFIG_SYS_CS6_CFG);
101 #if defined(CONFIG_SYS_CS7_START) && defined(CONFIG_SYS_CS7_SIZE)
102 out_be32(&im->sysconf.lpcs7aw,
103 CSAW_START(CONFIG_SYS_CS7_START) |
104 CSAW_STOP(CONFIG_SYS_CS7_START, CONFIG_SYS_CS7_SIZE));
105 sync_law(&im->sysconf.lpcs7aw);
107 #if defined(CONFIG_SYS_CS7_CFG)
108 out_be32(&im->lpc.cs_cfg[7], CONFIG_SYS_CS7_CFG);
111 #if defined CONFIG_SYS_CS_ALETIMING
112 if (SVR_MJREV(in_be32(&im->sysconf.spridr)) >= 2)
113 out_be32(&im->lpc.altr, CONFIG_SYS_CS_ALETIMING);
115 #if defined CONFIG_SYS_CS_BURST
116 out_be32(&im->lpc.cs_bcr, CONFIG_SYS_CS_BURST);
118 #if defined CONFIG_SYS_CS_DEADCYCLE
119 out_be32(&im->lpc.cs_dccr, CONFIG_SYS_CS_DEADCYCLE);
121 #if defined CONFIG_SYS_CS_HOLDCYCLE
122 out_be32(&im->lpc.cs_hccr, CONFIG_SYS_CS_HOLDCYCLE);
125 /* system performance tweaking */
127 #ifdef CONFIG_SYS_ACR_PIPE_DEP
128 /* Arbiter pipeline depth */
129 out_be32(&im->arbiter.acr,
130 (im->arbiter.acr & ~ACR_PIPE_DEP) |
131 (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT)
135 #ifdef CONFIG_SYS_ACR_RPTCNT
136 /* Arbiter repeat count */
137 out_be32(im->arbiter.acr,
138 (im->arbiter.acr & ~(ACR_RPTCNT)) |
139 (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT)
143 /* RSR - Reset Status Register - clear all status */
144 gd->arch.reset_status = im->reset.rsr;
145 out_be32(&im->reset.rsr, ~RSR_RES);
148 * RMR - Reset Mode Register - enable checkstop reset
150 out_be32(&im->reset.rmr, RMR_CSRE & (1 << RMR_CSRE_SHIFT));
152 /* Set IPS-CSB divider: IPS = 1/2 CSB */
153 ips_div = in_be32(&im->clk.scfr[0]);
154 ips_div &= ~(SCFR1_IPS_DIV_MASK);
155 ips_div |= SCFR1_IPS_DIV << SCFR1_IPS_DIV_SHIFT;
156 out_be32(&im->clk.scfr[0], ips_div);
159 clrsetbits_be32(&im->clk.scfr[0], SCFR1_LPC_DIV_MASK,
160 SCFR1_LPC_DIV << SCFR1_LPC_DIV_SHIFT);
164 clrsetbits_be32(&im->clk.scfr[0], SCFR1_NFC_DIV_MASK,
165 SCFR1_NFC_DIV << SCFR1_NFC_DIV_SHIFT);
169 clrsetbits_be32(&im->clk.scfr[0], SCFR1_DIU_DIV_MASK,
170 SCFR1_DIU_DIV << SCFR1_DIU_DIV_SHIFT);
174 * Enable Time Base/Decrementer
176 * NOTICE: TB needs to be enabled as early as possible in order to
177 * have udelay() working; if not enabled, usually leads to a hang, like
178 * during FLASH chip identification etc.
180 setbits_be32(&im->sysconf.spcr, SPCR_TBEN);
185 out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN);
186 out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN);
187 #if defined(CONFIG_FSL_IIM) || defined(CONFIG_CMD_FUSE)
188 setbits_be32(&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN);
192 int cpu_init_r (void)