1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2014 Freescale Semiconductor, Inc.
10 #include <fsl_ddr_sdram.h>
11 #include <fsl_ddr_dimm_params.h>
12 #include <asm/fsl_law.h>
15 DECLARE_GLOBAL_DATA_PTR;
17 void fsl_ddr_board_options(memctl_options_t *popts,
19 unsigned int ctrl_num)
21 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
25 printf("Not supported controller number %d\n", ctrl_num);
32 * we use identical timing for all slots. If needed, change the code
33 * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
35 if (popts->registered_dimm_en)
41 /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
42 * freqency and n_banks specified in board_specific_parameters table.
44 ddr_freq = get_ddr_freq(0) / 1000000;
45 while (pbsp->datarate_mhz_high) {
46 if (pbsp->n_ranks == pdimm->n_ranks &&
47 (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
48 if (ddr_freq <= pbsp->datarate_mhz_high) {
49 popts->clk_adjust = pbsp->clk_adjust;
50 popts->wrlvl_start = pbsp->wrlvl_start;
51 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
52 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
61 printf("Error: board specific timing not found for data\n"
63 "Trying to use the highest speed (%u) parameters\n",
64 ddr_freq, pbsp_highest->datarate_mhz_high);
65 popts->clk_adjust = pbsp_highest->clk_adjust;
66 popts->wrlvl_start = pbsp_highest->wrlvl_start;
67 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
68 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
70 panic("DIMM is not supported by this board");
73 debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
74 "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x,\n"
75 "wrlvl_ctrl_3 0x%x\n",
76 pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
77 pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
81 * Factors to consider for half-strength driver enable:
82 * - number of DIMMs installed
84 popts->half_strength_driver_enable = 0;
86 * Write leveling override
88 popts->wrlvl_override = 1;
89 popts->wrlvl_sample = 0xf;
92 * Rtt and Rtt_WR override
94 popts->rtt_override = 0;
96 /* Enable ZQ calibration */
99 /* DHC_EN =1, ODT = 75 Ohm */
100 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
101 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
103 /* optimize cpo for erratum A-009942 */
104 popts->cpo_sample = 0x64;
109 phys_size_t dram_size;
111 puts("Initializing....using SPD\n");
113 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
114 dram_size = fsl_ddr_sdram();
116 /* DDR has been initialised by first stage boot loader */
117 dram_size = fsl_ddr_sdram_size();
119 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
120 dram_size *= 0x100000;
122 gd->ram_size = dram_size;