3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
8 * (C) Copyright 2005-2009
9 * Modified for InterControl digsyMTC MPC5200 board by
10 * Frank Bodammer, GCD Hard- & Software GmbH,
11 * frank.bodammer@gcd-solutions.de
14 * Grzegorz Bernacki, Semihalf, gjb@semihalf.com
16 * See file CREDITS for list of people who contributed to this
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License as
21 * published by the Free Software Foundation; either version 2 of
22 * the License, or (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
39 #include <asm/processor.h>
42 #if defined(CONFIG_DIGSY_REV5)
43 #include "is45s16800a2.h"
44 #include <mtd/cfi_flash.h>
47 #include "is42s16800a-7t.h"
50 #include <fdt_support.h>
52 DECLARE_GLOBAL_DATA_PTR;
54 extern int usb_cpu_init(void);
56 #if defined(CONFIG_DIGSY_REV5)
58 * The M29W128GH needs a specail reset command function,
59 * details see the doc/README.cfi file
61 void flash_cmd_reset(flash_info_t *info)
63 flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
67 #ifndef CONFIG_SYS_RAMBOOT
68 static void sdram_start(int hi_addr)
70 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
71 long control = SDRAM_CONTROL | hi_addr_bit;
73 /* unlock mode register */
74 out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000);
76 /* precharge all banks */
77 out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
80 out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004);
82 /* set mode register */
83 out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
85 /* normal operation */
86 out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
91 * ATTENTION: Although partially referenced initdram does NOT make real use
92 * use of CONFIG_SYS_SDRAM_BASE. The code does not work if
93 * CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
96 phys_size_t initdram(int board_type)
101 #ifndef CONFIG_SYS_RAMBOOT
104 /* setup SDRAM chip selects */
105 out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001C); /* 512MB at 0x0 */
106 out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */
108 /* setup config registers */
109 out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
110 out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
112 /* find RAM size using SDRAM CS0 only */
114 test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
116 test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
124 /* memory smaller than 1MB is impossible */
125 if (dramsize < (1 << 20))
128 /* set SDRAM CS0 size according to the amount of RAM found */
130 out_be32((void *)MPC5XXX_SDRAM_CS0CFG,
131 (0x13 + __builtin_ffs(dramsize >> 20) - 1));
133 out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */
136 /* let SDRAM CS1 start right after CS0 */
137 out_be32((void *)MPC5XXX_SDRAM_CS1CFG, dramsize + 0x0000001C);
139 /* find RAM size using SDRAM CS1 only */
140 test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize),
144 /* memory smaller than 1MB is impossible */
145 if (dramsize2 < (1 << 20))
148 /* set SDRAM CS1 size according to the amount of RAM found */
150 out_be32((void *)MPC5XXX_SDRAM_CS1CFG, (dramsize |
151 (0x13 + __builtin_ffs(dramsize2 >> 20) - 1)));
153 out_be32((void *)MPC5XXX_SDRAM_CS1CFG, dramsize); /* disabled */
156 #else /* CONFIG_SYS_RAMBOOT */
158 /* retrieve size of memory connected to SDRAM CS0 */
159 dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
160 if (dramsize >= 0x13)
161 dramsize = (1 << (dramsize - 0x13)) << 20;
165 /* retrieve size of memory connected to SDRAM CS1 */
166 dramsize2 = in_be32((void *)MPC5XXX_SDRAM_CS1CFG) & 0xFF;
167 if (dramsize2 >= 0x13)
168 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
172 #endif /* CONFIG_SYS_RAMBOOT */
175 * On MPC5200B we need to set the special configuration delay in the
176 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
177 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
179 * "The SDelay should be written to a value of 0x00000004. It is
180 * required to account for changes caused by normal wafer processing
185 if ((SVR_MJREV(svr) >= 2) &&
186 (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
187 out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
189 return dramsize + dramsize2;
195 int i = getenv_f("serial#", buf, sizeof(buf));
197 puts ("Board: InterControl digsyMTC");
198 #if defined(CONFIG_DIGSY_REV5)
210 int board_early_init_r(void)
212 #ifdef CONFIG_MPC52XX_SPI
213 struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt*)MPC5XXX_GPT;
216 * Now, when we are in RAM, enable flash write access for detection
217 * process. Note that CS_BOOT cannot be cleared when executing in
220 /* disable CS_BOOT */
221 clrbits_be32((void *)MPC5XXX_ADDECR, (1 << 25));
223 setbits_be32((void *)MPC5XXX_ADDECR, (1 << 17));
225 setbits_be32((void *)MPC5XXX_ADDECR, (1 << 16));
227 #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
228 /* Low level USB init, required for proper kernel operation */
231 #ifdef CONFIG_MPC52XX_SPI
232 /* GPT 6 Output Enable */
233 out_be32(&gpt[6].emsr, 0x00000034);
234 /* GPT 7 Output Enable */
235 out_be32(&gpt[7].emsr, 0x00000034);
241 void board_get_enetaddr (uchar * enet)
244 ushort addr_of_eth_addr = 0;
246 ushort len_sys_cfg = 0;
248 /* check identification word */
249 eeprom_read(EEPROM_ADDR, EEPROM_ADDR_IDENT, (uchar *)&read, 2);
250 if (read != EEPROM_IDENT)
253 /* calculate offset of config area */
254 eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYS, (uchar *)&len_sys, 2);
255 eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYSCFG,
256 (uchar *)&len_sys_cfg, 2);
257 addr_of_eth_addr = (len_sys + len_sys_cfg + EEPROM_ADDR_ETHADDR) << 1;
258 if (addr_of_eth_addr >= EEPROM_LEN)
261 eeprom_read(EEPROM_ADDR, addr_of_eth_addr, enet, 6);
264 int misc_init_r(void)
268 if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
269 board_get_enetaddr(enetaddr);
270 eth_setenv_enetaddr("ethaddr", enetaddr);
277 static struct pci_controller hose;
279 extern void pci_mpc5xxx_init(struct pci_controller *);
281 void pci_init_board(void)
283 pci_mpc5xxx_init(&hose);
287 #ifdef CONFIG_CMD_IDE
289 #ifdef CONFIG_IDE_RESET
291 void init_ide_reset(void)
293 debug ("init_ide_reset\n");
295 /* set gpio output value to 1 */
296 setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
297 /* open drain output */
298 setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
299 /* direction output */
300 setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
302 setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
306 void ide_set_reset(int idereset)
308 debug ("ide_reset(%d)\n", idereset);
310 /* set gpio output value to 0 */
311 clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
312 /* open drain output */
313 setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
314 /* direction output */
315 setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
317 setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
321 /* set gpio output value to 1 */
322 setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
323 /* open drain output */
324 setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
325 /* direction output */
326 setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
328 setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
330 #endif /* CONFIG_IDE_RESET */
331 #endif /* CONFIG_CMD_IDE */
333 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
334 static void ft_delete_node(void *fdt, const char *compat)
339 off = fdt_node_offset_by_compatible(fdt, -1, compat);
341 printf("Could not find %s node.\n", compat);
345 ret = fdt_del_node(fdt, off);
347 printf("Could not delete %s node.\n", compat);
349 #if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
350 static void ft_adapt_flash_base(void *blob)
352 flash_info_t *dev = &flash_info[0];
354 struct fdt_property *prop;
358 off = fdt_node_offset_by_compatible(blob, -1, "fsl,mpc5200b-lpb");
360 printf("Could not find fsl,mpc5200b-lpb node.\n");
364 /* found compatible property */
365 prop = fdt_get_property_w(blob, off, "ranges", &len);
367 reg = reg2 = (u32 *)&prop->data[0];
369 reg[2] = dev->start[0];
371 fdt_setprop(blob, off, "ranges", reg2, len);
373 printf("Could not find ranges\n");
376 extern ulong flash_get_size (phys_addr_t base, int banknum);
378 /* Update the Flash Baseaddr settings */
379 int update_flash_size (int flash_size)
381 volatile struct mpc5xxx_mmap_ctl *mm =
382 (struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
386 unsigned long base = 0x0;
387 u32 *cs_reg = (u32 *)&mm->cs0_start;
389 for (i = 0; i < 2; i++) {
390 dev = &flash_info[i];
393 /* calculate new base addr for this chipselect */
395 out_be32(cs_reg, START_REG(base));
397 out_be32(cs_reg, STOP_REG(base, dev->size));
399 /* recalculate the sectoraddr in the cfi driver */
400 size += flash_get_size(base, i);
403 flash_protect_default();
404 gd->bd->bi_flashstart = base;
407 #endif /* defined(CONFIG_SYS_UPDATE_FLASH_SIZE) */
409 void ft_board_setup(void *blob, bd_t *bd)
411 int phy_addr = CONFIG_PHY_ADDR;
412 char eth_path[] = "/soc5200@f0000000/mdio@3000/ethernet-phy@0";
414 ft_cpu_setup(blob, bd);
416 * There are 2 RTC nodes in the DTS, so remove
417 * the unneeded node here.
419 #if defined(CONFIG_DIGSY_REV5)
420 ft_delete_node(blob, "dallas,ds1339");
422 ft_delete_node(blob, "mc,rv3029c2");
424 #if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
425 #ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
426 /* Update reg property in all nor flash nodes too */
427 fdt_fixup_nor_flash_size(blob);
429 ft_adapt_flash_base(blob);
431 /* fix up the phy address */
432 do_fixup_by_path(blob, eth_path, "reg", &phy_addr, sizeof(int), 0);
434 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */