1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
7 * OpenOCD: (openocd). OpenOCD User's Guide
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009-2010 David Brownell
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
40 @titlefont{@emph{Open On-Chip Debugger:}}
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
47 @vskip 0pt plus 1filll
56 @top OpenOCD User's Guide
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About Jim-Tcl:: About Jim-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Server Configuration:: Server Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * Flash Programming:: Flash Programming
76 * PLD/FPGA Commands:: PLD/FPGA Commands
77 * General Commands:: General Commands
78 * Architecture and Core Commands:: Architecture and Core Commands
79 * JTAG Commands:: JTAG Commands
80 * Boundary Scan Commands:: Boundary Scan Commands
81 * Utility Commands:: Utility Commands
83 * GDB and OpenOCD:: Using GDB and OpenOCD
84 * Tcl Scripting API:: Tcl Scripting API
85 * FAQ:: Frequently Asked Questions
86 * Tcl Crash Course:: Tcl Crash Course
87 * License:: GNU Free Documentation License
89 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
90 @comment case issue with ``Index.html'' and ``index.html''
91 @comment Occurs when creating ``--html --no-split'' output
92 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
93 * OpenOCD Concept Index:: Concept Index
94 * Command and Driver Index:: Command and Driver Index
101 OpenOCD was created by Dominic Rath as part of a 2005 diploma thesis written
102 at the University of Applied Sciences Augsburg (@uref{http://www.hs-augsburg.de}).
103 Since that time, the project has grown into an active open-source project,
104 supported by a diverse community of software and hardware developers from
107 @section What is OpenOCD?
111 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
112 in-system programming and boundary-scan testing for embedded target
115 It does so with the assistance of a @dfn{debug adapter}, which is
116 a small hardware module which helps provide the right kind of
117 electrical signaling to the target being debugged. These are
118 required since the debug host (on which OpenOCD runs) won't
119 usually have native support for such signaling, or the connector
120 needed to hook up to the target.
122 Such debug adapters support one or more @dfn{transport} protocols,
123 each of which involves different electrical signaling (and uses
124 different messaging protocols on top of that signaling). There
125 are many types of debug adapter, and little uniformity in what
126 they are called. (There are also product naming differences.)
128 These adapters are sometimes packaged as discrete dongles, which
129 may generically be called @dfn{hardware interface dongles}.
130 Some development boards also integrate them directly, which may
131 let the development board connect directly to the debug
132 host over USB (and sometimes also to power it over USB).
134 For example, a @dfn{JTAG Adapter} supports JTAG
135 signaling, and is used to communicate
136 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
137 A @dfn{TAP} is a ``Test Access Port'', a module which processes
138 special instructions and data. TAPs are daisy-chained within and
139 between chips and boards. JTAG supports debugging and boundary
142 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
143 signaling to communicate with some newer ARM cores, as well as debug
144 adapters which support both JTAG and SWD transports. SWD supports only
145 debugging, whereas JTAG also supports boundary scan operations.
147 For some chips, there are also @dfn{Programming Adapters} supporting
148 special transports used only to write code to flash memory, without
149 support for on-chip debugging or boundary scan.
150 (At this writing, OpenOCD does not support such non-debug adapters.)
153 @b{Dongles:} OpenOCD currently supports many types of hardware dongles:
154 USB-based, parallel port-based, and other standalone boxes that run
155 OpenOCD internally. @xref{Debug Adapter Hardware}.
157 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
158 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x), Cortex-M3
159 (Stellaris LM3, ST STM32 and Energy Micro EFM32) and Intel Quark (x10xx)
160 based cores to be debugged via the GDB protocol.
162 @b{Flash Programming:} Flash writing is supported for external
163 CFI-compatible NOR flashes (Intel and AMD/Spansion command set) and several
164 internal flashes (LPC1700, LPC1800, LPC2000, LPC4300, AT91SAM7, AT91SAM3U,
165 STR7x, STR9x, LM3, STM32x and EFM32). Preliminary support for various NAND flash
166 controllers (LPC3180, Orion, S3C24xx, more) is included.
168 @section OpenOCD Web Site
170 The OpenOCD web site provides the latest public news from the community:
172 @uref{http://openocd.org/}
174 @section Latest User's Guide:
176 The user's guide you are now reading may not be the latest one
177 available. A version for more recent code may be available.
178 Its HTML form is published regularly at:
180 @uref{http://openocd.org/doc/html/index.html}
182 PDF form is likewise published at:
184 @uref{http://openocd.org/doc/pdf/openocd.pdf}
186 @section OpenOCD User's Forum
188 There is an OpenOCD forum (phpBB) hosted by SparkFun,
189 which might be helpful to you. Note that if you want
190 anything to come to the attention of developers, you
191 should post it to the OpenOCD Developer Mailing List
192 instead of this forum.
194 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
196 @section OpenOCD User's Mailing List
198 The OpenOCD User Mailing List provides the primary means of
199 communication between users:
201 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-user}
205 Support can also be found on irc:
206 @uref{irc://irc.freenode.net/openocd}
209 @chapter OpenOCD Developer Resources
212 If you are interested in improving the state of OpenOCD's debugging and
213 testing support, new contributions will be welcome. Motivated developers
214 can produce new target, flash or interface drivers, improve the
215 documentation, as well as more conventional bug fixes and enhancements.
217 The resources in this chapter are available for developers wishing to explore
218 or expand the OpenOCD source code.
220 @section OpenOCD Git Repository
222 During the 0.3.x release cycle, OpenOCD switched from Subversion to
223 a Git repository hosted at SourceForge. The repository URL is:
225 @uref{git://git.code.sf.net/p/openocd/code}
229 @uref{http://git.code.sf.net/p/openocd/code}
231 You may prefer to use a mirror and the HTTP protocol:
233 @uref{http://repo.or.cz/r/openocd.git}
235 With standard Git tools, use @command{git clone} to initialize
236 a local repository, and @command{git pull} to update it.
237 There are also gitweb pages letting you browse the repository
238 with a web browser, or download arbitrary snapshots without
239 needing a Git client:
241 @uref{http://repo.or.cz/w/openocd.git}
243 The @file{README} file contains the instructions for building the project
244 from the repository or a snapshot.
246 Developers that want to contribute patches to the OpenOCD system are
247 @b{strongly} encouraged to work against mainline.
248 Patches created against older versions may require additional
249 work from their submitter in order to be updated for newer releases.
251 @section Doxygen Developer Manual
253 During the 0.2.x release cycle, the OpenOCD project began
254 providing a Doxygen reference manual. This document contains more
255 technical information about the software internals, development
256 processes, and similar documentation:
258 @uref{http://openocd.org/doc/doxygen/html/index.html}
260 This document is a work-in-progress, but contributions would be welcome
261 to fill in the gaps. All of the source files are provided in-tree,
262 listed in the Doxyfile configuration at the top of the source tree.
264 @section Gerrit Review System
266 All changes in the OpenOCD Git repository go through the web-based Gerrit
269 @uref{http://openocd.zylin.com/}
271 After a one-time registration and repository setup, anyone can push commits
272 from their local Git repository directly into Gerrit.
273 All users and developers are encouraged to review, test, discuss and vote
274 for changes in Gerrit. The feedback provides the basis for a maintainer to
275 eventually submit the change to the main Git repository.
277 The @file{HACKING} file, also available as the Patch Guide in the Doxygen
278 Developer Manual, contains basic information about how to connect a
279 repository to Gerrit, prepare and push patches. Patch authors are expected to
280 maintain their changes while they're in Gerrit, respond to feedback and if
281 necessary rework and push improved versions of the change.
283 @section OpenOCD Developer Mailing List
285 The OpenOCD Developer Mailing List provides the primary means of
286 communication between developers:
288 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-devel}
290 @section OpenOCD Bug Tracker
292 The OpenOCD Bug Tracker is hosted on SourceForge:
294 @uref{http://bugs.openocd.org/}
297 @node Debug Adapter Hardware
298 @chapter Debug Adapter Hardware
307 Defined: @b{dongle}: A small device that plugs into a computer and serves as
308 an adapter .... [snip]
310 In the OpenOCD case, this generally refers to @b{a small adapter} that
311 attaches to your computer via USB or the parallel port. One
312 exception is the Ultimate Solutions ZY1000, packaged as a small box you
313 attach via an ethernet cable. The ZY1000 has the advantage that it does not
314 require any drivers to be installed on the developer PC. It also has
315 a built in web interface. It supports RTCK/RCLK or adaptive clocking
316 and has a built-in relay to power cycle targets remotely.
319 @section Choosing a Dongle
321 There are several things you should keep in mind when choosing a dongle.
324 @item @b{Transport} Does it support the kind of communication that you need?
325 OpenOCD focusses mostly on JTAG. Your version may also support
326 other ways to communicate with target devices.
327 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
328 Does your dongle support it? You might need a level converter.
329 @item @b{Pinout} What pinout does your target board use?
330 Does your dongle support it? You may be able to use jumper
331 wires, or an "octopus" connector, to convert pinouts.
332 @item @b{Connection} Does your computer have the USB, parallel, or
333 Ethernet port needed?
334 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
335 RTCK support (also known as ``adaptive clocking'')?
338 @section Stand-alone JTAG Probe
340 The ZY1000 from Ultimate Solutions is technically not a dongle but a
341 stand-alone JTAG probe that, unlike most dongles, doesn't require any drivers
342 running on the developer's host computer.
343 Once installed on a network using DHCP or a static IP assignment, users can
344 access the ZY1000 probe locally or remotely from any host with access to the
345 IP address assigned to the probe.
346 The ZY1000 provides an intuitive web interface with direct access to the
348 Users may also run a GDBSERVER directly on the ZY1000 to take full advantage
349 of GCC & GDB to debug any distribution of embedded Linux or NetBSD running on
351 The ZY1000 supports RTCK & RCLK or adaptive clocking and has a built-in relay
352 to power cycle the target remotely.
354 For more information, visit:
356 @b{ZY1000} See: @url{http://www.ultsol.com/index.php/component/content/article/8/210-zylin-zy1000-main}
358 @section USB FT2232 Based
360 There are many USB JTAG dongles on the market, many of them based
361 on a chip from ``Future Technology Devices International'' (FTDI)
362 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
363 See: @url{http://www.ftdichip.com} for more information.
364 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
365 chips started to become available in JTAG adapters. Around 2012, a new
366 variant appeared - FT232H - this is a single-channel version of FT2232H.
367 (Adapters using those high speed FT2232H or FT232H chips may support adaptive
370 The FT2232 chips are flexible enough to support some other
371 transport options, such as SWD or the SPI variants used to
372 program some chips. They have two communications channels,
373 and one can be used for a UART adapter at the same time the
374 other one is used to provide a debug adapter.
376 Also, some development boards integrate an FT2232 chip to serve as
377 a built-in low-cost debug adapter and USB-to-serial solution.
381 @* Link @url{http://elk.informatik.fh-augsburg.de/hhweb/doc/openocd/usbjtag/usbjtag.html}
383 @* See: @url{http://www.amontec.com/jtagkey.shtml}
385 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
387 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
389 @* See: @url{http://www.signalyzer.com}
390 @item @b{Stellaris Eval Boards}
391 @* See: @url{http://www.ti.com} - The Stellaris eval boards
392 bundle FT2232-based JTAG and SWD support, which can be used to debug
393 the Stellaris chips. Using separate JTAG adapters is optional.
394 These boards can also be used in a "pass through" mode as JTAG adapters
395 to other target boards, disabling the Stellaris chip.
396 @item @b{TI/Luminary ICDI}
397 @* See: @url{http://www.ti.com} - TI/Luminary In-Circuit Debug
398 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
399 Evaluation Kits. Like the non-detachable FT2232 support on the other
400 Stellaris eval boards, they can be used to debug other target boards.
401 @item @b{olimex-jtag}
402 @* See: @url{http://www.olimex.com}
403 @item @b{Flyswatter/Flyswatter2}
404 @* See: @url{http://www.tincantools.com}
405 @item @b{turtelizer2}
407 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
408 @url{http://www.ethernut.de}
410 @* Link: @url{http://www.hitex.com/index.php?id=383}
412 @* Link @url{http://www.hitex.com/stm32-stick}
413 @item @b{axm0432_jtag}
414 @* Axiom AXM-0432 Link @url{http://www.axman.com} - NOTE: This JTAG does not appear
415 to be available anymore as of April 2012.
417 @* Link @url{http://www.hitex.com/index.php?id=cortino}
418 @item @b{dlp-usb1232h}
419 @* Link @url{http://www.dlpdesign.com/usb/usb1232h.shtml}
420 @item @b{digilent-hs1}
421 @* Link @url{http://www.digilentinc.com/Products/Detail.cfm?Prod=JTAG-HS1}
423 @* Link @url{http://code.google.com/p/opendous/wiki/JTAG} FT2232H-based
425 @item @b{JTAG-lock-pick Tiny 2}
426 @* Link @url{http://www.distortec.com/jtag-lock-pick-tiny-2} FT232H-based
429 @* Link: @url{http://shop.gateworks.com/index.php?route=product/product&path=70_80&product_id=64}
433 @section USB-JTAG / Altera USB-Blaster compatibles
435 These devices also show up as FTDI devices, but are not
436 protocol-compatible with the FT2232 devices. They are, however,
437 protocol-compatible among themselves. USB-JTAG devices typically consist
438 of a FT245 followed by a CPLD that understands a particular protocol,
439 or emulates this protocol using some other hardware.
441 They may appear under different USB VID/PID depending on the particular
442 product. The driver can be configured to search for any VID/PID pair
443 (see the section on driver commands).
446 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
447 @* Link: @url{http://ixo-jtag.sourceforge.net/}
448 @item @b{Altera USB-Blaster}
449 @* Link: @url{http://www.altera.com/literature/ug/ug_usb_blstr.pdf}
452 @section USB J-Link based
453 There are several OEM versions of the SEGGER @b{J-Link} adapter. It is
454 an example of a microcontroller based JTAG adapter, it uses an
455 AT91SAM764 internally.
458 @item @b{SEGGER J-Link}
459 @* Link: @url{http://www.segger.com/jlink.html}
460 @item @b{Atmel SAM-ICE} (Only works with Atmel chips!)
461 @* Link: @url{http://www.atmel.com/tools/atmelsam-ice.aspx}
465 @section USB RLINK based
466 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer,
467 permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for
468 SWD and not JTAG, thus not supported.
471 @item @b{Raisonance RLink}
472 @* Link: @url{http://www.mcu-raisonance.com/~rlink-debugger-programmer__@/microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html}
473 @item @b{STM32 Primer}
474 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
475 @item @b{STM32 Primer2}
476 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
479 @section USB ST-LINK based
480 ST Micro has an adapter called @b{ST-LINK}.
481 They only work with ST Micro chips, notably STM32 and STM8.
485 @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
486 @* Link: @url{http://www.st.com/internet/evalboard/product/219866.jsp}
488 @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
489 @* Link: @url{http://www.st.com/internet/evalboard/product/251168.jsp}
492 For info the original ST-LINK enumerates using the mass storage usb class; however,
493 its implementation is completely broken. The result is this causes issues under Linux.
494 The simplest solution is to get Linux to ignore the ST-LINK using one of the following methods:
496 @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
497 @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
500 @section USB TI/Stellaris ICDI based
501 Texas Instruments has an adapter called @b{ICDI}.
502 It is not to be confused with the FTDI based adapters that were originally fitted to their
503 evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
505 @section USB CMSIS-DAP based
506 ARM has released a interface standard called CMSIS-DAP that simplifies connecting
507 debuggers to ARM Cortex based targets @url{http://www.keil.com/support/man/docs/dapdebug/dapdebug_introduction.htm}.
512 @* Link: @url{http://shop.embedded-projects.net/} - which uses an Atmel MEGA32 and a UBN9604
514 @item @b{USB - Presto}
515 @* Link: @url{http://tools.asix.net/prg_presto.htm}
517 @item @b{Versaloon-Link}
518 @* Link: @url{http://www.versaloon.com}
520 @item @b{ARM-JTAG-EW}
521 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
524 @* Link: @url{http://dangerousprototypes.com/bus-pirate-manual/}
527 @* Link: @url{http://code.google.com/p/opendous-jtag/} - which uses an AT90USB162
530 @* Link: @url{http://code.google.com/p/estick-jtag/}
532 @item @b{Keil ULINK v1}
533 @* Link: @url{http://www.keil.com/ulink1/}
536 @section IBM PC Parallel Printer Port Based
538 The two well-known ``JTAG Parallel Ports'' cables are the Xilinx DLC5
539 and the Macraigor Wiggler. There are many clones and variations of
542 Note that parallel ports are becoming much less common, so if you
543 have the choice you should probably avoid these adapters in favor
548 @item @b{Wiggler} - There are many clones of this.
549 @* Link: @url{http://www.macraigor.com/wiggler.htm}
551 @item @b{DLC5} - From XILINX - There are many clones of this
552 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
553 produced, PDF schematics are easily found and it is easy to make.
555 @item @b{Amontec - JTAG Accelerator}
556 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
559 @* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
561 @item @b{Wiggler_ntrst_inverted}
562 @* Yet another variation - See the source code, src/jtag/parport.c
564 @item @b{old_amt_wiggler}
565 @* Unknown - probably not on the market today
568 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
571 @* Link: @url{http://www.amontec.com/chameleon.shtml}
577 @* ispDownload from Lattice Semiconductor
578 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
581 @* From ST Microsystems;
582 @* Link: @url{http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATA_BRIEF/DM00039500.pdf}
590 @* An EP93xx based Linux machine using the GPIO pins directly.
593 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
595 @item @b{bcm2835gpio}
596 @* A BCM2835-based board (e.g. Raspberry Pi) using the GPIO pins of the expansion header.
599 @* A NXP i.MX-based board (e.g. Wandboard) using the GPIO pins (should work on any i.MX processor).
602 @* A JTAG driver acting as a client for the JTAG VPI server interface.
603 @* Link: @url{http://github.com/fjullien/jtag_vpi}
608 @chapter About Jim-Tcl
612 OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
613 This programming language provides a simple and extensible
616 All commands presented in this Guide are extensions to Jim-Tcl.
617 You can use them as simple commands, without needing to learn
618 much of anything about Tcl.
619 Alternatively, you can write Tcl programs with them.
621 You can learn more about Jim at its website, @url{http://jim.tcl.tk}.
622 There is an active and responsive community, get on the mailing list
623 if you have any questions. Jim-Tcl maintainers also lurk on the
624 OpenOCD mailing list.
627 @item @b{Jim vs. Tcl}
628 @* Jim-Tcl is a stripped down version of the well known Tcl language,
629 which can be found here: @url{http://www.tcl.tk}. Jim-Tcl has far
630 fewer features. Jim-Tcl is several dozens of .C files and .H files and
631 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
632 4.2 MB .zip file containing 1540 files.
634 @item @b{Missing Features}
635 @* Our practice has been: Add/clone the real Tcl feature if/when
636 needed. We welcome Jim-Tcl improvements, not bloat. Also there
637 are a large number of optional Jim-Tcl features that are not
641 @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
642 command interpreter today is a mixture of (newer)
643 Jim-Tcl commands, and the (older) original command interpreter.
646 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
647 can type a Tcl for() loop, set variables, etc.
648 Some of the commands documented in this guide are implemented
649 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
651 @item @b{Historical Note}
652 @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
653 before OpenOCD 0.5 release, OpenOCD switched to using Jim-Tcl
654 as a Git submodule, which greatly simplified upgrading Jim-Tcl
655 to benefit from new features and bugfixes in Jim-Tcl.
657 @item @b{Need a crash course in Tcl?}
658 @*@xref{Tcl Crash Course}.
663 @cindex command line options
665 @cindex directory search
667 Properly installing OpenOCD sets up your operating system to grant it access
668 to the debug adapters. On Linux, this usually involves installing a file
669 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. An example rules file
670 that works for many common adapters is shipped with OpenOCD in the
671 @file{contrib} directory. MS-Windows needs
672 complex and confusing driver configuration for every peripheral. Such issues
673 are unique to each operating system, and are not detailed in this User's Guide.
675 Then later you will invoke the OpenOCD server, with various options to
676 tell it how each debug session should work.
677 The @option{--help} option shows:
681 --help | -h display this help
682 --version | -v display OpenOCD version
683 --file | -f use configuration file <name>
684 --search | -s dir to search for config files and scripts
685 --debug | -d set debug level to 3
686 | -d<n> set debug level to <level>
687 --log_output | -l redirect log output to file <name>
688 --command | -c run <command>
691 If you don't give any @option{-f} or @option{-c} options,
692 OpenOCD tries to read the configuration file @file{openocd.cfg}.
693 To specify one or more different
694 configuration files, use @option{-f} options. For example:
697 openocd -f config1.cfg -f config2.cfg -f config3.cfg
700 Configuration files and scripts are searched for in
702 @item the current directory,
703 @item any search dir specified on the command line using the @option{-s} option,
704 @item any search dir specified using the @command{add_script_search_dir} command,
705 @item @file{$HOME/.openocd} (not on Windows),
706 @item a directory in the @env{OPENOCD_SCRIPTS} environment variable (if set),
707 @item the site wide script library @file{$pkgdatadir/site} and
708 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
710 The first found file with a matching file name will be used.
713 Don't try to use configuration script names or paths which
714 include the "#" character. That character begins Tcl comments.
717 @section Simple setup, no customization
719 In the best case, you can use two scripts from one of the script
720 libraries, hook up your JTAG adapter, and start the server ... and
721 your JTAG setup will just work "out of the box". Always try to
722 start by reusing those scripts, but assume you'll need more
723 customization even if this works. @xref{OpenOCD Project Setup}.
725 If you find a script for your JTAG adapter, and for your board or
726 target, you may be able to hook up your JTAG adapter then start
727 the server with some variation of one of the following:
730 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
731 openocd -f interface/ftdi/ADAPTER.cfg -f board/MYBOARD.cfg
734 You might also need to configure which reset signals are present,
735 using @option{-c 'reset_config trst_and_srst'} or something similar.
736 If all goes well you'll see output something like
739 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
740 For bug reports, read
741 http://openocd.org/doc/doxygen/bugs.html
742 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
743 (mfg: 0x23b, part: 0xba00, ver: 0x3)
746 Seeing that "tap/device found" message, and no warnings, means
747 the JTAG communication is working. That's a key milestone, but
748 you'll probably need more project-specific setup.
750 @section What OpenOCD does as it starts
752 OpenOCD starts by processing the configuration commands provided
753 on the command line or, if there were no @option{-c command} or
754 @option{-f file.cfg} options given, in @file{openocd.cfg}.
755 @xref{configurationstage,,Configuration Stage}.
756 At the end of the configuration stage it verifies the JTAG scan
757 chain defined using those commands; your configuration should
758 ensure that this always succeeds.
759 Normally, OpenOCD then starts running as a server.
760 Alternatively, commands may be used to terminate the configuration
761 stage early, perform work (such as updating some flash memory),
762 and then shut down without acting as a server.
764 Once OpenOCD starts running as a server, it waits for connections from
765 clients (Telnet, GDB, RPC) and processes the commands issued through
768 If you are having problems, you can enable internal debug messages via
769 the @option{-d} option.
771 Also it is possible to interleave Jim-Tcl commands w/config scripts using the
772 @option{-c} command line switch.
774 To enable debug output (when reporting problems or working on OpenOCD
775 itself), use the @option{-d} command line switch. This sets the
776 @option{debug_level} to "3", outputting the most information,
777 including debug messages. The default setting is "2", outputting only
778 informational messages, warnings and errors. You can also change this
779 setting from within a telnet or gdb session using @command{debug_level<n>}
780 (@pxref{debuglevel,,debug_level}).
782 You can redirect all output from the server to a file using the
783 @option{-l <logfile>} switch.
785 Note! OpenOCD will launch the GDB & telnet server even if it can not
786 establish a connection with the target. In general, it is possible for
787 the JTAG controller to be unresponsive until the target is set up
788 correctly via e.g. GDB monitor commands in a GDB init script.
790 @node OpenOCD Project Setup
791 @chapter OpenOCD Project Setup
793 To use OpenOCD with your development projects, you need to do more than
794 just connect the JTAG adapter hardware (dongle) to your development board
795 and start the OpenOCD server.
796 You also need to configure your OpenOCD server so that it knows
797 about your adapter and board, and helps your work.
798 You may also want to connect OpenOCD to GDB, possibly
799 using Eclipse or some other GUI.
801 @section Hooking up the JTAG Adapter
803 Today's most common case is a dongle with a JTAG cable on one side
804 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
805 and a USB cable on the other.
806 Instead of USB, some cables use Ethernet;
807 older ones may use a PC parallel port, or even a serial port.
810 @item @emph{Start with power to your target board turned off},
811 and nothing connected to your JTAG adapter.
812 If you're particularly paranoid, unplug power to the board.
813 It's important to have the ground signal properly set up,
814 unless you are using a JTAG adapter which provides
815 galvanic isolation between the target board and the
818 @item @emph{Be sure it's the right kind of JTAG connector.}
819 If your dongle has a 20-pin ARM connector, you need some kind
820 of adapter (or octopus, see below) to hook it up to
821 boards using 14-pin or 10-pin connectors ... or to 20-pin
822 connectors which don't use ARM's pinout.
824 In the same vein, make sure the voltage levels are compatible.
825 Not all JTAG adapters have the level shifters needed to work
826 with 1.2 Volt boards.
828 @item @emph{Be certain the cable is properly oriented} or you might
829 damage your board. In most cases there are only two possible
830 ways to connect the cable.
831 Connect the JTAG cable from your adapter to the board.
832 Be sure it's firmly connected.
834 In the best case, the connector is keyed to physically
835 prevent you from inserting it wrong.
836 This is most often done using a slot on the board's male connector
837 housing, which must match a key on the JTAG cable's female connector.
838 If there's no housing, then you must look carefully and
839 make sure pin 1 on the cable hooks up to pin 1 on the board.
840 Ribbon cables are frequently all grey except for a wire on one
841 edge, which is red. The red wire is pin 1.
843 Sometimes dongles provide cables where one end is an ``octopus'' of
844 color coded single-wire connectors, instead of a connector block.
845 These are great when converting from one JTAG pinout to another,
846 but are tedious to set up.
847 Use these with connector pinout diagrams to help you match up the
848 adapter signals to the right board pins.
850 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
851 A USB, parallel, or serial port connector will go to the host which
852 you are using to run OpenOCD.
853 For Ethernet, consult the documentation and your network administrator.
855 For USB-based JTAG adapters you have an easy sanity check at this point:
856 does the host operating system see the JTAG adapter? If you're running
857 Linux, try the @command{lsusb} command. If that host is an
858 MS-Windows host, you'll need to install a driver before OpenOCD works.
860 @item @emph{Connect the adapter's power supply, if needed.}
861 This step is primarily for non-USB adapters,
862 but sometimes USB adapters need extra power.
864 @item @emph{Power up the target board.}
865 Unless you just let the magic smoke escape,
866 you're now ready to set up the OpenOCD server
867 so you can use JTAG to work with that board.
871 Talk with the OpenOCD server using
872 telnet (@code{telnet localhost 4444} on many systems) or GDB.
873 @xref{GDB and OpenOCD}.
875 @section Project Directory
877 There are many ways you can configure OpenOCD and start it up.
879 A simple way to organize them all involves keeping a
880 single directory for your work with a given board.
881 When you start OpenOCD from that directory,
882 it searches there first for configuration files, scripts,
883 files accessed through semihosting,
884 and for code you upload to the target board.
885 It is also the natural place to write files,
886 such as log files and data you download from the board.
888 @section Configuration Basics
890 There are two basic ways of configuring OpenOCD, and
891 a variety of ways you can mix them.
892 Think of the difference as just being how you start the server:
895 @item Many @option{-f file} or @option{-c command} options on the command line
896 @item No options, but a @dfn{user config file}
897 in the current directory named @file{openocd.cfg}
900 Here is an example @file{openocd.cfg} file for a setup
901 using a Signalyzer FT2232-based JTAG adapter to talk to
902 a board with an Atmel AT91SAM7X256 microcontroller:
905 source [find interface/ftdi/signalyzer.cfg]
907 # GDB can also flash my flash!
908 gdb_memory_map enable
909 gdb_flash_program enable
911 source [find target/sam7x256.cfg]
914 Here is the command line equivalent of that configuration:
917 openocd -f interface/ftdi/signalyzer.cfg \
918 -c "gdb_memory_map enable" \
919 -c "gdb_flash_program enable" \
920 -f target/sam7x256.cfg
923 You could wrap such long command lines in shell scripts,
924 each supporting a different development task.
925 One might re-flash the board with a specific firmware version.
926 Another might set up a particular debugging or run-time environment.
929 At this writing (October 2009) the command line method has
930 problems with how it treats variables.
931 For example, after @option{-c "set VAR value"}, or doing the
932 same in a script, the variable @var{VAR} will have no value
933 that can be tested in a later script.
936 Here we will focus on the simpler solution: one user config
937 file, including basic configuration plus any TCL procedures
938 to simplify your work.
940 @section User Config Files
941 @cindex config file, user
942 @cindex user config file
943 @cindex config file, overview
945 A user configuration file ties together all the parts of a project
947 One of the following will match your situation best:
950 @item Ideally almost everything comes from configuration files
951 provided by someone else.
952 For example, OpenOCD distributes a @file{scripts} directory
953 (probably in @file{/usr/share/openocd/scripts} on Linux).
954 Board and tool vendors can provide these too, as can individual
955 user sites; the @option{-s} command line option lets you say
956 where to find these files. (@xref{Running}.)
957 The AT91SAM7X256 example above works this way.
959 Three main types of non-user configuration file each have their
960 own subdirectory in the @file{scripts} directory:
963 @item @b{interface} -- one for each different debug adapter;
964 @item @b{board} -- one for each different board
965 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
968 Best case: include just two files, and they handle everything else.
969 The first is an interface config file.
970 The second is board-specific, and it sets up the JTAG TAPs and
971 their GDB targets (by deferring to some @file{target.cfg} file),
972 declares all flash memory, and leaves you nothing to do except
976 source [find interface/olimex-jtag-tiny.cfg]
977 source [find board/csb337.cfg]
980 Boards with a single microcontroller often won't need more
981 than the target config file, as in the AT91SAM7X256 example.
982 That's because there is no external memory (flash, DDR RAM), and
983 the board differences are encapsulated by application code.
985 @item Maybe you don't know yet what your board looks like to JTAG.
986 Once you know the @file{interface.cfg} file to use, you may
987 need help from OpenOCD to discover what's on the board.
988 Once you find the JTAG TAPs, you can just search for appropriate
990 configuration files ... or write your own, from the bottom up.
991 @xref{autoprobing,,Autoprobing}.
993 @item You can often reuse some standard config files but
994 need to write a few new ones, probably a @file{board.cfg} file.
995 You will be using commands described later in this User's Guide,
996 and working with the guidelines in the next chapter.
998 For example, there may be configuration files for your JTAG adapter
999 and target chip, but you need a new board-specific config file
1000 giving access to your particular flash chips.
1001 Or you might need to write another target chip configuration file
1002 for a new chip built around the Cortex-M3 core.
1005 When you write new configuration files, please submit
1006 them for inclusion in the next OpenOCD release.
1007 For example, a @file{board/newboard.cfg} file will help the
1008 next users of that board, and a @file{target/newcpu.cfg}
1009 will help support users of any board using that chip.
1013 You may may need to write some C code.
1014 It may be as simple as supporting a new FT2232 or parport
1015 based adapter; a bit more involved, like a NAND or NOR flash
1016 controller driver; or a big piece of work like supporting
1017 a new chip architecture.
1020 Reuse the existing config files when you can.
1021 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
1022 You may find a board configuration that's a good example to follow.
1024 When you write config files, separate the reusable parts
1025 (things every user of that interface, chip, or board needs)
1026 from ones specific to your environment and debugging approach.
1030 For example, a @code{gdb-attach} event handler that invokes
1031 the @command{reset init} command will interfere with debugging
1032 early boot code, which performs some of the same actions
1033 that the @code{reset-init} event handler does.
1036 Likewise, the @command{arm9 vector_catch} command (or
1037 @cindex vector_catch
1038 its siblings @command{xscale vector_catch}
1039 and @command{cortex_m vector_catch}) can be a timesaver
1040 during some debug sessions, but don't make everyone use that either.
1041 Keep those kinds of debugging aids in your user config file,
1042 along with messaging and tracing setup.
1043 (@xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.)
1046 You might need to override some defaults.
1047 For example, you might need to move, shrink, or back up the target's
1048 work area if your application needs much SRAM.
1051 TCP/IP port configuration is another example of something which
1052 is environment-specific, and should only appear in
1053 a user config file. @xref{tcpipports,,TCP/IP Ports}.
1056 @section Project-Specific Utilities
1058 A few project-specific utility
1059 routines may well speed up your work.
1060 Write them, and keep them in your project's user config file.
1062 For example, if you are making a boot loader work on a
1063 board, it's nice to be able to debug the ``after it's
1064 loaded to RAM'' parts separately from the finicky early
1065 code which sets up the DDR RAM controller and clocks.
1066 A script like this one, or a more GDB-aware sibling,
1070 proc ramboot @{ @} @{
1071 # Reset, running the target's "reset-init" scripts
1072 # to initialize clocks and the DDR RAM controller.
1073 # Leave the CPU halted.
1076 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
1077 load_image u-boot.bin 0x20000000
1084 Then once that code is working you will need to make it
1085 boot from NOR flash; a different utility would help.
1086 Alternatively, some developers write to flash using GDB.
1087 (You might use a similar script if you're working with a flash
1088 based microcontroller application instead of a boot loader.)
1091 proc newboot @{ @} @{
1092 # Reset, leaving the CPU halted. The "reset-init" event
1093 # proc gives faster access to the CPU and to NOR flash;
1094 # "reset halt" would be slower.
1097 # Write standard version of U-Boot into the first two
1098 # sectors of NOR flash ... the standard version should
1099 # do the same lowlevel init as "reset-init".
1100 flash protect 0 0 1 off
1101 flash erase_sector 0 0 1
1102 flash write_bank 0 u-boot.bin 0x0
1103 flash protect 0 0 1 on
1105 # Reboot from scratch using that new boot loader.
1110 You may need more complicated utility procedures when booting
1112 That often involves an extra bootloader stage,
1113 running from on-chip SRAM to perform DDR RAM setup so it can load
1114 the main bootloader code (which won't fit into that SRAM).
1116 Other helper scripts might be used to write production system images,
1117 involving considerably more than just a three stage bootloader.
1119 @section Target Software Changes
1121 Sometimes you may want to make some small changes to the software
1122 you're developing, to help make JTAG debugging work better.
1123 For example, in C or assembly language code you might
1124 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1125 handling issues like:
1129 @item @b{Watchdog Timers}...
1130 Watchog timers are typically used to automatically reset systems if
1131 some application task doesn't periodically reset the timer. (The
1132 assumption is that the system has locked up if the task can't run.)
1133 When a JTAG debugger halts the system, that task won't be able to run
1134 and reset the timer ... potentially causing resets in the middle of
1135 your debug sessions.
1137 It's rarely a good idea to disable such watchdogs, since their usage
1138 needs to be debugged just like all other parts of your firmware.
1139 That might however be your only option.
1141 Look instead for chip-specific ways to stop the watchdog from counting
1142 while the system is in a debug halt state. It may be simplest to set
1143 that non-counting mode in your debugger startup scripts. You may however
1144 need a different approach when, for example, a motor could be physically
1145 damaged by firmware remaining inactive in a debug halt state. That might
1146 involve a type of firmware mode where that "non-counting" mode is disabled
1147 at the beginning then re-enabled at the end; a watchdog reset might fire
1148 and complicate the debug session, but hardware (or people) would be
1149 protected.@footnote{Note that many systems support a "monitor mode" debug
1150 that is a somewhat cleaner way to address such issues. You can think of
1151 it as only halting part of the system, maybe just one task,
1152 instead of the whole thing.
1153 At this writing, January 2010, OpenOCD based debugging does not support
1154 monitor mode debug, only "halt mode" debug.}
1156 @item @b{ARM Semihosting}...
1157 @cindex ARM semihosting
1158 When linked with a special runtime library provided with many
1159 toolchains@footnote{See chapter 8 "Semihosting" in
1160 @uref{http://infocenter.arm.com/help/topic/com.arm.doc.dui0203i/DUI0203I_rvct_developer_guide.pdf,
1161 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1162 The CodeSourcery EABI toolchain also includes a semihosting library.},
1163 your target code can use I/O facilities on the debug host. That library
1164 provides a small set of system calls which are handled by OpenOCD.
1165 It can let the debugger provide your system console and a file system,
1166 helping with early debugging or providing a more capable environment
1167 for sometimes-complex tasks like installing system firmware onto
1170 @item @b{ARM Wait-For-Interrupt}...
1171 Many ARM chips synchronize the JTAG clock using the core clock.
1172 Low power states which stop that core clock thus prevent JTAG access.
1173 Idle loops in tasking environments often enter those low power states
1174 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1176 You may want to @emph{disable that instruction} in source code,
1177 or otherwise prevent using that state,
1178 to ensure you can get JTAG access at any time.@footnote{As a more
1179 polite alternative, some processors have special debug-oriented
1180 registers which can be used to change various features including
1181 how the low power states are clocked while debugging.
1182 The STM32 DBGMCU_CR register is an example; at the cost of extra
1183 power consumption, JTAG can be used during low power states.}
1184 For example, the OpenOCD @command{halt} command may not
1185 work for an idle processor otherwise.
1187 @item @b{Delay after reset}...
1188 Not all chips have good support for debugger access
1189 right after reset; many LPC2xxx chips have issues here.
1190 Similarly, applications that reconfigure pins used for
1191 JTAG access as they start will also block debugger access.
1193 To work with boards like this, @emph{enable a short delay loop}
1194 the first thing after reset, before "real" startup activities.
1195 For example, one second's delay is usually more than enough
1196 time for a JTAG debugger to attach, so that
1197 early code execution can be debugged
1198 or firmware can be replaced.
1200 @item @b{Debug Communications Channel (DCC)}...
1201 Some processors include mechanisms to send messages over JTAG.
1202 Many ARM cores support these, as do some cores from other vendors.
1203 (OpenOCD may be able to use this DCC internally, speeding up some
1204 operations like writing to memory.)
1206 Your application may want to deliver various debugging messages
1207 over JTAG, by @emph{linking with a small library of code}
1208 provided with OpenOCD and using the utilities there to send
1209 various kinds of message.
1210 @xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.
1214 @section Target Hardware Setup
1216 Chip vendors often provide software development boards which
1217 are highly configurable, so that they can support all options
1218 that product boards may require. @emph{Make sure that any
1219 jumpers or switches match the system configuration you are
1222 Common issues include:
1226 @item @b{JTAG setup} ...
1227 Boards may support more than one JTAG configuration.
1228 Examples include jumpers controlling pullups versus pulldowns
1229 on the nTRST and/or nSRST signals, and choice of connectors
1230 (e.g. which of two headers on the base board,
1231 or one from a daughtercard).
1232 For some Texas Instruments boards, you may need to jumper the
1233 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1235 @item @b{Boot Modes} ...
1236 Complex chips often support multiple boot modes, controlled
1237 by external jumpers. Make sure this is set up correctly.
1238 For example many i.MX boards from NXP need to be jumpered
1239 to "ATX mode" to start booting using the on-chip ROM, when
1240 using second stage bootloader code stored in a NAND flash chip.
1242 Such explicit configuration is common, and not limited to
1243 booting from NAND. You might also need to set jumpers to
1244 start booting using code loaded from an MMC/SD card; external
1245 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1246 flash; some external host; or various other sources.
1249 @item @b{Memory Addressing} ...
1250 Boards which support multiple boot modes may also have jumpers
1251 to configure memory addressing. One board, for example, jumpers
1252 external chipselect 0 (used for booting) to address either
1253 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1254 or NAND flash. When it's jumpered to address NAND flash, that
1255 board must also be told to start booting from on-chip ROM.
1257 Your @file{board.cfg} file may also need to be told this jumper
1258 configuration, so that it can know whether to declare NOR flash
1259 using @command{flash bank} or instead declare NAND flash with
1260 @command{nand device}; and likewise which probe to perform in
1261 its @code{reset-init} handler.
1263 A closely related issue is bus width. Jumpers might need to
1264 distinguish between 8 bit or 16 bit bus access for the flash
1265 used to start booting.
1267 @item @b{Peripheral Access} ...
1268 Development boards generally provide access to every peripheral
1269 on the chip, sometimes in multiple modes (such as by providing
1270 multiple audio codec chips).
1271 This interacts with software
1272 configuration of pin multiplexing, where for example a
1273 given pin may be routed either to the MMC/SD controller
1274 or the GPIO controller. It also often interacts with
1275 configuration jumpers. One jumper may be used to route
1276 signals to an MMC/SD card slot or an expansion bus (which
1277 might in turn affect booting); others might control which
1278 audio or video codecs are used.
1282 Plus you should of course have @code{reset-init} event handlers
1283 which set up the hardware to match that jumper configuration.
1284 That includes in particular any oscillator or PLL used to clock
1285 the CPU, and any memory controllers needed to access external
1286 memory and peripherals. Without such handlers, you won't be
1287 able to access those resources without working target firmware
1288 which can do that setup ... this can be awkward when you're
1289 trying to debug that target firmware. Even if there's a ROM
1290 bootloader which handles a few issues, it rarely provides full
1291 access to all board-specific capabilities.
1294 @node Config File Guidelines
1295 @chapter Config File Guidelines
1297 This chapter is aimed at any user who needs to write a config file,
1298 including developers and integrators of OpenOCD and any user who
1299 needs to get a new board working smoothly.
1300 It provides guidelines for creating those files.
1302 You should find the following directories under
1303 @t{$(INSTALLDIR)/scripts}, with config files maintained upstream. Use
1304 them as-is where you can; or as models for new files.
1306 @item @file{interface} ...
1307 These are for debug adapters. Files that specify configuration to use
1308 specific JTAG, SWD and other adapters go here.
1309 @item @file{board} ...
1310 Think Circuit Board, PWA, PCB, they go by many names. Board files
1311 contain initialization items that are specific to a board.
1313 They reuse target configuration files, since the same
1314 microprocessor chips are used on many boards,
1315 but support for external parts varies widely. For
1316 example, the SDRAM initialization sequence for the board, or the type
1317 of external flash and what address it uses. Any initialization
1318 sequence to enable that external flash or SDRAM should be found in the
1319 board file. Boards may also contain multiple targets: two CPUs; or
1321 @item @file{target} ...
1322 Think chip. The ``target'' directory represents the JTAG TAPs
1324 which OpenOCD should control, not a board. Two common types of targets
1325 are ARM chips and FPGA or CPLD chips.
1326 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1327 the target config file defines all of them.
1328 @item @emph{more} ... browse for other library files which may be useful.
1329 For example, there are various generic and CPU-specific utilities.
1332 The @file{openocd.cfg} user config
1333 file may override features in any of the above files by
1334 setting variables before sourcing the target file, or by adding
1335 commands specific to their situation.
1337 @section Interface Config Files
1339 The user config file
1340 should be able to source one of these files with a command like this:
1343 source [find interface/FOOBAR.cfg]
1346 A preconfigured interface file should exist for every debug adapter
1347 in use today with OpenOCD.
1348 That said, perhaps some of these config files
1349 have only been used by the developer who created it.
1351 A separate chapter gives information about how to set these up.
1352 @xref{Debug Adapter Configuration}.
1353 Read the OpenOCD source code (and Developer's Guide)
1354 if you have a new kind of hardware interface
1355 and need to provide a driver for it.
1357 @section Board Config Files
1358 @cindex config file, board
1359 @cindex board config file
1361 The user config file
1362 should be able to source one of these files with a command like this:
1365 source [find board/FOOBAR.cfg]
1368 The point of a board config file is to package everything
1369 about a given board that user config files need to know.
1370 In summary the board files should contain (if present)
1373 @item One or more @command{source [find target/...cfg]} statements
1374 @item NOR flash configuration (@pxref{norconfiguration,,NOR Configuration})
1375 @item NAND flash configuration (@pxref{nandconfiguration,,NAND Configuration})
1376 @item Target @code{reset} handlers for SDRAM and I/O configuration
1377 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1378 @item All things that are not ``inside a chip''
1381 Generic things inside target chips belong in target config files,
1382 not board config files. So for example a @code{reset-init} event
1383 handler should know board-specific oscillator and PLL parameters,
1384 which it passes to target-specific utility code.
1386 The most complex task of a board config file is creating such a
1387 @code{reset-init} event handler.
1388 Define those handlers last, after you verify the rest of the board
1389 configuration works.
1391 @subsection Communication Between Config files
1393 In addition to target-specific utility code, another way that
1394 board and target config files communicate is by following a
1395 convention on how to use certain variables.
1397 The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
1398 Thus the rule we follow in OpenOCD is this: Variables that begin with
1399 a leading underscore are temporary in nature, and can be modified and
1400 used at will within a target configuration file.
1402 Complex board config files can do the things like this,
1403 for a board with three chips:
1406 # Chip #1: PXA270 for network side, big endian
1407 set CHIPNAME network
1409 source [find target/pxa270.cfg]
1410 # on return: _TARGETNAME = network.cpu
1411 # other commands can refer to the "network.cpu" target.
1412 $_TARGETNAME configure .... events for this CPU..
1414 # Chip #2: PXA270 for video side, little endian
1417 source [find target/pxa270.cfg]
1418 # on return: _TARGETNAME = video.cpu
1419 # other commands can refer to the "video.cpu" target.
1420 $_TARGETNAME configure .... events for this CPU..
1422 # Chip #3: Xilinx FPGA for glue logic
1425 source [find target/spartan3.cfg]
1428 That example is oversimplified because it doesn't show any flash memory,
1429 or the @code{reset-init} event handlers to initialize external DRAM
1430 or (assuming it needs it) load a configuration into the FPGA.
1431 Such features are usually needed for low-level work with many boards,
1432 where ``low level'' implies that the board initialization software may
1433 not be working. (That's a common reason to need JTAG tools. Another
1434 is to enable working with microcontroller-based systems, which often
1435 have no debugging support except a JTAG connector.)
1437 Target config files may also export utility functions to board and user
1438 config files. Such functions should use name prefixes, to help avoid
1441 Board files could also accept input variables from user config files.
1442 For example, there might be a @code{J4_JUMPER} setting used to identify
1443 what kind of flash memory a development board is using, or how to set
1444 up other clocks and peripherals.
1446 @subsection Variable Naming Convention
1447 @cindex variable names
1449 Most boards have only one instance of a chip.
1450 However, it should be easy to create a board with more than
1451 one such chip (as shown above).
1452 Accordingly, we encourage these conventions for naming
1453 variables associated with different @file{target.cfg} files,
1454 to promote consistency and
1455 so that board files can override target defaults.
1457 Inputs to target config files include:
1460 @item @code{CHIPNAME} ...
1461 This gives a name to the overall chip, and is used as part of
1462 tap identifier dotted names.
1463 While the default is normally provided by the chip manufacturer,
1464 board files may need to distinguish between instances of a chip.
1465 @item @code{ENDIAN} ...
1466 By default @option{little} - although chips may hard-wire @option{big}.
1467 Chips that can't change endianness don't need to use this variable.
1468 @item @code{CPUTAPID} ...
1469 When OpenOCD examines the JTAG chain, it can be told verify the
1470 chips against the JTAG IDCODE register.
1471 The target file will hold one or more defaults, but sometimes the
1472 chip in a board will use a different ID (perhaps a newer revision).
1475 Outputs from target config files include:
1478 @item @code{_TARGETNAME} ...
1479 By convention, this variable is created by the target configuration
1480 script. The board configuration file may make use of this variable to
1481 configure things like a ``reset init'' script, or other things
1482 specific to that board and that target.
1483 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1484 @code{_TARGETNAME1}, ... etc.
1487 @subsection The reset-init Event Handler
1488 @cindex event, reset-init
1489 @cindex reset-init handler
1491 Board config files run in the OpenOCD configuration stage;
1492 they can't use TAPs or targets, since they haven't been
1494 This means you can't write memory or access chip registers;
1495 you can't even verify that a flash chip is present.
1496 That's done later in event handlers, of which the target @code{reset-init}
1497 handler is one of the most important.
1499 Except on microcontrollers, the basic job of @code{reset-init} event
1500 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1501 Microcontrollers rarely use boot loaders; they run right out of their
1502 on-chip flash and SRAM memory. But they may want to use one of these
1503 handlers too, if just for developer convenience.
1506 Because this is so very board-specific, and chip-specific, no examples
1508 Instead, look at the board config files distributed with OpenOCD.
1509 If you have a boot loader, its source code will help; so will
1510 configuration files for other JTAG tools
1511 (@pxref{translatingconfigurationfiles,,Translating Configuration Files}).
1514 Some of this code could probably be shared between different boards.
1515 For example, setting up a DRAM controller often doesn't differ by
1516 much except the bus width (16 bits or 32?) and memory timings, so a
1517 reusable TCL procedure loaded by the @file{target.cfg} file might take
1518 those as parameters.
1519 Similarly with oscillator, PLL, and clock setup;
1520 and disabling the watchdog.
1521 Structure the code cleanly, and provide comments to help
1522 the next developer doing such work.
1523 (@emph{You might be that next person} trying to reuse init code!)
1525 The last thing normally done in a @code{reset-init} handler is probing
1526 whatever flash memory was configured. For most chips that needs to be
1527 done while the associated target is halted, either because JTAG memory
1528 access uses the CPU or to prevent conflicting CPU access.
1530 @subsection JTAG Clock Rate
1532 Before your @code{reset-init} handler has set up
1533 the PLLs and clocking, you may need to run with
1534 a low JTAG clock rate.
1535 @xref{jtagspeed,,JTAG Speed}.
1536 Then you'd increase that rate after your handler has
1537 made it possible to use the faster JTAG clock.
1538 When the initial low speed is board-specific, for example
1539 because it depends on a board-specific oscillator speed, then
1540 you should probably set it up in the board config file;
1541 if it's target-specific, it belongs in the target config file.
1543 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1544 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1545 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1546 Consult chip documentation to determine the peak JTAG clock rate,
1547 which might be less than that.
1550 On most ARMs, JTAG clock detection is coupled to the core clock, so
1551 software using a @option{wait for interrupt} operation blocks JTAG access.
1552 Adaptive clocking provides a partial workaround, but a more complete
1553 solution just avoids using that instruction with JTAG debuggers.
1556 If both the chip and the board support adaptive clocking,
1557 use the @command{jtag_rclk}
1558 command, in case your board is used with JTAG adapter which
1559 also supports it. Otherwise use @command{adapter_khz}.
1560 Set the slow rate at the beginning of the reset sequence,
1561 and the faster rate as soon as the clocks are at full speed.
1563 @anchor{theinitboardprocedure}
1564 @subsection The init_board procedure
1565 @cindex init_board procedure
1567 The concept of @code{init_board} procedure is very similar to @code{init_targets}
1568 (@xref{theinittargetsprocedure,,The init_targets procedure}.) - it's a replacement of ``linear''
1569 configuration scripts. This procedure is meant to be executed when OpenOCD enters run stage
1570 (@xref{enteringtherunstage,,Entering the Run Stage},) after @code{init_targets}. The idea to have
1571 separate @code{init_targets} and @code{init_board} procedures is to allow the first one to configure
1572 everything target specific (internal flash, internal RAM, etc.) and the second one to configure
1573 everything board specific (reset signals, chip frequency, reset-init event handler, external memory, etc.).
1574 Additionally ``linear'' board config file will most likely fail when target config file uses
1575 @code{init_targets} scheme (``linear'' script is executed before @code{init} and @code{init_targets} - after),
1576 so separating these two configuration stages is very convenient, as the easiest way to overcome this
1577 problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
1578 need to override @code{init_targets} defined in target config files when they only need to add some specifics.
1580 Just as @code{init_targets}, the @code{init_board} procedure can be overridden by ``next level'' script (which sources
1581 the original), allowing greater code reuse.
1584 ### board_file.cfg ###
1586 # source target file that does most of the config in init_targets
1587 source [find target/target.cfg]
1589 proc enable_fast_clock @{@} @{
1590 # enables fast on-board clock source
1591 # configures the chip to use it
1594 # initialize only board specifics - reset, clock, adapter frequency
1595 proc init_board @{@} @{
1596 reset_config trst_and_srst trst_pulls_srst
1598 $_TARGETNAME configure -event reset-start @{
1602 $_TARGETNAME configure -event reset-init @{
1609 @section Target Config Files
1610 @cindex config file, target
1611 @cindex target config file
1613 Board config files communicate with target config files using
1614 naming conventions as described above, and may source one or
1615 more target config files like this:
1618 source [find target/FOOBAR.cfg]
1621 The point of a target config file is to package everything
1622 about a given chip that board config files need to know.
1623 In summary the target files should contain
1627 @item Add TAPs to the scan chain
1628 @item Add CPU targets (includes GDB support)
1629 @item CPU/Chip/CPU-Core specific features
1633 As a rule of thumb, a target file sets up only one chip.
1634 For a microcontroller, that will often include a single TAP,
1635 which is a CPU needing a GDB target, and its on-chip flash.
1637 More complex chips may include multiple TAPs, and the target
1638 config file may need to define them all before OpenOCD
1639 can talk to the chip.
1640 For example, some phone chips have JTAG scan chains that include
1641 an ARM core for operating system use, a DSP,
1642 another ARM core embedded in an image processing engine,
1643 and other processing engines.
1645 @subsection Default Value Boiler Plate Code
1647 All target configuration files should start with code like this,
1648 letting board config files express environment-specific
1649 differences in how things should be set up.
1652 # Boards may override chip names, perhaps based on role,
1653 # but the default should match what the vendor uses
1654 if @{ [info exists CHIPNAME] @} @{
1655 set _CHIPNAME $CHIPNAME
1657 set _CHIPNAME sam7x256
1660 # ONLY use ENDIAN with targets that can change it.
1661 if @{ [info exists ENDIAN] @} @{
1667 # TAP identifiers may change as chips mature, for example with
1668 # new revision fields (the "3" here). Pick a good default; you
1669 # can pass several such identifiers to the "jtag newtap" command.
1670 if @{ [info exists CPUTAPID ] @} @{
1671 set _CPUTAPID $CPUTAPID
1673 set _CPUTAPID 0x3f0f0f0f
1676 @c but 0x3f0f0f0f is for an str73x part ...
1678 @emph{Remember:} Board config files may include multiple target
1679 config files, or the same target file multiple times
1680 (changing at least @code{CHIPNAME}).
1682 Likewise, the target configuration file should define
1683 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1684 use it later on when defining debug targets:
1687 set _TARGETNAME $_CHIPNAME.cpu
1688 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1691 @subsection Adding TAPs to the Scan Chain
1692 After the ``defaults'' are set up,
1693 add the TAPs on each chip to the JTAG scan chain.
1694 @xref{TAP Declaration}, and the naming convention
1697 In the simplest case the chip has only one TAP,
1698 probably for a CPU or FPGA.
1699 The config file for the Atmel AT91SAM7X256
1700 looks (in part) like this:
1703 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1706 A board with two such at91sam7 chips would be able
1707 to source such a config file twice, with different
1708 values for @code{CHIPNAME}, so
1709 it adds a different TAP each time.
1711 If there are nonzero @option{-expected-id} values,
1712 OpenOCD attempts to verify the actual tap id against those values.
1713 It will issue error messages if there is mismatch, which
1714 can help to pinpoint problems in OpenOCD configurations.
1717 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1718 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1719 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1720 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1721 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1724 There are more complex examples too, with chips that have
1725 multiple TAPs. Ones worth looking at include:
1728 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1729 plus a JRC to enable them
1730 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1731 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1732 is not currently used)
1735 @subsection Add CPU targets
1737 After adding a TAP for a CPU, you should set it up so that
1738 GDB and other commands can use it.
1739 @xref{CPU Configuration}.
1740 For the at91sam7 example above, the command can look like this;
1741 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1742 to little endian, and this chip doesn't support changing that.
1745 set _TARGETNAME $_CHIPNAME.cpu
1746 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1749 Work areas are small RAM areas associated with CPU targets.
1750 They are used by OpenOCD to speed up downloads,
1751 and to download small snippets of code to program flash chips.
1752 If the chip includes a form of ``on-chip-ram'' - and many do - define
1753 a work area if you can.
1754 Again using the at91sam7 as an example, this can look like:
1757 $_TARGETNAME configure -work-area-phys 0x00200000 \
1758 -work-area-size 0x4000 -work-area-backup 0
1761 @anchor{definecputargetsworkinginsmp}
1762 @subsection Define CPU targets working in SMP
1764 After setting targets, you can define a list of targets working in SMP.
1767 set _TARGETNAME_1 $_CHIPNAME.cpu1
1768 set _TARGETNAME_2 $_CHIPNAME.cpu2
1769 target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap \
1770 -coreid 0 -dbgbase $_DAP_DBG1
1771 target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap \
1772 -coreid 1 -dbgbase $_DAP_DBG2
1773 #define 2 targets working in smp.
1774 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
1776 In the above example on cortex_a, 2 cpus are working in SMP.
1777 In SMP only one GDB instance is created and :
1779 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
1780 @item halt command triggers the halt of all targets in the list.
1781 @item resume command triggers the write context and the restart of all targets in the list.
1782 @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
1783 @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
1784 displayed by the GDB session @pxref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.
1787 The SMP behaviour can be disabled/enabled dynamically. On cortex_a following
1788 command have been implemented.
1790 @item cortex_a smp_on : enable SMP mode, behaviour is as described above.
1791 @item cortex_a smp_off : disable SMP mode, the current target is the one
1792 displayed in the GDB session, only this target is now controlled by GDB
1793 session. This behaviour is useful during system boot up.
1794 @item cortex_a smp_gdb : display/fix the core id displayed in GDB session see
1801 #0 : coreid 0 is displayed to GDB ,
1802 #-> -1 : next resume triggers a real resume
1803 > cortex_a smp_gdb 1
1805 #0 :coreid 0 is displayed to GDB ,
1806 #->1 : next resume displays coreid 1 to GDB
1810 #1 :coreid 1 is displayed to GDB ,
1811 #->1 : next resume displays coreid 1 to GDB
1812 > cortex_a smp_gdb -1
1814 #1 :coreid 1 is displayed to GDB,
1815 #->-1 : next resume triggers a real resume
1819 @subsection Chip Reset Setup
1821 As a rule, you should put the @command{reset_config} command
1822 into the board file. Most things you think you know about a
1823 chip can be tweaked by the board.
1825 Some chips have specific ways the TRST and SRST signals are
1826 managed. In the unusual case that these are @emph{chip specific}
1827 and can never be changed by board wiring, they could go here.
1828 For example, some chips can't support JTAG debugging without
1831 Provide a @code{reset-assert} event handler if you can.
1832 Such a handler uses JTAG operations to reset the target,
1833 letting this target config be used in systems which don't
1834 provide the optional SRST signal, or on systems where you
1835 don't want to reset all targets at once.
1836 Such a handler might write to chip registers to force a reset,
1837 use a JRC to do that (preferable -- the target may be wedged!),
1838 or force a watchdog timer to trigger.
1839 (For Cortex-M targets, this is not necessary. The target
1840 driver knows how to use trigger an NVIC reset when SRST is
1843 Some chips need special attention during reset handling if
1844 they're going to be used with JTAG.
1845 An example might be needing to send some commands right
1846 after the target's TAP has been reset, providing a
1847 @code{reset-deassert-post} event handler that writes a chip
1848 register to report that JTAG debugging is being done.
1849 Another would be reconfiguring the watchdog so that it stops
1850 counting while the core is halted in the debugger.
1852 JTAG clocking constraints often change during reset, and in
1853 some cases target config files (rather than board config files)
1854 are the right places to handle some of those issues.
1855 For example, immediately after reset most chips run using a
1856 slower clock than they will use later.
1857 That means that after reset (and potentially, as OpenOCD
1858 first starts up) they must use a slower JTAG clock rate
1859 than they will use later.
1860 @xref{jtagspeed,,JTAG Speed}.
1862 @quotation Important
1863 When you are debugging code that runs right after chip
1864 reset, getting these issues right is critical.
1865 In particular, if you see intermittent failures when
1866 OpenOCD verifies the scan chain after reset,
1867 look at how you are setting up JTAG clocking.
1870 @anchor{theinittargetsprocedure}
1871 @subsection The init_targets procedure
1872 @cindex init_targets procedure
1874 Target config files can either be ``linear'' (script executed line-by-line when parsed in
1875 configuration stage, @xref{configurationstage,,Configuration Stage},) or they can contain a special
1876 procedure called @code{init_targets}, which will be executed when entering run stage
1877 (after parsing all config files or after @code{init} command, @xref{enteringtherunstage,,Entering the Run Stage}.)
1878 Such procedure can be overriden by ``next level'' script (which sources the original).
1879 This concept faciliates code reuse when basic target config files provide generic configuration
1880 procedures and @code{init_targets} procedure, which can then be sourced and enchanced or changed in
1881 a ``more specific'' target config file. This is not possible with ``linear'' config scripts,
1882 because sourcing them executes every initialization commands they provide.
1885 ### generic_file.cfg ###
1887 proc setup_my_chip @{chip_name flash_size ram_size@} @{
1888 # basic initialization procedure ...
1891 proc init_targets @{@} @{
1892 # initializes generic chip with 4kB of flash and 1kB of RAM
1893 setup_my_chip MY_GENERIC_CHIP 4096 1024
1896 ### specific_file.cfg ###
1898 source [find target/generic_file.cfg]
1900 proc init_targets @{@} @{
1901 # initializes specific chip with 128kB of flash and 64kB of RAM
1902 setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
1906 The easiest way to convert ``linear'' config files to @code{init_targets} version is to
1907 enclose every line of ``code'' (i.e. not @code{source} commands, procedures, etc.) in this procedure.
1909 For an example of this scheme see LPC2000 target config files.
1911 The @code{init_boards} procedure is a similar concept concerning board config files
1912 (@xref{theinitboardprocedure,,The init_board procedure}.)
1914 @anchor{theinittargeteventsprocedure}
1915 @subsection The init_target_events procedure
1916 @cindex init_target_events procedure
1918 A special procedure called @code{init_target_events} is run just after
1919 @code{init_targets} (@xref{theinittargetsprocedure,,The init_targets
1920 procedure}.) and before @code{init_board}
1921 (@xref{theinitboardprocedure,,The init_board procedure}.) It is used
1922 to set up default target events for the targets that do not have those
1923 events already assigned.
1925 @subsection ARM Core Specific Hacks
1927 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1928 special high speed download features - enable it.
1930 If present, the MMU, the MPU and the CACHE should be disabled.
1932 Some ARM cores are equipped with trace support, which permits
1933 examination of the instruction and data bus activity. Trace
1934 activity is controlled through an ``Embedded Trace Module'' (ETM)
1935 on one of the core's scan chains. The ETM emits voluminous data
1936 through a ``trace port''. (@xref{armhardwaretracing,,ARM Hardware Tracing}.)
1937 If you are using an external trace port,
1938 configure it in your board config file.
1939 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
1940 configure it in your target config file.
1943 etm config $_TARGETNAME 16 normal full etb
1944 etb config $_TARGETNAME $_CHIPNAME.etb
1947 @subsection Internal Flash Configuration
1949 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1951 @b{Never ever} in the ``target configuration file'' define any type of
1952 flash that is external to the chip. (For example a BOOT flash on
1953 Chip Select 0.) Such flash information goes in a board file - not
1954 the TARGET (chip) file.
1958 @item at91sam7x256 - has 256K flash YES enable it.
1959 @item str912 - has flash internal YES enable it.
1960 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1961 @item pxa270 - again - CS0 flash - it goes in the board file.
1964 @anchor{translatingconfigurationfiles}
1965 @section Translating Configuration Files
1967 If you have a configuration file for another hardware debugger
1968 or toolset (Abatron, BDI2000, BDI3000, CCS,
1969 Lauterbach, SEGGER, Macraigor, etc.), translating
1970 it into OpenOCD syntax is often quite straightforward. The most tricky
1971 part of creating a configuration script is oftentimes the reset init
1972 sequence where e.g. PLLs, DRAM and the like is set up.
1974 One trick that you can use when translating is to write small
1975 Tcl procedures to translate the syntax into OpenOCD syntax. This
1976 can avoid manual translation errors and make it easier to
1977 convert other scripts later on.
1979 Example of transforming quirky arguments to a simple search and
1983 # Lauterbach syntax(?)
1985 # Data.Set c15:0x042f %long 0x40000015
1987 # OpenOCD syntax when using procedure below.
1989 # setc15 0x01 0x00050078
1991 proc setc15 @{regs value@} @{
1994 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
1996 arm mcr 15 [expr ($regs>>12)&0x7] \
1997 [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
1998 [expr ($regs>>8)&0x7] $value
2004 @node Server Configuration
2005 @chapter Server Configuration
2006 @cindex initialization
2007 The commands here are commonly found in the openocd.cfg file and are
2008 used to specify what TCP/IP ports are used, and how GDB should be
2011 @anchor{configurationstage}
2012 @section Configuration Stage
2013 @cindex configuration stage
2014 @cindex config command
2016 When the OpenOCD server process starts up, it enters a
2017 @emph{configuration stage} which is the only time that
2018 certain commands, @emph{configuration commands}, may be issued.
2019 Normally, configuration commands are only available
2020 inside startup scripts.
2022 In this manual, the definition of a configuration command is
2023 presented as a @emph{Config Command}, not as a @emph{Command}
2024 which may be issued interactively.
2025 The runtime @command{help} command also highlights configuration
2026 commands, and those which may be issued at any time.
2028 Those configuration commands include declaration of TAPs,
2030 the interface used for JTAG communication,
2031 and other basic setup.
2032 The server must leave the configuration stage before it
2033 may access or activate TAPs.
2034 After it leaves this stage, configuration commands may no
2037 @anchor{enteringtherunstage}
2038 @section Entering the Run Stage
2040 The first thing OpenOCD does after leaving the configuration
2041 stage is to verify that it can talk to the scan chain
2042 (list of TAPs) which has been configured.
2043 It will warn if it doesn't find TAPs it expects to find,
2044 or finds TAPs that aren't supposed to be there.
2045 You should see no errors at this point.
2046 If you see errors, resolve them by correcting the
2047 commands you used to configure the server.
2048 Common errors include using an initial JTAG speed that's too
2049 fast, and not providing the right IDCODE values for the TAPs
2052 Once OpenOCD has entered the run stage, a number of commands
2054 A number of these relate to the debug targets you may have declared.
2055 For example, the @command{mww} command will not be available until
2056 a target has been successfuly instantiated.
2057 If you want to use those commands, you may need to force
2058 entry to the run stage.
2060 @deffn {Config Command} init
2061 This command terminates the configuration stage and
2062 enters the run stage. This helps when you need to have
2063 the startup scripts manage tasks such as resetting the target,
2064 programming flash, etc. To reset the CPU upon startup, add "init" and
2065 "reset" at the end of the config script or at the end of the OpenOCD
2066 command line using the @option{-c} command line switch.
2068 If this command does not appear in any startup/configuration file
2069 OpenOCD executes the command for you after processing all
2070 configuration files and/or command line options.
2072 @b{NOTE:} This command normally occurs at or near the end of your
2073 openocd.cfg file to force OpenOCD to ``initialize'' and make the
2074 targets ready. For example: If your openocd.cfg file needs to
2075 read/write memory on your target, @command{init} must occur before
2076 the memory read/write commands. This includes @command{nand probe}.
2079 @deffn {Overridable Procedure} jtag_init
2080 This is invoked at server startup to verify that it can talk
2081 to the scan chain (list of TAPs) which has been configured.
2083 The default implementation first tries @command{jtag arp_init},
2084 which uses only a lightweight JTAG reset before examining the
2086 If that fails, it tries again, using a harder reset
2087 from the overridable procedure @command{init_reset}.
2089 Implementations must have verified the JTAG scan chain before
2091 This is done by calling @command{jtag arp_init}
2092 (or @command{jtag arp_init-reset}).
2096 @section TCP/IP Ports
2101 The OpenOCD server accepts remote commands in several syntaxes.
2102 Each syntax uses a different TCP/IP port, which you may specify
2103 only during configuration (before those ports are opened).
2105 For reasons including security, you may wish to prevent remote
2106 access using one or more of these ports.
2107 In such cases, just specify the relevant port number as "disabled".
2108 If you disable all access through TCP/IP, you will need to
2109 use the command line @option{-pipe} option.
2111 @deffn {Command} gdb_port [number]
2113 Normally gdb listens to a TCP/IP port, but GDB can also
2114 communicate via pipes(stdin/out or named pipes). The name
2115 "gdb_port" stuck because it covers probably more than 90% of
2116 the normal use cases.
2118 No arguments reports GDB port. "pipe" means listen to stdin
2119 output to stdout, an integer is base port number, "disabled"
2120 disables the gdb server.
2122 When using "pipe", also use log_output to redirect the log
2123 output to a file so as not to flood the stdin/out pipes.
2125 The -p/--pipe option is deprecated and a warning is printed
2126 as it is equivalent to passing in -c "gdb_port pipe; log_output openocd.log".
2128 Any other string is interpreted as named pipe to listen to.
2129 Output pipe is the same name as input pipe, but with 'o' appended,
2130 e.g. /var/gdb, /var/gdbo.
2132 The GDB port for the first target will be the base port, the
2133 second target will listen on gdb_port + 1, and so on.
2134 When not specified during the configuration stage,
2135 the port @var{number} defaults to 3333.
2137 Note: when using "gdb_port pipe", increasing the default remote timeout in
2138 gdb (with 'set remotetimeout') is recommended. An insufficient timeout may
2139 cause initialization to fail with "Unknown remote qXfer reply: OK".
2143 @deffn {Command} tcl_port [number]
2144 Specify or query the port used for a simplified RPC
2145 connection that can be used by clients to issue TCL commands and get the
2146 output from the Tcl engine.
2147 Intended as a machine interface.
2148 When not specified during the configuration stage,
2149 the port @var{number} defaults to 6666.
2150 When specified as "disabled", this service is not activated.
2153 @deffn {Command} telnet_port [number]
2154 Specify or query the
2155 port on which to listen for incoming telnet connections.
2156 This port is intended for interaction with one human through TCL commands.
2157 When not specified during the configuration stage,
2158 the port @var{number} defaults to 4444.
2159 When specified as "disabled", this service is not activated.
2162 @anchor{gdbconfiguration}
2163 @section GDB Configuration
2165 @cindex GDB configuration
2166 You can reconfigure some GDB behaviors if needed.
2167 The ones listed here are static and global.
2168 @xref{targetconfiguration,,Target Configuration}, about configuring individual targets.
2169 @xref{targetevents,,Target Events}, about configuring target-specific event handling.
2171 @anchor{gdbbreakpointoverride}
2172 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
2173 Force breakpoint type for gdb @command{break} commands.
2174 This option supports GDB GUIs which don't
2175 distinguish hard versus soft breakpoints, if the default OpenOCD and
2176 GDB behaviour is not sufficient. GDB normally uses hardware
2177 breakpoints if the memory map has been set up for flash regions.
2180 @anchor{gdbflashprogram}
2181 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
2182 Set to @option{enable} to cause OpenOCD to program the flash memory when a
2183 vFlash packet is received.
2184 The default behaviour is @option{enable}.
2187 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
2188 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
2189 requested. GDB will then know when to set hardware breakpoints, and program flash
2190 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
2191 for flash programming to work.
2192 Default behaviour is @option{enable}.
2193 @xref{gdbflashprogram,,gdb_flash_program}.
2196 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
2197 Specifies whether data aborts cause an error to be reported
2198 by GDB memory read packets.
2199 The default behaviour is @option{disable};
2200 use @option{enable} see these errors reported.
2203 @deffn {Config Command} gdb_report_register_access_error (@option{enable}|@option{disable})
2204 Specifies whether register accesses requested by GDB register read/write
2205 packets report errors or not.
2206 The default behaviour is @option{disable};
2207 use @option{enable} see these errors reported.
2210 @deffn {Config Command} gdb_target_description (@option{enable}|@option{disable})
2211 Set to @option{enable} to cause OpenOCD to send the target descriptions to gdb via qXfer:features:read packet.
2212 The default behaviour is @option{enable}.
2215 @deffn {Command} gdb_save_tdesc
2216 Saves the target descripton file to the local file system.
2218 The file name is @i{target_name}.xml.
2221 @anchor{eventpolling}
2222 @section Event Polling
2224 Hardware debuggers are parts of asynchronous systems,
2225 where significant events can happen at any time.
2226 The OpenOCD server needs to detect some of these events,
2227 so it can report them to through TCL command line
2230 Examples of such events include:
2233 @item One of the targets can stop running ... maybe it triggers
2234 a code breakpoint or data watchpoint, or halts itself.
2235 @item Messages may be sent over ``debug message'' channels ... many
2236 targets support such messages sent over JTAG,
2237 for receipt by the person debugging or tools.
2238 @item Loss of power ... some adapters can detect these events.
2239 @item Resets not issued through JTAG ... such reset sources
2240 can include button presses or other system hardware, sometimes
2241 including the target itself (perhaps through a watchdog).
2242 @item Debug instrumentation sometimes supports event triggering
2243 such as ``trace buffer full'' (so it can quickly be emptied)
2244 or other signals (to correlate with code behavior).
2247 None of those events are signaled through standard JTAG signals.
2248 However, most conventions for JTAG connectors include voltage
2249 level and system reset (SRST) signal detection.
2250 Some connectors also include instrumentation signals, which
2251 can imply events when those signals are inputs.
2253 In general, OpenOCD needs to periodically check for those events,
2254 either by looking at the status of signals on the JTAG connector
2255 or by sending synchronous ``tell me your status'' JTAG requests
2256 to the various active targets.
2257 There is a command to manage and monitor that polling,
2258 which is normally done in the background.
2260 @deffn Command poll [@option{on}|@option{off}]
2261 Poll the current target for its current state.
2262 (Also, @pxref{targetcurstate,,target curstate}.)
2263 If that target is in debug mode, architecture
2264 specific information about the current state is printed.
2265 An optional parameter
2266 allows background polling to be enabled and disabled.
2268 You could use this from the TCL command shell, or
2269 from GDB using @command{monitor poll} command.
2270 Leave background polling enabled while you're using GDB.
2273 background polling: on
2274 target state: halted
2275 target halted in ARM state due to debug-request, \
2276 current mode: Supervisor
2277 cpsr: 0x800000d3 pc: 0x11081bfc
2278 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2283 @node Debug Adapter Configuration
2284 @chapter Debug Adapter Configuration
2285 @cindex config file, interface
2286 @cindex interface config file
2288 Correctly installing OpenOCD includes making your operating system give
2289 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2290 are used to select which one is used, and to configure how it is used.
2293 Because OpenOCD started out with a focus purely on JTAG, you may find
2294 places where it wrongly presumes JTAG is the only transport protocol
2295 in use. Be aware that recent versions of OpenOCD are removing that
2296 limitation. JTAG remains more functional than most other transports.
2297 Other transports do not support boundary scan operations, or may be
2298 specific to a given chip vendor. Some might be usable only for
2299 programming flash memory, instead of also for debugging.
2302 Debug Adapters/Interfaces/Dongles are normally configured
2303 through commands in an interface configuration
2304 file which is sourced by your @file{openocd.cfg} file, or
2305 through a command line @option{-f interface/....cfg} option.
2308 source [find interface/olimex-jtag-tiny.cfg]
2312 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2313 A few cases are so simple that you only need to say what driver to use:
2320 Most adapters need a bit more configuration than that.
2323 @section Interface Configuration
2325 The interface command tells OpenOCD what type of debug adapter you are
2326 using. Depending on the type of adapter, you may need to use one or
2327 more additional commands to further identify or configure the adapter.
2329 @deffn {Config Command} {interface} name
2330 Use the interface driver @var{name} to connect to the
2334 @deffn Command {interface_list}
2335 List the debug adapter drivers that have been built into
2336 the running copy of OpenOCD.
2338 @deffn Command {interface transports} transport_name+
2339 Specifies the transports supported by this debug adapter.
2340 The adapter driver builds-in similar knowledge; use this only
2341 when external configuration (such as jumpering) changes what
2342 the hardware can support.
2347 @deffn Command {adapter_name}
2348 Returns the name of the debug adapter driver being used.
2351 @section Interface Drivers
2353 Each of the interface drivers listed here must be explicitly
2354 enabled when OpenOCD is configured, in order to be made
2355 available at run time.
2357 @deffn {Interface Driver} {amt_jtagaccel}
2358 Amontec Chameleon in its JTAG Accelerator configuration,
2359 connected to a PC's EPP mode parallel port.
2360 This defines some driver-specific commands:
2362 @deffn {Config Command} {parport_port} number
2363 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2364 the number of the @file{/dev/parport} device.
2367 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
2368 Displays status of RTCK option.
2369 Optionally sets that option first.
2373 @deffn {Interface Driver} {arm-jtag-ew}
2374 Olimex ARM-JTAG-EW USB adapter
2375 This has one driver-specific command:
2377 @deffn Command {armjtagew_info}
2382 @deffn {Interface Driver} {at91rm9200}
2383 Supports bitbanged JTAG from the local system,
2384 presuming that system is an Atmel AT91rm9200
2385 and a specific set of GPIOs is used.
2386 @c command: at91rm9200_device NAME
2387 @c chooses among list of bit configs ... only one option
2390 @deffn {Interface Driver} {cmsis-dap}
2391 ARM CMSIS-DAP compliant based adapter.
2393 @deffn {Config Command} {cmsis_dap_vid_pid} [vid pid]+
2394 The vendor ID and product ID of the CMSIS-DAP device. If not specified
2395 the driver will attempt to auto detect the CMSIS-DAP device.
2396 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2398 cmsis_dap_vid_pid 0xc251 0xf001 0x0d28 0x0204
2402 @deffn {Config Command} {cmsis_dap_serial} [serial]
2403 Specifies the @var{serial} of the CMSIS-DAP device to use.
2404 If not specified, serial numbers are not considered.
2407 @deffn {Command} {cmsis-dap info}
2408 Display various device information, like hardware version, firmware version, current bus status.
2412 @deffn {Interface Driver} {dummy}
2413 A dummy software-only driver for debugging.
2416 @deffn {Interface Driver} {ep93xx}
2417 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2420 @deffn {Interface Driver} {ftdi}
2421 This driver is for adapters using the MPSSE (Multi-Protocol Synchronous Serial
2422 Engine) mode built into many FTDI chips, such as the FT2232, FT4232 and FT232H.
2424 The driver is using libusb-1.0 in asynchronous mode to talk to the FTDI device,
2425 bypassing intermediate libraries like libftdi or D2XX.
2427 Support for new FTDI based adapters can be added competely through
2428 configuration files, without the need to patch and rebuild OpenOCD.
2430 The driver uses a signal abstraction to enable Tcl configuration files to
2431 define outputs for one or several FTDI GPIO. These outputs can then be
2432 controlled using the @command{ftdi_set_signal} command. Special signal names
2433 are reserved for nTRST, nSRST and LED (for blink) so that they, if defined,
2434 will be used for their customary purpose. Inputs can be read using the
2435 @command{ftdi_get_signal} command.
2437 To support SWD, a signal named SWD_EN must be defined. It is set to 1 when the
2438 SWD protocol is selected. When set, the adapter should route the SWDIO pin to
2439 the data input. An SWDIO_OE signal, if defined, will be set to 1 or 0 as
2440 required by the protocol, to tell the adapter to drive the data output onto
2441 the SWDIO pin or keep the SWDIO pin Hi-Z, respectively.
2443 Depending on the type of buffer attached to the FTDI GPIO, the outputs have to
2444 be controlled differently. In order to support tristateable signals such as
2445 nSRST, both a data GPIO and an output-enable GPIO can be specified for each
2446 signal. The following output buffer configurations are supported:
2449 @item Push-pull with one FTDI output as (non-)inverted data line
2450 @item Open drain with one FTDI output as (non-)inverted output-enable
2451 @item Tristate with one FTDI output as (non-)inverted data line and another
2452 FTDI output as (non-)inverted output-enable
2453 @item Unbuffered, using the FTDI GPIO as a tristate output directly by
2454 switching data and direction as necessary
2457 These interfaces have several commands, used to configure the driver
2458 before initializing the JTAG scan chain:
2460 @deffn {Config Command} {ftdi_vid_pid} [vid pid]+
2461 The vendor ID and product ID of the adapter. Up to eight
2462 [@var{vid}, @var{pid}] pairs may be given, e.g.
2464 ftdi_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2468 @deffn {Config Command} {ftdi_device_desc} description
2469 Provides the USB device description (the @emph{iProduct string})
2470 of the adapter. If not specified, the device description is ignored
2471 during device selection.
2474 @deffn {Config Command} {ftdi_serial} serial-number
2475 Specifies the @var{serial-number} of the adapter to use,
2476 in case the vendor provides unique IDs and more than one adapter
2477 is connected to the host.
2478 If not specified, serial numbers are not considered.
2479 (Note that USB serial numbers can be arbitrary Unicode strings,
2480 and are not restricted to containing only decimal digits.)
2483 @deffn {Config Command} {ftdi_location} <bus>:<port>[,<port>]...
2484 Specifies the physical USB port of the adapter to use. The path
2485 roots at @var{bus} and walks down the physical ports, with each
2486 @var{port} option specifying a deeper level in the bus topology, the last
2487 @var{port} denoting where the target adapter is actually plugged.
2488 The USB bus topology can be queried with the command @emph{lsusb -t}.
2490 This command is only available if your libusb1 is at least version 1.0.16.
2493 @deffn {Config Command} {ftdi_channel} channel
2494 Selects the channel of the FTDI device to use for MPSSE operations. Most
2495 adapters use the default, channel 0, but there are exceptions.
2498 @deffn {Config Command} {ftdi_layout_init} data direction
2499 Specifies the initial values of the FTDI GPIO data and direction registers.
2500 Each value is a 16-bit number corresponding to the concatenation of the high
2501 and low FTDI GPIO registers. The values should be selected based on the
2502 schematics of the adapter, such that all signals are set to safe levels with
2503 minimal impact on the target system. Avoid floating inputs, conflicting outputs
2504 and initially asserted reset signals.
2507 @deffn {Config Command} {ftdi_layout_signal} name [@option{-data}|@option{-ndata} data_mask] [@option{-input}|@option{-ninput} input_mask] [@option{-oe}|@option{-noe} oe_mask] [@option{-alias}|@option{-nalias} name]
2508 Creates a signal with the specified @var{name}, controlled by one or more FTDI
2509 GPIO pins via a range of possible buffer connections. The masks are FTDI GPIO
2510 register bitmasks to tell the driver the connection and type of the output
2511 buffer driving the respective signal. @var{data_mask} is the bitmask for the
2512 pin(s) connected to the data input of the output buffer. @option{-ndata} is
2513 used with inverting data inputs and @option{-data} with non-inverting inputs.
2514 The @option{-oe} (or @option{-noe}) option tells where the output-enable (or
2515 not-output-enable) input to the output buffer is connected. The options
2516 @option{-input} and @option{-ninput} specify the bitmask for pins to be read
2517 with the method @command{ftdi_get_signal}.
2519 Both @var{data_mask} and @var{oe_mask} need not be specified. For example, a
2520 simple open-collector transistor driver would be specified with @option{-oe}
2521 only. In that case the signal can only be set to drive low or to Hi-Z and the
2522 driver will complain if the signal is set to drive high. Which means that if
2523 it's a reset signal, @command{reset_config} must be specified as
2524 @option{srst_open_drain}, not @option{srst_push_pull}.
2526 A special case is provided when @option{-data} and @option{-oe} is set to the
2527 same bitmask. Then the FTDI pin is considered being connected straight to the
2528 target without any buffer. The FTDI pin is then switched between output and
2529 input as necessary to provide the full set of low, high and Hi-Z
2530 characteristics. In all other cases, the pins specified in a signal definition
2531 are always driven by the FTDI.
2533 If @option{-alias} or @option{-nalias} is used, the signal is created
2534 identical (or with data inverted) to an already specified signal
2538 @deffn {Command} {ftdi_set_signal} name @option{0}|@option{1}|@option{z}
2539 Set a previously defined signal to the specified level.
2541 @item @option{0}, drive low
2542 @item @option{1}, drive high
2543 @item @option{z}, set to high-impedance
2547 @deffn {Command} {ftdi_get_signal} name
2548 Get the value of a previously defined signal.
2551 @deffn {Command} {ftdi_tdo_sample_edge} @option{rising}|@option{falling}
2552 Configure TCK edge at which the adapter samples the value of the TDO signal
2554 Due to signal propagation delays, sampling TDO on rising TCK can become quite
2555 peculiar at high JTAG clock speeds. However, FTDI chips offer a possiblity to sample
2556 TDO on falling edge of TCK. With some board/adapter configurations, this may increase
2557 stability at higher JTAG clocks.
2559 @item @option{rising}, sample TDO on rising edge of TCK - this is the default
2560 @item @option{falling}, sample TDO on falling edge of TCK
2564 For example adapter definitions, see the configuration files shipped in the
2565 @file{interface/ftdi} directory.
2569 @deffn {Interface Driver} {ft232r}
2570 This driver is implementing synchronous bitbang mode of an FTDI FT232R
2573 List of connections (pin numbers for SSOP):
2580 @item DCD(10) - SRST
2583 These interfaces have several commands, used to configure the driver
2584 before initializing the JTAG scan chain:
2586 @deffn {Config Command} {ft232r_vid_pid} @var{vid} @var{pid}
2587 The vendor ID and product ID of the adapter. If not specified, default
2588 0x0403:0x6001 is used.
2591 @deffn {Config Command} {ft232r_serial_desc} @var{serial}
2592 Specifies the @var{serial} of the adapter to use, in case the
2593 vendor provides unique IDs and more than one adapter is connected to
2594 the host. If not specified, serial numbers are not considered.
2599 @deffn {Interface Driver} {remote_bitbang}
2600 Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
2601 with a remote process and sends ASCII encoded bitbang requests to that process
2602 instead of directly driving JTAG.
2604 The remote_bitbang driver is useful for debugging software running on
2605 processors which are being simulated.
2607 @deffn {Config Command} {remote_bitbang_port} number
2608 Specifies the TCP port of the remote process to connect to or 0 to use UNIX
2609 sockets instead of TCP.
2612 @deffn {Config Command} {remote_bitbang_host} hostname
2613 Specifies the hostname of the remote process to connect to using TCP, or the
2614 name of the UNIX socket to use if remote_bitbang_port is 0.
2617 For example, to connect remotely via TCP to the host foobar you might have
2621 interface remote_bitbang
2622 remote_bitbang_port 3335
2623 remote_bitbang_host foobar
2626 To connect to another process running locally via UNIX sockets with socket
2630 interface remote_bitbang
2631 remote_bitbang_port 0
2632 remote_bitbang_host mysocket
2636 @deffn {Interface Driver} {usb_blaster}
2637 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2638 for FTDI chips. These interfaces have several commands, used to
2639 configure the driver before initializing the JTAG scan chain:
2641 @deffn {Config Command} {usb_blaster_device_desc} description
2642 Provides the USB device description (the @emph{iProduct string})
2643 of the FTDI FT245 device. If not
2644 specified, the FTDI default value is used. This setting is only valid
2645 if compiled with FTD2XX support.
2648 @deffn {Config Command} {usb_blaster_vid_pid} vid pid
2649 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2650 default values are used.
2651 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2652 Altera USB-Blaster (default):
2654 usb_blaster_vid_pid 0x09FB 0x6001
2656 The following VID/PID is for Kolja Waschk's USB JTAG:
2658 usb_blaster_vid_pid 0x16C0 0x06AD
2662 @deffn {Command} {usb_blaster_pin} (@option{pin6}|@option{pin8}) (@option{0}|@option{1}|@option{s}|@option{t})
2663 Sets the state or function of the unused GPIO pins on USB-Blasters
2664 (pins 6 and 8 on the female JTAG header). These pins can be used as
2665 SRST and/or TRST provided the appropriate connections are made on the
2668 For example, to use pin 6 as SRST:
2670 usb_blaster_pin pin6 s
2671 reset_config srst_only
2675 @deffn {Command} {usb_blaster_lowlevel_driver} (@option{ftdi}|@option{ublast2})
2676 Chooses the low level access method for the adapter. If not specified,
2677 @option{ftdi} is selected unless it wasn't enabled during the
2678 configure stage. USB-Blaster II needs @option{ublast2}.
2681 @deffn {Command} {usb_blaster_firmware} @var{path}
2682 This command specifies @var{path} to access USB-Blaster II firmware
2683 image. To be used with USB-Blaster II only.
2688 @deffn {Interface Driver} {gw16012}
2689 Gateworks GW16012 JTAG programmer.
2690 This has one driver-specific command:
2692 @deffn {Config Command} {parport_port} [port_number]
2693 Display either the address of the I/O port
2694 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2695 If a parameter is provided, first switch to use that port.
2696 This is a write-once setting.
2700 @deffn {Interface Driver} {jlink}
2701 SEGGER J-Link family of USB adapters. It currently supports JTAG and SWD
2704 @quotation Compatibility Note
2705 SEGGER released many firmware versions for the many harware versions they
2706 produced. OpenOCD was extensively tested and intended to run on all of them,
2707 but some combinations were reported as incompatible. As a general
2708 recommendation, it is advisable to use the latest firmware version
2709 available for each hardware version. However the current V8 is a moving
2710 target, and SEGGER firmware versions released after the OpenOCD was
2711 released may not be compatible. In such cases it is recommended to
2712 revert to the last known functional version. For 0.5.0, this is from
2713 "Feb 8 2012 14:30:39", packed with 4.42c. For 0.6.0, the last known
2714 version is from "May 3 2012 18:36:22", packed with 4.46f.
2717 @deffn {Command} {jlink hwstatus}
2718 Display various hardware related information, for example target voltage and pin
2721 @deffn {Command} {jlink freemem}
2722 Display free device internal memory.
2724 @deffn {Command} {jlink jtag} [@option{2}|@option{3}]
2725 Set the JTAG command version to be used. Without argument, show the actual JTAG
2728 @deffn {Command} {jlink config}
2729 Display the device configuration.
2731 @deffn {Command} {jlink config targetpower} [@option{on}|@option{off}]
2732 Set the target power state on JTAG-pin 19. Without argument, show the target
2735 @deffn {Command} {jlink config mac} [@option{ff:ff:ff:ff:ff:ff}]
2736 Set the MAC address of the device. Without argument, show the MAC address.
2738 @deffn {Command} {jlink config ip} [@option{A.B.C.D}(@option{/E}|@option{F.G.H.I})]
2739 Set the IP configuration of the device, where A.B.C.D is the IP address, E the
2740 bit of the subnet mask and F.G.H.I the subnet mask. Without arguments, show the
2743 @deffn {Command} {jlink config usb} [@option{0} to @option{3}]
2744 Set the USB address of the device. This will also change the USB Product ID
2745 (PID) of the device. Without argument, show the USB address.
2747 @deffn {Command} {jlink config reset}
2748 Reset the current configuration.
2750 @deffn {Command} {jlink config write}
2751 Write the current configuration to the internal persistent storage.
2753 @deffn {Command} {jlink emucom write <channel> <data>}
2754 Write data to an EMUCOM channel. The data needs to be encoded as hexadecimal
2757 The following example shows how to write the three bytes 0xaa, 0x0b and 0x23 to
2758 the EMUCOM channel 0x10:
2760 > jlink emucom write 0x10 aa0b23
2763 @deffn {Command} {jlink emucom read <channel> <length>}
2764 Read data from an EMUCOM channel. The read data is encoded as hexadecimal
2767 The following example shows how to read 4 bytes from the EMUCOM channel 0x0:
2769 > jlink emucom read 0x0 4
2773 @deffn {Config} {jlink usb} <@option{0} to @option{3}>
2774 Set the USB address of the interface, in case more than one adapter is connected
2775 to the host. If not specified, USB addresses are not considered. Device
2776 selection via USB address is deprecated and the serial number should be used
2779 As a configuration command, it can be used only before 'init'.
2781 @deffn {Config} {jlink serial} <serial number>
2782 Set the serial number of the interface, in case more than one adapter is
2783 connected to the host. If not specified, serial numbers are not considered.
2785 As a configuration command, it can be used only before 'init'.
2789 @deffn {Interface Driver} {kitprog}
2790 This driver is for Cypress Semiconductor's KitProg adapters. The KitProg is an
2791 SWD-only adapter that is designed to be used with Cypress's PSoC and PRoC device
2792 families, but it is possible to use it with some other devices. If you are using
2793 this adapter with a PSoC or a PRoC, you may need to add
2794 @command{kitprog_init_acquire_psoc} or @command{kitprog acquire_psoc} to your
2795 configuration script.
2797 Note that this driver is for the proprietary KitProg protocol, not the CMSIS-DAP
2798 mode introduced in firmware 2.14. If the KitProg is in CMSIS-DAP mode, it cannot
2799 be used with this driver, and must either be used with the cmsis-dap driver or
2800 switched back to KitProg mode. See the Cypress KitProg User Guide for
2801 instructions on how to switch KitProg modes.
2805 @item The frequency of SWCLK cannot be configured, and varies between 1.6 MHz
2807 @item For firmware versions below 2.14, "JTAG to SWD" sequences are replaced by
2808 "SWD line reset" in the driver. This is for two reasons. First, the KitProg does
2809 not support sending arbitrary SWD sequences, and only firmware 2.14 and later
2810 implement both "JTAG to SWD" and "SWD line reset" in firmware. Earlier firmware
2811 versions only implement "SWD line reset". Second, due to a firmware quirk, an
2812 SWD sequence must be sent after every target reset in order to re-establish
2813 communications with the target.
2814 @item Due in part to the limitation above, KitProg devices with firmware below
2815 version 2.14 will need to use @command{kitprog_init_acquire_psoc} in order to
2816 communicate with PSoC 5LP devices. This is because, assuming debug is not
2817 disabled on the PSoC, the PSoC 5LP needs its JTAG interface switched to SWD
2818 mode before communication can begin, but prior to firmware 2.14, "JTAG to SWD"
2819 could only be sent with an acquisition sequence.
2822 @deffn {Config Command} {kitprog_init_acquire_psoc}
2823 Indicate that a PSoC acquisition sequence needs to be run during adapter init.
2824 Please be aware that the acquisition sequence hard-resets the target.
2827 @deffn {Config Command} {kitprog_serial} serial
2828 Select a KitProg device by its @var{serial}. If left unspecified, the first
2829 device detected by OpenOCD will be used.
2832 @deffn {Command} {kitprog acquire_psoc}
2833 Run a PSoC acquisition sequence immediately. Typically, this should not be used
2834 outside of the target-specific configuration scripts since it hard-resets the
2835 target as a side-effect.
2836 This is necessary for "reset halt" on some PSoC 4 series devices.
2839 @deffn {Command} {kitprog info}
2840 Display various adapter information, such as the hardware version, firmware
2841 version, and target voltage.
2845 @deffn {Interface Driver} {parport}
2846 Supports PC parallel port bit-banging cables:
2847 Wigglers, PLD download cable, and more.
2848 These interfaces have several commands, used to configure the driver
2849 before initializing the JTAG scan chain:
2851 @deffn {Config Command} {parport_cable} name
2852 Set the layout of the parallel port cable used to connect to the target.
2853 This is a write-once setting.
2854 Currently valid cable @var{name} values include:
2857 @item @b{altium} Altium Universal JTAG cable.
2858 @item @b{arm-jtag} Same as original wiggler except SRST and
2859 TRST connections reversed and TRST is also inverted.
2860 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
2861 in configuration mode. This is only used to
2862 program the Chameleon itself, not a connected target.
2863 @item @b{dlc5} The Xilinx Parallel cable III.
2864 @item @b{flashlink} The ST Parallel cable.
2865 @item @b{lattice} Lattice ispDOWNLOAD Cable
2866 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
2868 Amontec's Chameleon Programmer. The new version available from
2869 the website uses the original Wiggler layout ('@var{wiggler}')
2870 @item @b{triton} The parallel port adapter found on the
2871 ``Karo Triton 1 Development Board''.
2872 This is also the layout used by the HollyGates design
2873 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
2874 @item @b{wiggler} The original Wiggler layout, also supported by
2875 several clones, such as the Olimex ARM-JTAG
2876 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
2877 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
2881 @deffn {Config Command} {parport_port} [port_number]
2882 Display either the address of the I/O port
2883 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2884 If a parameter is provided, first switch to use that port.
2885 This is a write-once setting.
2887 When using PPDEV to access the parallel port, use the number of the parallel port:
2888 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
2889 you may encounter a problem.
2892 @deffn Command {parport_toggling_time} [nanoseconds]
2893 Displays how many nanoseconds the hardware needs to toggle TCK;
2894 the parport driver uses this value to obey the
2895 @command{adapter_khz} configuration.
2896 When the optional @var{nanoseconds} parameter is given,
2897 that setting is changed before displaying the current value.
2899 The default setting should work reasonably well on commodity PC hardware.
2900 However, you may want to calibrate for your specific hardware.
2902 To measure the toggling time with a logic analyzer or a digital storage
2903 oscilloscope, follow the procedure below:
2905 > parport_toggling_time 1000
2908 This sets the maximum JTAG clock speed of the hardware, but
2909 the actual speed probably deviates from the requested 500 kHz.
2910 Now, measure the time between the two closest spaced TCK transitions.
2911 You can use @command{runtest 1000} or something similar to generate a
2912 large set of samples.
2913 Update the setting to match your measurement:
2915 > parport_toggling_time <measured nanoseconds>
2917 Now the clock speed will be a better match for @command{adapter_khz rate}
2918 commands given in OpenOCD scripts and event handlers.
2920 You can do something similar with many digital multimeters, but note
2921 that you'll probably need to run the clock continuously for several
2922 seconds before it decides what clock rate to show. Adjust the
2923 toggling time up or down until the measured clock rate is a good
2924 match for the adapter_khz rate you specified; be conservative.
2928 @deffn {Config Command} {parport_write_on_exit} (@option{on}|@option{off})
2929 This will configure the parallel driver to write a known
2930 cable-specific value to the parallel interface on exiting OpenOCD.
2933 For example, the interface configuration file for a
2934 classic ``Wiggler'' cable on LPT2 might look something like this:
2939 parport_cable wiggler
2943 @deffn {Interface Driver} {presto}
2944 ASIX PRESTO USB JTAG programmer.
2945 @deffn {Config Command} {presto_serial} serial_string
2946 Configures the USB serial number of the Presto device to use.
2950 @deffn {Interface Driver} {rlink}
2951 Raisonance RLink USB adapter
2954 @deffn {Interface Driver} {usbprog}
2955 usbprog is a freely programmable USB adapter.
2958 @deffn {Interface Driver} {vsllink}
2959 vsllink is part of Versaloon which is a versatile USB programmer.
2962 This defines quite a few driver-specific commands,
2963 which are not currently documented here.
2967 @anchor{hla_interface}
2968 @deffn {Interface Driver} {hla}
2969 This is a driver that supports multiple High Level Adapters.
2970 This type of adapter does not expose some of the lower level api's
2971 that OpenOCD would normally use to access the target.
2973 Currently supported adapters include the ST STLINK and TI ICDI.
2974 STLINK firmware version >= V2.J21.S4 recommended due to issues with earlier
2975 versions of firmware where serial number is reset after first use. Suggest
2976 using ST firmware update utility to upgrade STLINK firmware even if current
2977 version reported is V2.J21.S4.
2979 @deffn {Config Command} {hla_device_desc} description
2980 Currently Not Supported.
2983 @deffn {Config Command} {hla_serial} serial
2984 Specifies the serial number of the adapter.
2987 @deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi})
2988 Specifies the adapter layout to use.
2991 @deffn {Config Command} {hla_vid_pid} [vid pid]+
2992 Pairs of vendor IDs and product IDs of the device.
2995 @deffn {Command} {hla_command} command
2996 Execute a custom adapter-specific command. The @var{command} string is
2997 passed as is to the underlying adapter layout handler.
3001 @deffn {Interface Driver} {opendous}
3002 opendous-jtag is a freely programmable USB adapter.
3005 @deffn {Interface Driver} {ulink}
3006 This is the Keil ULINK v1 JTAG debugger.
3009 @deffn {Interface Driver} {ZY1000}
3010 This is the Zylin ZY1000 JTAG debugger.
3014 This defines some driver-specific commands,
3015 which are not currently documented here.
3018 @deffn Command power [@option{on}|@option{off}]
3019 Turn power switch to target on/off.
3020 No arguments: print status.
3023 @deffn {Interface Driver} {bcm2835gpio}
3024 This SoC is present in Raspberry Pi which is a cheap single-board computer
3025 exposing some GPIOs on its expansion header.
3027 The driver accesses memory-mapped GPIO peripheral registers directly
3028 for maximum performance, but the only possible race condition is for
3029 the pins' modes/muxing (which is highly unlikely), so it should be
3030 able to coexist nicely with both sysfs bitbanging and various
3031 peripherals' kernel drivers. The driver restores the previous
3032 configuration on exit.
3034 See @file{interface/raspberrypi-native.cfg} for a sample config and
3039 @deffn {Interface Driver} {imx_gpio}
3040 i.MX SoC is present in many community boards. Wandboard is an example
3041 of the one which is most popular.
3043 This driver is mostly the same as bcm2835gpio.
3045 See @file{interface/imx-native.cfg} for a sample config and
3051 @deffn {Interface Driver} {openjtag}
3052 OpenJTAG compatible USB adapter.
3053 This defines some driver-specific commands:
3055 @deffn {Config Command} {openjtag_variant} variant
3056 Specifies the variant of the OpenJTAG adapter (see @uref{http://www.openjtag.org/}).
3057 Currently valid @var{variant} values include:
3060 @item @b{standard} Standard variant (default).
3061 @item @b{cy7c65215} Cypress CY7C65215 Dual Channel USB-Serial Bridge Controller
3062 (see @uref{http://www.cypress.com/?rID=82870}).
3066 @deffn {Config Command} {openjtag_device_desc} string
3067 The USB device description string of the adapter.
3068 This value is only used with the standard variant.
3072 @section Transport Configuration
3074 As noted earlier, depending on the version of OpenOCD you use,
3075 and the debug adapter you are using,
3076 several transports may be available to
3077 communicate with debug targets (or perhaps to program flash memory).
3078 @deffn Command {transport list}
3079 displays the names of the transports supported by this
3083 @deffn Command {transport select} @option{transport_name}
3084 Select which of the supported transports to use in this OpenOCD session.
3086 When invoked with @option{transport_name}, attempts to select the named
3087 transport. The transport must be supported by the debug adapter
3088 hardware and by the version of OpenOCD you are using (including the
3091 If no transport has been selected and no @option{transport_name} is
3092 provided, @command{transport select} auto-selects the first transport
3093 supported by the debug adapter.
3095 @command{transport select} always returns the name of the session's selected
3099 @subsection JTAG Transport
3101 JTAG is the original transport supported by OpenOCD, and most
3102 of the OpenOCD commands support it.
3103 JTAG transports expose a chain of one or more Test Access Points (TAPs),
3104 each of which must be explicitly declared.
3105 JTAG supports both debugging and boundary scan testing.
3106 Flash programming support is built on top of debug support.
3108 JTAG transport is selected with the command @command{transport select
3109 jtag}. Unless your adapter uses @ref{hla_interface,the hla interface
3110 driver}, in which case the command is @command{transport select
3113 @subsection SWD Transport
3115 @cindex Serial Wire Debug
3116 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
3117 Debug Access Point (DAP, which must be explicitly declared.
3118 (SWD uses fewer signal wires than JTAG.)
3119 SWD is debug-oriented, and does not support boundary scan testing.
3120 Flash programming support is built on top of debug support.
3121 (Some processors support both JTAG and SWD.)
3123 SWD transport is selected with the command @command{transport select
3124 swd}. Unless your adapter uses @ref{hla_interface,the hla interface
3125 driver}, in which case the command is @command{transport select
3128 @deffn Command {swd newdap} ...
3129 Declares a single DAP which uses SWD transport.
3130 Parameters are currently the same as "jtag newtap" but this is
3133 @deffn Command {swd wcr trn prescale}
3134 Updates TRN (turnaraound delay) and prescaling.fields of the
3135 Wire Control Register (WCR).
3136 No parameters: displays current settings.
3139 @subsection SPI Transport
3141 @cindex Serial Peripheral Interface
3142 The Serial Peripheral Interface (SPI) is a general purpose transport
3143 which uses four wire signaling. Some processors use it as part of a
3144 solution for flash programming.
3148 JTAG clock setup is part of system setup.
3149 It @emph{does not belong with interface setup} since any interface
3150 only knows a few of the constraints for the JTAG clock speed.
3151 Sometimes the JTAG speed is
3152 changed during the target initialization process: (1) slow at
3153 reset, (2) program the CPU clocks, (3) run fast.
3154 Both the "slow" and "fast" clock rates are functions of the
3155 oscillators used, the chip, the board design, and sometimes
3156 power management software that may be active.
3158 The speed used during reset, and the scan chain verification which
3159 follows reset, can be adjusted using a @code{reset-start}
3160 target event handler.
3161 It can then be reconfigured to a faster speed by a
3162 @code{reset-init} target event handler after it reprograms those
3163 CPU clocks, or manually (if something else, such as a boot loader,
3164 sets up those clocks).
3165 @xref{targetevents,,Target Events}.
3166 When the initial low JTAG speed is a chip characteristic, perhaps
3167 because of a required oscillator speed, provide such a handler
3168 in the target config file.
3169 When that speed is a function of a board-specific characteristic
3170 such as which speed oscillator is used, it belongs in the board
3171 config file instead.
3172 In both cases it's safest to also set the initial JTAG clock rate
3173 to that same slow speed, so that OpenOCD never starts up using a
3174 clock speed that's faster than the scan chain can support.
3178 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
3181 If your system supports adaptive clocking (RTCK), configuring
3182 JTAG to use that is probably the most robust approach.
3183 However, it introduces delays to synchronize clocks; so it
3184 may not be the fastest solution.
3186 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
3187 instead of @command{adapter_khz}, but only for (ARM) cores and boards
3188 which support adaptive clocking.
3190 @deffn {Command} adapter_khz max_speed_kHz
3191 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
3192 JTAG interfaces usually support a limited number of
3193 speeds. The speed actually used won't be faster
3194 than the speed specified.
3196 Chip data sheets generally include a top JTAG clock rate.
3197 The actual rate is often a function of a CPU core clock,
3198 and is normally less than that peak rate.
3199 For example, most ARM cores accept at most one sixth of the CPU clock.
3201 Speed 0 (khz) selects RTCK method.
3202 @xref{faqrtck,,FAQ RTCK}.
3203 If your system uses RTCK, you won't need to change the
3204 JTAG clocking after setup.
3205 Not all interfaces, boards, or targets support ``rtck''.
3206 If the interface device can not
3207 support it, an error is returned when you try to use RTCK.
3210 @defun jtag_rclk fallback_speed_kHz
3211 @cindex adaptive clocking
3213 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
3214 If that fails (maybe the interface, board, or target doesn't
3215 support it), falls back to the specified frequency.
3217 # Fall back to 3mhz if RTCK is not supported
3222 @node Reset Configuration
3223 @chapter Reset Configuration
3224 @cindex Reset Configuration
3226 Every system configuration may require a different reset
3227 configuration. This can also be quite confusing.
3228 Resets also interact with @var{reset-init} event handlers,
3229 which do things like setting up clocks and DRAM, and
3230 JTAG clock rates. (@xref{jtagspeed,,JTAG Speed}.)
3231 They can also interact with JTAG routers.
3232 Please see the various board files for examples.
3235 To maintainers and integrators:
3236 Reset configuration touches several things at once.
3237 Normally the board configuration file
3238 should define it and assume that the JTAG adapter supports
3239 everything that's wired up to the board's JTAG connector.
3241 However, the target configuration file could also make note
3242 of something the silicon vendor has done inside the chip,
3243 which will be true for most (or all) boards using that chip.
3244 And when the JTAG adapter doesn't support everything, the
3245 user configuration file will need to override parts of
3246 the reset configuration provided by other files.
3249 @section Types of Reset
3251 There are many kinds of reset possible through JTAG, but
3252 they may not all work with a given board and adapter.
3253 That's part of why reset configuration can be error prone.
3257 @emph{System Reset} ... the @emph{SRST} hardware signal
3258 resets all chips connected to the JTAG adapter, such as processors,
3259 power management chips, and I/O controllers. Normally resets triggered
3260 with this signal behave exactly like pressing a RESET button.
3262 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
3263 just the TAP controllers connected to the JTAG adapter.
3264 Such resets should not be visible to the rest of the system; resetting a
3265 device's TAP controller just puts that controller into a known state.
3267 @emph{Emulation Reset} ... many devices can be reset through JTAG
3268 commands. These resets are often distinguishable from system
3269 resets, either explicitly (a "reset reason" register says so)
3270 or implicitly (not all parts of the chip get reset).
3272 @emph{Other Resets} ... system-on-chip devices often support
3273 several other types of reset.
3274 You may need to arrange that a watchdog timer stops
3275 while debugging, preventing a watchdog reset.
3276 There may be individual module resets.
3279 In the best case, OpenOCD can hold SRST, then reset
3280 the TAPs via TRST and send commands through JTAG to halt the
3281 CPU at the reset vector before the 1st instruction is executed.
3282 Then when it finally releases the SRST signal, the system is
3283 halted under debugger control before any code has executed.
3284 This is the behavior required to support the @command{reset halt}
3285 and @command{reset init} commands; after @command{reset init} a
3286 board-specific script might do things like setting up DRAM.
3287 (@xref{resetcommand,,Reset Command}.)
3289 @anchor{srstandtrstissues}
3290 @section SRST and TRST Issues
3292 Because SRST and TRST are hardware signals, they can have a
3293 variety of system-specific constraints. Some of the most
3298 @item @emph{Signal not available} ... Some boards don't wire
3299 SRST or TRST to the JTAG connector. Some JTAG adapters don't
3300 support such signals even if they are wired up.
3301 Use the @command{reset_config} @var{signals} options to say
3302 when either of those signals is not connected.
3303 When SRST is not available, your code might not be able to rely
3304 on controllers having been fully reset during code startup.
3305 Missing TRST is not a problem, since JTAG-level resets can
3306 be triggered using with TMS signaling.
3308 @item @emph{Signals shorted} ... Sometimes a chip, board, or
3309 adapter will connect SRST to TRST, instead of keeping them separate.
3310 Use the @command{reset_config} @var{combination} options to say
3311 when those signals aren't properly independent.
3313 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
3314 delay circuit, reset supervisor, or on-chip features can extend
3315 the effect of a JTAG adapter's reset for some time after the adapter
3316 stops issuing the reset. For example, there may be chip or board
3317 requirements that all reset pulses last for at least a
3318 certain amount of time; and reset buttons commonly have
3319 hardware debouncing.
3320 Use the @command{adapter_nsrst_delay} and @command{jtag_ntrst_delay}
3321 commands to say when extra delays are needed.
3323 @item @emph{Drive type} ... Reset lines often have a pullup
3324 resistor, letting the JTAG interface treat them as open-drain
3325 signals. But that's not a requirement, so the adapter may need
3326 to use push/pull output drivers.
3327 Also, with weak pullups it may be advisable to drive
3328 signals to both levels (push/pull) to minimize rise times.
3329 Use the @command{reset_config} @var{trst_type} and
3330 @var{srst_type} parameters to say how to drive reset signals.
3332 @item @emph{Special initialization} ... Targets sometimes need
3333 special JTAG initialization sequences to handle chip-specific
3334 issues (not limited to errata).
3335 For example, certain JTAG commands might need to be issued while
3336 the system as a whole is in a reset state (SRST active)
3337 but the JTAG scan chain is usable (TRST inactive).
3338 Many systems treat combined assertion of SRST and TRST as a
3339 trigger for a harder reset than SRST alone.
3340 Such custom reset handling is discussed later in this chapter.
3343 There can also be other issues.
3344 Some devices don't fully conform to the JTAG specifications.
3345 Trivial system-specific differences are common, such as
3346 SRST and TRST using slightly different names.
3347 There are also vendors who distribute key JTAG documentation for
3348 their chips only to developers who have signed a Non-Disclosure
3351 Sometimes there are chip-specific extensions like a requirement to use
3352 the normally-optional TRST signal (precluding use of JTAG adapters which
3353 don't pass TRST through), or needing extra steps to complete a TAP reset.
3355 In short, SRST and especially TRST handling may be very finicky,
3356 needing to cope with both architecture and board specific constraints.
3358 @section Commands for Handling Resets
3360 @deffn {Command} adapter_nsrst_assert_width milliseconds
3361 Minimum amount of time (in milliseconds) OpenOCD should wait
3362 after asserting nSRST (active-low system reset) before
3363 allowing it to be deasserted.
3366 @deffn {Command} adapter_nsrst_delay milliseconds
3367 How long (in milliseconds) OpenOCD should wait after deasserting
3368 nSRST (active-low system reset) before starting new JTAG operations.
3369 When a board has a reset button connected to SRST line it will
3370 probably have hardware debouncing, implying you should use this.
3373 @deffn {Command} jtag_ntrst_assert_width milliseconds
3374 Minimum amount of time (in milliseconds) OpenOCD should wait
3375 after asserting nTRST (active-low JTAG TAP reset) before
3376 allowing it to be deasserted.
3379 @deffn {Command} jtag_ntrst_delay milliseconds
3380 How long (in milliseconds) OpenOCD should wait after deasserting
3381 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
3384 @deffn {Command} reset_config mode_flag ...
3385 This command displays or modifies the reset configuration
3386 of your combination of JTAG board and target in target
3387 configuration scripts.
3389 Information earlier in this section describes the kind of problems
3390 the command is intended to address (@pxref{srstandtrstissues,,SRST and TRST Issues}).
3391 As a rule this command belongs only in board config files,
3392 describing issues like @emph{board doesn't connect TRST};
3393 or in user config files, addressing limitations derived
3394 from a particular combination of interface and board.
3395 (An unlikely example would be using a TRST-only adapter
3396 with a board that only wires up SRST.)
3398 The @var{mode_flag} options can be specified in any order, but only one
3399 of each type -- @var{signals}, @var{combination}, @var{gates},
3400 @var{trst_type}, @var{srst_type} and @var{connect_type}
3401 -- may be specified at a time.
3402 If you don't provide a new value for a given type, its previous
3403 value (perhaps the default) is unchanged.
3404 For example, this means that you don't need to say anything at all about
3405 TRST just to declare that if the JTAG adapter should want to drive SRST,
3406 it must explicitly be driven high (@option{srst_push_pull}).
3410 @var{signals} can specify which of the reset signals are connected.
3411 For example, If the JTAG interface provides SRST, but the board doesn't
3412 connect that signal properly, then OpenOCD can't use it.
3413 Possible values are @option{none} (the default), @option{trst_only},
3414 @option{srst_only} and @option{trst_and_srst}.
3417 If your board provides SRST and/or TRST through the JTAG connector,
3418 you must declare that so those signals can be used.
3422 The @var{combination} is an optional value specifying broken reset
3423 signal implementations.
3424 The default behaviour if no option given is @option{separate},
3425 indicating everything behaves normally.
3426 @option{srst_pulls_trst} states that the
3427 test logic is reset together with the reset of the system (e.g. NXP
3428 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
3429 the system is reset together with the test logic (only hypothetical, I
3430 haven't seen hardware with such a bug, and can be worked around).
3431 @option{combined} implies both @option{srst_pulls_trst} and
3432 @option{trst_pulls_srst}.
3435 The @var{gates} tokens control flags that describe some cases where
3436 JTAG may be unvailable during reset.
3437 @option{srst_gates_jtag} (default)
3438 indicates that asserting SRST gates the
3439 JTAG clock. This means that no communication can happen on JTAG
3440 while SRST is asserted.
3441 Its converse is @option{srst_nogate}, indicating that JTAG commands
3442 can safely be issued while SRST is active.
3445 The @var{connect_type} tokens control flags that describe some cases where
3446 SRST is asserted while connecting to the target. @option{srst_nogate}
3447 is required to use this option.
3448 @option{connect_deassert_srst} (default)
3449 indicates that SRST will not be asserted while connecting to the target.
3450 Its converse is @option{connect_assert_srst}, indicating that SRST will
3451 be asserted before any target connection.
3452 Only some targets support this feature, STM32 and STR9 are examples.
3453 This feature is useful if you are unable to connect to your target due
3454 to incorrect options byte config or illegal program execution.
3457 The optional @var{trst_type} and @var{srst_type} parameters allow the
3458 driver mode of each reset line to be specified. These values only affect
3459 JTAG interfaces with support for different driver modes, like the Amontec
3460 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
3461 relevant signal (TRST or SRST) is not connected.
3465 Possible @var{trst_type} driver modes for the test reset signal (TRST)
3466 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
3467 Most boards connect this signal to a pulldown, so the JTAG TAPs
3468 never leave reset unless they are hooked up to a JTAG adapter.
3471 Possible @var{srst_type} driver modes for the system reset signal (SRST)
3472 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
3473 Most boards connect this signal to a pullup, and allow the
3474 signal to be pulled low by various events including system
3475 powerup and pressing a reset button.
3479 @section Custom Reset Handling
3482 OpenOCD has several ways to help support the various reset
3483 mechanisms provided by chip and board vendors.
3484 The commands shown in the previous section give standard parameters.
3485 There are also @emph{event handlers} associated with TAPs or Targets.
3486 Those handlers are Tcl procedures you can provide, which are invoked
3487 at particular points in the reset sequence.
3489 @emph{When SRST is not an option} you must set
3490 up a @code{reset-assert} event handler for your target.
3491 For example, some JTAG adapters don't include the SRST signal;
3492 and some boards have multiple targets, and you won't always
3493 want to reset everything at once.
3495 After configuring those mechanisms, you might still
3496 find your board doesn't start up or reset correctly.
3497 For example, maybe it needs a slightly different sequence
3498 of SRST and/or TRST manipulations, because of quirks that
3499 the @command{reset_config} mechanism doesn't address;
3500 or asserting both might trigger a stronger reset, which
3501 needs special attention.
3503 Experiment with lower level operations, such as @command{jtag_reset}
3504 and the @command{jtag arp_*} operations shown here,
3505 to find a sequence of operations that works.
3506 @xref{JTAG Commands}.
3507 When you find a working sequence, it can be used to override
3508 @command{jtag_init}, which fires during OpenOCD startup
3509 (@pxref{configurationstage,,Configuration Stage});
3510 or @command{init_reset}, which fires during reset processing.
3512 You might also want to provide some project-specific reset
3513 schemes. For example, on a multi-target board the standard
3514 @command{reset} command would reset all targets, but you
3515 may need the ability to reset only one target at time and
3516 thus want to avoid using the board-wide SRST signal.
3518 @deffn {Overridable Procedure} init_reset mode
3519 This is invoked near the beginning of the @command{reset} command,
3520 usually to provide as much of a cold (power-up) reset as practical.
3521 By default it is also invoked from @command{jtag_init} if
3522 the scan chain does not respond to pure JTAG operations.
3523 The @var{mode} parameter is the parameter given to the
3524 low level reset command (@option{halt},
3525 @option{init}, or @option{run}), @option{setup},
3526 or potentially some other value.
3528 The default implementation just invokes @command{jtag arp_init-reset}.
3529 Replacements will normally build on low level JTAG
3530 operations such as @command{jtag_reset}.
3531 Operations here must not address individual TAPs
3532 (or their associated targets)
3533 until the JTAG scan chain has first been verified to work.
3535 Implementations must have verified the JTAG scan chain before
3537 This is done by calling @command{jtag arp_init}
3538 (or @command{jtag arp_init-reset}).
3541 @deffn Command {jtag arp_init}
3542 This validates the scan chain using just the four
3543 standard JTAG signals (TMS, TCK, TDI, TDO).
3544 It starts by issuing a JTAG-only reset.
3545 Then it performs checks to verify that the scan chain configuration
3546 matches the TAPs it can observe.
3547 Those checks include checking IDCODE values for each active TAP,
3548 and verifying the length of their instruction registers using
3549 TAP @code{-ircapture} and @code{-irmask} values.
3550 If these tests all pass, TAP @code{setup} events are
3551 issued to all TAPs with handlers for that event.
3554 @deffn Command {jtag arp_init-reset}
3555 This uses TRST and SRST to try resetting
3556 everything on the JTAG scan chain
3557 (and anything else connected to SRST).
3558 It then invokes the logic of @command{jtag arp_init}.
3562 @node TAP Declaration
3563 @chapter TAP Declaration
3564 @cindex TAP declaration
3565 @cindex TAP configuration
3567 @emph{Test Access Ports} (TAPs) are the core of JTAG.
3568 TAPs serve many roles, including:
3571 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target.
3572 @item @b{Flash Programming} Some chips program the flash directly via JTAG.
3573 Others do it indirectly, making a CPU do it.
3574 @item @b{Program Download} Using the same CPU support GDB uses,
3575 you can initialize a DRAM controller, download code to DRAM, and then
3576 start running that code.
3577 @item @b{Boundary Scan} Most chips support boundary scan, which
3578 helps test for board assembly problems like solder bridges
3579 and missing connections.
3582 OpenOCD must know about the active TAPs on your board(s).
3583 Setting up the TAPs is the core task of your configuration files.
3584 Once those TAPs are set up, you can pass their names to code
3585 which sets up CPUs and exports them as GDB targets,
3586 probes flash memory, performs low-level JTAG operations, and more.
3588 @section Scan Chains
3591 TAPs are part of a hardware @dfn{scan chain},
3592 which is a daisy chain of TAPs.
3593 They also need to be added to
3594 OpenOCD's software mirror of that hardware list,
3595 giving each member a name and associating other data with it.
3596 Simple scan chains, with a single TAP, are common in
3597 systems with a single microcontroller or microprocessor.
3598 More complex chips may have several TAPs internally.
3599 Very complex scan chains might have a dozen or more TAPs:
3600 several in one chip, more in the next, and connecting
3601 to other boards with their own chips and TAPs.
3603 You can display the list with the @command{scan_chain} command.
3604 (Don't confuse this with the list displayed by the @command{targets}
3605 command, presented in the next chapter.
3606 That only displays TAPs for CPUs which are configured as
3608 Here's what the scan chain might look like for a chip more than one TAP:
3611 TapName Enabled IdCode Expected IrLen IrCap IrMask
3612 -- ------------------ ------- ---------- ---------- ----- ----- ------
3613 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
3614 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
3615 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
3618 OpenOCD can detect some of that information, but not all
3619 of it. @xref{autoprobing,,Autoprobing}.
3620 Unfortunately, those TAPs can't always be autoconfigured,
3621 because not all devices provide good support for that.
3622 JTAG doesn't require supporting IDCODE instructions, and
3623 chips with JTAG routers may not link TAPs into the chain
3624 until they are told to do so.
3626 The configuration mechanism currently supported by OpenOCD
3627 requires explicit configuration of all TAP devices using
3628 @command{jtag newtap} commands, as detailed later in this chapter.
3629 A command like this would declare one tap and name it @code{chip1.cpu}:
3632 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
3635 Each target configuration file lists the TAPs provided
3637 Board configuration files combine all the targets on a board,
3639 Note that @emph{the order in which TAPs are declared is very important.}
3640 That declaration order must match the order in the JTAG scan chain,
3641 both inside a single chip and between them.
3642 @xref{faqtaporder,,FAQ TAP Order}.
3644 For example, the ST Microsystems STR912 chip has
3645 three separate TAPs@footnote{See the ST
3646 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
3647 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
3648 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
3649 To configure those taps, @file{target/str912.cfg}
3650 includes commands something like this:
3653 jtag newtap str912 flash ... params ...
3654 jtag newtap str912 cpu ... params ...
3655 jtag newtap str912 bs ... params ...
3658 Actual config files typically use a variable such as @code{$_CHIPNAME}
3659 instead of literals like @option{str912}, to support more than one chip
3660 of each type. @xref{Config File Guidelines}.
3662 @deffn Command {jtag names}
3663 Returns the names of all current TAPs in the scan chain.
3664 Use @command{jtag cget} or @command{jtag tapisenabled}
3665 to examine attributes and state of each TAP.
3667 foreach t [jtag names] @{
3668 puts [format "TAP: %s\n" $t]
3673 @deffn Command {scan_chain}
3674 Displays the TAPs in the scan chain configuration,
3676 The set of TAPs listed by this command is fixed by
3677 exiting the OpenOCD configuration stage,
3678 but systems with a JTAG router can
3679 enable or disable TAPs dynamically.
3682 @c FIXME! "jtag cget" should be able to return all TAP
3683 @c attributes, like "$target_name cget" does for targets.
3685 @c Probably want "jtag eventlist", and a "tap-reset" event
3686 @c (on entry to RESET state).
3691 When TAP objects are declared with @command{jtag newtap},
3692 a @dfn{dotted.name} is created for the TAP, combining the
3693 name of a module (usually a chip) and a label for the TAP.
3694 For example: @code{xilinx.tap}, @code{str912.flash},
3695 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
3696 Many other commands use that dotted.name to manipulate or
3697 refer to the TAP. For example, CPU configuration uses the
3698 name, as does declaration of NAND or NOR flash banks.
3700 The components of a dotted name should follow ``C'' symbol
3701 name rules: start with an alphabetic character, then numbers
3702 and underscores are OK; while others (including dots!) are not.
3704 @section TAP Declaration Commands
3706 @c shouldn't this be(come) a {Config Command}?
3707 @deffn Command {jtag newtap} chipname tapname configparams...
3708 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
3709 and configured according to the various @var{configparams}.
3711 The @var{chipname} is a symbolic name for the chip.
3712 Conventionally target config files use @code{$_CHIPNAME},
3713 defaulting to the model name given by the chip vendor but
3716 @cindex TAP naming convention
3717 The @var{tapname} reflects the role of that TAP,
3718 and should follow this convention:
3721 @item @code{bs} -- For boundary scan if this is a separate TAP;
3722 @item @code{cpu} -- The main CPU of the chip, alternatively
3723 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
3724 @code{arm1} and @code{arm2} on chips with two ARMs, and so forth;
3725 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
3726 @item @code{flash} -- If the chip has a flash TAP, like the str912;
3727 @item @code{jrc} -- For JTAG route controller (example: the ICEPick modules
3728 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
3729 @item @code{tap} -- Should be used only for FPGA- or CPLD-like devices
3731 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
3732 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
3733 For example, the Freescale i.MX31 has a SDMA (Smart DMA) with
3734 a JTAG TAP; that TAP should be named @code{sdma}.
3737 Every TAP requires at least the following @var{configparams}:
3740 @item @code{-irlen} @var{NUMBER}
3741 @*The length in bits of the
3742 instruction register, such as 4 or 5 bits.
3745 A TAP may also provide optional @var{configparams}:
3748 @item @code{-disable} (or @code{-enable})
3749 @*Use the @code{-disable} parameter to flag a TAP which is not
3750 linked into the scan chain after a reset using either TRST
3751 or the JTAG state machine's @sc{reset} state.
3752 You may use @code{-enable} to highlight the default state
3753 (the TAP is linked in).
3754 @xref{enablinganddisablingtaps,,Enabling and Disabling TAPs}.
3755 @item @code{-expected-id} @var{NUMBER}
3756 @*A non-zero @var{number} represents a 32-bit IDCODE
3757 which you expect to find when the scan chain is examined.
3758 These codes are not required by all JTAG devices.
3759 @emph{Repeat the option} as many times as required if more than one
3760 ID code could appear (for example, multiple versions).
3761 Specify @var{number} as zero to suppress warnings about IDCODE
3762 values that were found but not included in the list.
3764 Provide this value if at all possible, since it lets OpenOCD
3765 tell when the scan chain it sees isn't right. These values
3766 are provided in vendors' chip documentation, usually a technical
3767 reference manual. Sometimes you may need to probe the JTAG
3768 hardware to find these values.
3769 @xref{autoprobing,,Autoprobing}.
3770 @item @code{-ignore-version}
3771 @*Specify this to ignore the JTAG version field in the @code{-expected-id}
3772 option. When vendors put out multiple versions of a chip, or use the same
3773 JTAG-level ID for several largely-compatible chips, it may be more practical
3774 to ignore the version field than to update config files to handle all of
3775 the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
3776 @item @code{-ircapture} @var{NUMBER}
3777 @*The bit pattern loaded by the TAP into the JTAG shift register
3778 on entry to the @sc{ircapture} state, such as 0x01.
3779 JTAG requires the two LSBs of this value to be 01.
3780 By default, @code{-ircapture} and @code{-irmask} are set
3781 up to verify that two-bit value. You may provide
3782 additional bits if you know them, or indicate that
3783 a TAP doesn't conform to the JTAG specification.
3784 @item @code{-irmask} @var{NUMBER}
3785 @*A mask used with @code{-ircapture}
3786 to verify that instruction scans work correctly.
3787 Such scans are not used by OpenOCD except to verify that
3788 there seems to be no problems with JTAG scan chain operations.
3789 @item @code{-ignore-syspwrupack}
3790 @*Specify this to ignore the CSYSPWRUPACK bit in the ARM DAP DP CTRL/STAT
3791 register during initial examination and when checking the sticky error bit.
3792 This bit is normally checked after setting the CSYSPWRUPREQ bit, but some
3793 devices do not set the ack bit until sometime later.
3797 @section Other TAP commands
3799 @deffn Command {jtag cget} dotted.name @option{-event} event_name
3800 @deffnx Command {jtag configure} dotted.name @option{-event} event_name handler
3801 At this writing this TAP attribute
3802 mechanism is used only for event handling.
3803 (It is not a direct analogue of the @code{cget}/@code{configure}
3804 mechanism for debugger targets.)
3805 See the next section for information about the available events.
3807 The @code{configure} subcommand assigns an event handler,
3808 a TCL string which is evaluated when the event is triggered.
3809 The @code{cget} subcommand returns that handler.
3816 OpenOCD includes two event mechanisms.
3817 The one presented here applies to all JTAG TAPs.
3818 The other applies to debugger targets,
3819 which are associated with certain TAPs.
3821 The TAP events currently defined are:
3824 @item @b{post-reset}
3825 @* The TAP has just completed a JTAG reset.
3826 The tap may still be in the JTAG @sc{reset} state.
3827 Handlers for these events might perform initialization sequences
3828 such as issuing TCK cycles, TMS sequences to ensure
3829 exit from the ARM SWD mode, and more.
3831 Because the scan chain has not yet been verified, handlers for these events
3832 @emph{should not issue commands which scan the JTAG IR or DR registers}
3833 of any particular target.
3834 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
3836 @* The scan chain has been reset and verified.
3837 This handler may enable TAPs as needed.
3838 @item @b{tap-disable}
3839 @* The TAP needs to be disabled. This handler should
3840 implement @command{jtag tapdisable}
3841 by issuing the relevant JTAG commands.
3842 @item @b{tap-enable}
3843 @* The TAP needs to be enabled. This handler should
3844 implement @command{jtag tapenable}
3845 by issuing the relevant JTAG commands.
3848 If you need some action after each JTAG reset which isn't actually
3849 specific to any TAP (since you can't yet trust the scan chain's
3850 contents to be accurate), you might:
3853 jtag configure CHIP.jrc -event post-reset @{
3854 echo "JTAG Reset done"
3855 ... non-scan jtag operations to be done after reset
3860 @anchor{enablinganddisablingtaps}
3861 @section Enabling and Disabling TAPs
3862 @cindex JTAG Route Controller
3865 In some systems, a @dfn{JTAG Route Controller} (JRC)
3866 is used to enable and/or disable specific JTAG TAPs.
3867 Many ARM-based chips from Texas Instruments include
3868 an ``ICEPick'' module, which is a JRC.
3869 Such chips include DaVinci and OMAP3 processors.
3871 A given TAP may not be visible until the JRC has been
3872 told to link it into the scan chain; and if the JRC
3873 has been told to unlink that TAP, it will no longer
3875 Such routers address problems that JTAG ``bypass mode''
3879 @item The scan chain can only go as fast as its slowest TAP.
3880 @item Having many TAPs slows instruction scans, since all
3881 TAPs receive new instructions.
3882 @item TAPs in the scan chain must be powered up, which wastes
3883 power and prevents debugging some power management mechanisms.
3886 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
3887 as implied by the existence of JTAG routers.
3888 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
3889 does include a kind of JTAG router functionality.
3891 @c (a) currently the event handlers don't seem to be able to
3892 @c fail in a way that could lead to no-change-of-state.
3894 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
3895 shown below, and is implemented using TAP event handlers.
3896 So for example, when defining a TAP for a CPU connected to
3897 a JTAG router, your @file{target.cfg} file
3898 should define TAP event handlers using
3899 code that looks something like this:
3902 jtag configure CHIP.cpu -event tap-enable @{
3903 ... jtag operations using CHIP.jrc
3905 jtag configure CHIP.cpu -event tap-disable @{
3906 ... jtag operations using CHIP.jrc
3910 Then you might want that CPU's TAP enabled almost all the time:
3913 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
3916 Note how that particular setup event handler declaration
3917 uses quotes to evaluate @code{$CHIP} when the event is configured.
3918 Using brackets @{ @} would cause it to be evaluated later,
3919 at runtime, when it might have a different value.
3921 @deffn Command {jtag tapdisable} dotted.name
3922 If necessary, disables the tap
3923 by sending it a @option{tap-disable} event.
3924 Returns the string "1" if the tap
3925 specified by @var{dotted.name} is enabled,
3926 and "0" if it is disabled.
3929 @deffn Command {jtag tapenable} dotted.name
3930 If necessary, enables the tap
3931 by sending it a @option{tap-enable} event.
3932 Returns the string "1" if the tap
3933 specified by @var{dotted.name} is enabled,
3934 and "0" if it is disabled.
3937 @deffn Command {jtag tapisenabled} dotted.name
3938 Returns the string "1" if the tap
3939 specified by @var{dotted.name} is enabled,
3940 and "0" if it is disabled.
3943 Humans will find the @command{scan_chain} command more helpful
3944 for querying the state of the JTAG taps.
3948 @anchor{autoprobing}
3949 @section Autoprobing
3951 @cindex JTAG autoprobe
3953 TAP configuration is the first thing that needs to be done
3954 after interface and reset configuration. Sometimes it's
3955 hard finding out what TAPs exist, or how they are identified.
3956 Vendor documentation is not always easy to find and use.
3958 To help you get past such problems, OpenOCD has a limited
3959 @emph{autoprobing} ability to look at the scan chain, doing
3960 a @dfn{blind interrogation} and then reporting the TAPs it finds.
3961 To use this mechanism, start the OpenOCD server with only data
3962 that configures your JTAG interface, and arranges to come up
3963 with a slow clock (many devices don't support fast JTAG clocks
3964 right when they come out of reset).
3966 For example, your @file{openocd.cfg} file might have:
3969 source [find interface/olimex-arm-usb-tiny-h.cfg]
3970 reset_config trst_and_srst
3974 When you start the server without any TAPs configured, it will
3975 attempt to autoconfigure the TAPs. There are two parts to this:
3978 @item @emph{TAP discovery} ...
3979 After a JTAG reset (sometimes a system reset may be needed too),
3980 each TAP's data registers will hold the contents of either the
3981 IDCODE or BYPASS register.
3982 If JTAG communication is working, OpenOCD will see each TAP,
3983 and report what @option{-expected-id} to use with it.
3984 @item @emph{IR Length discovery} ...
3985 Unfortunately JTAG does not provide a reliable way to find out
3986 the value of the @option{-irlen} parameter to use with a TAP
3988 If OpenOCD can discover the length of a TAP's instruction
3989 register, it will report it.
3990 Otherwise you may need to consult vendor documentation, such
3991 as chip data sheets or BSDL files.
3994 In many cases your board will have a simple scan chain with just
3995 a single device. Here's what OpenOCD reported with one board
3996 that's a bit more complex:
4000 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
4001 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
4002 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
4003 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
4004 AUTO auto0.tap - use "... -irlen 4"
4005 AUTO auto1.tap - use "... -irlen 4"
4006 AUTO auto2.tap - use "... -irlen 6"
4007 no gdb ports allocated as no target has been specified
4010 Given that information, you should be able to either find some existing
4011 config files to use, or create your own. If you create your own, you
4012 would configure from the bottom up: first a @file{target.cfg} file
4013 with these TAPs, any targets associated with them, and any on-chip
4014 resources; then a @file{board.cfg} with off-chip resources, clocking,
4017 @anchor{dapdeclaration}
4018 @section DAP declaration (ARMv7 and ARMv8 targets)
4019 @cindex DAP declaration
4021 Since OpenOCD version 0.11.0, the Debug Access Port (DAP) is
4022 no longer implicitly created together with the target. It must be
4023 explicitly declared using the @command{dap create} command. For all
4024 ARMv7 and ARMv8 targets, the option "@option{-dap} @var{dap_name}" has to be used
4025 instead of "@option{-chain-position} @var{dotted.name}" when the target is created.
4027 The @command{dap} command group supports the following sub-commands:
4029 @deffn Command {dap create} dap_name @option{-chain-position} dotted.name configparams...
4030 Declare a DAP instance named @var{dap_name} linked to the JTAG tap
4031 @var{dotted.name}. This also creates a new command (@command{dap_name})
4032 which is used for various purposes including additional configuration.
4033 There can only be one DAP for each JTAG tap in the system.
4035 A DAP may also provide optional @var{configparams}:
4038 @item @code{-ignore-syspwrupack}
4039 @*Specify this to ignore the CSYSPWRUPACK bit in the ARM DAP DP CTRL/STAT
4040 register during initial examination and when checking the sticky error bit.
4041 This bit is normally checked after setting the CSYSPWRUPREQ bit, but some
4042 devices do not set the ack bit until sometime later.
4046 @deffn Command {dap names}
4047 This command returns a list of all registered DAP objects. It it useful mainly
4051 @deffn Command {dap info} [num]
4052 Displays the ROM table for MEM-AP @var{num},
4053 defaulting to the currently selected AP of the currently selected target.
4056 @deffn Command {dap init}
4057 Initialize all registered DAPs. This command is used internally
4058 during initialization. It can be issued at any time after the
4059 initialization, too.
4062 The following commands exist as subcommands of DAP instances:
4064 @deffn Command {$dap_name info} [num]
4065 Displays the ROM table for MEM-AP @var{num},
4066 defaulting to the currently selected AP.
4069 @deffn Command {$dap_name apid} [num]
4070 Displays ID register from AP @var{num}, defaulting to the currently selected AP.
4073 @anchor{DAP subcommand apreg}
4074 @deffn Command {$dap_name apreg} ap_num reg [value]
4075 Displays content of a register @var{reg} from AP @var{ap_num}
4076 or set a new value @var{value}.
4077 @var{reg} is byte address of a word register, 0, 4, 8 ... 0xfc.
4080 @deffn Command {$dap_name apsel} [num]
4081 Select AP @var{num}, defaulting to 0.
4084 @deffn Command {$dap_name baseaddr} [num]
4085 Displays debug base address from MEM-AP @var{num},
4086 defaulting to the currently selected AP.
4089 @deffn Command {$dap_name memaccess} [value]
4090 Displays the number of extra tck cycles in the JTAG idle to use for MEM-AP
4091 memory bus access [0-255], giving additional time to respond to reads.
4092 If @var{value} is defined, first assigns that.
4095 @deffn Command {$dap_name apcsw} [value [mask]]
4096 Displays or changes CSW bit pattern for MEM-AP transfers.
4098 At the begin of each memory access the CSW pattern is extended (bitwise or-ed)
4099 by @dfn{Size} and @dfn{AddrInc} bit-fields according to transfer requirements
4100 and the result is written to the real CSW register. All bits except dynamically
4101 updated fields @dfn{Size} and @dfn{AddrInc} can be changed by changing
4102 the CSW pattern. Refer to ARM ADI v5 manual chapter 7.6.4 and appendix A
4105 Use @var{value} only syntax if you want to set the new CSW pattern as a whole.
4106 The example sets HPROT1 bit (required by Cortex-M) and clears the rest of
4109 kx.dap apcsw 0x2000000
4112 If @var{mask} is also used, the CSW pattern is changed only on bit positions
4113 where the mask bit is 1. The following example sets HPROT3 (cacheable)
4114 and leaves the rest of the pattern intact. It configures memory access through
4115 DCache on Cortex-M7.
4117 set CSW_HPROT3_CACHEABLE [expr 1 << 27]
4118 samv.dap apcsw $CSW_HPROT3_CACHEABLE $CSW_HPROT3_CACHEABLE
4121 Another example clears SPROT bit and leaves the rest of pattern intact:
4123 set CSW_SPROT [expr 1 << 30]
4124 samv.dap apcsw 0 $CSW_SPROT
4127 @emph{Note:} If you want to check the real value of CSW, not CSW pattern, use
4128 @code{xxx.dap apreg 0}. @xref{DAP subcommand apreg,,}.
4130 @emph{Warning:} Some of the CSW bits are vital for working memory transfer.
4131 If you set a wrong CSW pattern and MEM-AP stopped working, use the following
4132 example with a proper dap name:
4134 xxx.dap apcsw default
4138 @deffn Command {$dap_name ti_be_32_quirks} [@option{enable}]
4139 Set/get quirks mode for TI TMS450/TMS570 processors
4144 @node CPU Configuration
4145 @chapter CPU Configuration
4148 This chapter discusses how to set up GDB debug targets for CPUs.
4149 You can also access these targets without GDB
4150 (@pxref{Architecture and Core Commands},
4151 and @ref{targetstatehandling,,Target State handling}) and
4152 through various kinds of NAND and NOR flash commands.
4153 If you have multiple CPUs you can have multiple such targets.
4155 We'll start by looking at how to examine the targets you have,
4156 then look at how to add one more target and how to configure it.
4158 @section Target List
4159 @cindex target, current
4160 @cindex target, list
4162 All targets that have been set up are part of a list,
4163 where each member has a name.
4164 That name should normally be the same as the TAP name.
4165 You can display the list with the @command{targets}
4167 This display often has only one CPU; here's what it might
4168 look like with more than one:
4170 TargetName Type Endian TapName State
4171 -- ------------------ ---------- ------ ------------------ ------------
4172 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
4173 1 MyTarget cortex_m little mychip.foo tap-disabled
4176 One member of that list is the @dfn{current target}, which
4177 is implicitly referenced by many commands.
4178 It's the one marked with a @code{*} near the target name.
4179 In particular, memory addresses often refer to the address
4180 space seen by that current target.
4181 Commands like @command{mdw} (memory display words)
4182 and @command{flash erase_address} (erase NOR flash blocks)
4183 are examples; and there are many more.
4185 Several commands let you examine the list of targets:
4187 @deffn Command {target current}
4188 Returns the name of the current target.
4191 @deffn Command {target names}
4192 Lists the names of all current targets in the list.
4194 foreach t [target names] @{
4195 puts [format "Target: %s\n" $t]
4200 @c yep, "target list" would have been better.
4201 @c plus maybe "target setdefault".
4203 @deffn Command targets [name]
4204 @emph{Note: the name of this command is plural. Other target
4205 command names are singular.}
4207 With no parameter, this command displays a table of all known
4208 targets in a user friendly form.
4210 With a parameter, this command sets the current target to
4211 the given target with the given @var{name}; this is
4212 only relevant on boards which have more than one target.
4215 @section Target CPU Types
4219 Each target has a @dfn{CPU type}, as shown in the output of
4220 the @command{targets} command. You need to specify that type
4221 when calling @command{target create}.
4222 The CPU type indicates more than just the instruction set.
4223 It also indicates how that instruction set is implemented,
4224 what kind of debug support it integrates,
4225 whether it has an MMU (and if so, what kind),
4226 what core-specific commands may be available
4227 (@pxref{Architecture and Core Commands}),
4230 It's easy to see what target types are supported,
4231 since there's a command to list them.
4233 @anchor{targettypes}
4234 @deffn Command {target types}
4235 Lists all supported target types.
4236 At this writing, the supported CPU types are:
4239 @item @code{arm11} -- this is a generation of ARMv6 cores
4240 @item @code{arm720t} -- this is an ARMv4 core with an MMU
4241 @item @code{arm7tdmi} -- this is an ARMv4 core
4242 @item @code{arm920t} -- this is an ARMv4 core with an MMU
4243 @item @code{arm926ejs} -- this is an ARMv5 core with an MMU
4244 @item @code{arm966e} -- this is an ARMv5 core
4245 @item @code{arm9tdmi} -- this is an ARMv4 core
4246 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
4247 (Support for this is preliminary and incomplete.)
4248 @item @code{cortex_a} -- this is an ARMv7 core with an MMU
4249 @item @code{cortex_m} -- this is an ARMv7 core, supporting only the
4250 compact Thumb2 instruction set.
4251 @item @code{aarch64} -- this is an ARMv8-A core with an MMU
4252 @item @code{dragonite} -- resembles arm966e
4253 @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
4254 (Support for this is still incomplete.)
4255 @item @code{fa526} -- resembles arm920 (w/o Thumb)
4256 @item @code{feroceon} -- resembles arm926
4257 @item @code{mips_m4k} -- a MIPS core
4258 @item @code{xscale} -- this is actually an architecture,
4259 not a CPU type. It is based on the ARMv5 architecture.
4260 @item @code{openrisc} -- this is an OpenRISC 1000 core.
4261 The current implementation supports three JTAG TAP cores:
4262 @item @code{ls1_sap} -- this is the SAP on NXP LS102x CPUs,
4263 allowing access to physical memory addresses independently of CPU cores.
4265 @item @code{OpenCores TAP} (See: @url{http://opencores.org/project,jtag})
4266 @item @code{Altera Virtual JTAG TAP} (See: @url{http://www.altera.com/literature/ug/ug_virtualjtag.pdf})
4267 @item @code{Xilinx BSCAN_* virtual JTAG interface} (See: @url{http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/spartan6_hdl.pdf})
4269 And two debug interfaces cores:
4271 @item @code{Advanced debug interface} (See: @url{http://opencores.org/project,adv_debug_sys})
4272 @item @code{SoC Debug Interface} (See: @url{http://opencores.org/project,dbg_interface})
4277 To avoid being confused by the variety of ARM based cores, remember
4278 this key point: @emph{ARM is a technology licencing company}.
4279 (See: @url{http://www.arm.com}.)
4280 The CPU name used by OpenOCD will reflect the CPU design that was
4281 licenced, not a vendor brand which incorporates that design.
4282 Name prefixes like arm7, arm9, arm11, and cortex
4283 reflect design generations;
4284 while names like ARMv4, ARMv5, ARMv6, ARMv7 and ARMv8
4285 reflect an architecture version implemented by a CPU design.
4287 @anchor{targetconfiguration}
4288 @section Target Configuration
4290 Before creating a ``target'', you must have added its TAP to the scan chain.
4291 When you've added that TAP, you will have a @code{dotted.name}
4292 which is used to set up the CPU support.
4293 The chip-specific configuration file will normally configure its CPU(s)
4294 right after it adds all of the chip's TAPs to the scan chain.
4296 Although you can set up a target in one step, it's often clearer if you
4297 use shorter commands and do it in two steps: create it, then configure
4299 All operations on the target after it's created will use a new
4300 command, created as part of target creation.
4302 The two main things to configure after target creation are
4303 a work area, which usually has target-specific defaults even
4304 if the board setup code overrides them later;
4305 and event handlers (@pxref{targetevents,,Target Events}), which tend
4306 to be much more board-specific.
4307 The key steps you use might look something like this
4310 dap create mychip.dap -chain-position mychip.cpu
4311 target create MyTarget cortex_m -dap mychip.dap
4312 MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
4313 MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
4314 MyTarget configure -event reset-init @{ myboard_reinit @}
4317 You should specify a working area if you can; typically it uses some
4319 Such a working area can speed up many things, including bulk
4320 writes to target memory;
4321 flash operations like checking to see if memory needs to be erased;
4322 GDB memory checksumming;
4326 On more complex chips, the work area can become
4327 inaccessible when application code
4328 (such as an operating system)
4329 enables or disables the MMU.
4330 For example, the particular MMU context used to acess the virtual
4331 address will probably matter ... and that context might not have
4332 easy access to other addresses needed.
4333 At this writing, OpenOCD doesn't have much MMU intelligence.
4336 It's often very useful to define a @code{reset-init} event handler.
4337 For systems that are normally used with a boot loader,
4338 common tasks include updating clocks and initializing memory
4340 That may be needed to let you write the boot loader into flash,
4341 in order to ``de-brick'' your board; or to load programs into
4342 external DDR memory without having run the boot loader.
4344 @deffn Command {target create} target_name type configparams...
4345 This command creates a GDB debug target that refers to a specific JTAG tap.
4346 It enters that target into a list, and creates a new
4347 command (@command{@var{target_name}}) which is used for various
4348 purposes including additional configuration.
4351 @item @var{target_name} ... is the name of the debug target.
4352 By convention this should be the same as the @emph{dotted.name}
4353 of the TAP associated with this target, which must be specified here
4354 using the @code{-chain-position @var{dotted.name}} configparam.
4356 This name is also used to create the target object command,
4357 referred to here as @command{$target_name},
4358 and in other places the target needs to be identified.
4359 @item @var{type} ... specifies the target type. @xref{targettypes,,target types}.
4360 @item @var{configparams} ... all parameters accepted by
4361 @command{$target_name configure} are permitted.
4362 If the target is big-endian, set it here with @code{-endian big}.
4364 You @emph{must} set the @code{-chain-position @var{dotted.name}} or
4365 @code{-dap @var{dap_name}} here.
4369 @deffn Command {$target_name configure} configparams...
4370 The options accepted by this command may also be
4371 specified as parameters to @command{target create}.
4372 Their values can later be queried one at a time by
4373 using the @command{$target_name cget} command.
4375 @emph{Warning:} changing some of these after setup is dangerous.
4376 For example, moving a target from one TAP to another;
4377 and changing its endianness.
4381 @item @code{-chain-position} @var{dotted.name} -- names the TAP
4382 used to access this target.
4384 @item @code{-dap} @var{dap_name} -- names the DAP used to access
4385 this target. @xref{dapdeclaration,,DAP declaration}, on how to
4386 create and manage DAP instances.
4388 @item @code{-endian} (@option{big}|@option{little}) -- specifies
4389 whether the CPU uses big or little endian conventions
4391 @item @code{-event} @var{event_name} @var{event_body} --
4392 @xref{targetevents,,Target Events}.
4393 Note that this updates a list of named event handlers.
4394 Calling this twice with two different event names assigns
4395 two different handlers, but calling it twice with the
4396 same event name assigns only one handler.
4398 Current target is temporarily overridden to the event issuing target
4399 before handler code starts and switched back after handler is done.
4401 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
4402 whether the work area gets backed up; by default,
4403 @emph{it is not backed up.}
4404 When possible, use a working_area that doesn't need to be backed up,
4405 since performing a backup slows down operations.
4406 For example, the beginning of an SRAM block is likely to
4407 be used by most build systems, but the end is often unused.
4409 @item @code{-work-area-size} @var{size} -- specify work are size,
4410 in bytes. The same size applies regardless of whether its physical
4411 or virtual address is being used.
4413 @item @code{-work-area-phys} @var{address} -- set the work area
4414 base @var{address} to be used when no MMU is active.
4416 @item @code{-work-area-virt} @var{address} -- set the work area
4417 base @var{address} to be used when an MMU is active.
4418 @emph{Do not specify a value for this except on targets with an MMU.}
4419 The value should normally correspond to a static mapping for the
4420 @code{-work-area-phys} address, set up by the current operating system.
4423 @item @code{-rtos} @var{rtos_type} -- enable rtos support for target,
4424 @var{rtos_type} can be one of @option{auto}, @option{eCos},
4425 @option{ThreadX}, @option{FreeRTOS}, @option{linux}, @option{ChibiOS},
4426 @option{embKernel}, @option{mqx}, @option{uCOS-III}
4427 @xref{gdbrtossupport,,RTOS Support}.
4429 @item @code{-defer-examine} -- skip target examination at initial JTAG chain
4430 scan and after a reset. A manual call to arp_examine is required to
4431 access the target for debugging.
4433 @item @code{-ap-num} @var{ap_number} -- set DAP access port for target,
4434 @var{ap_number} is the numeric index of the DAP AP the target is connected to.
4435 Use this option with systems where multiple, independent cores are connected
4436 to separate access ports of the same DAP.
4438 @item @code{-cti} @var{cti_name} -- set Cross-Trigger Interface (CTI) connected
4439 to the target. Currently, only the @code{aarch64} target makes use of this option,
4440 where it is a mandatory configuration for the target run control.
4441 @xref{armcrosstrigger,,ARM Cross-Trigger Interface},
4442 for instruction on how to declare and control a CTI instance.
4446 @section Other $target_name Commands
4447 @cindex object command
4449 The Tcl/Tk language has the concept of object commands,
4450 and OpenOCD adopts that same model for targets.
4452 A good Tk example is a on screen button.
4453 Once a button is created a button
4454 has a name (a path in Tk terms) and that name is useable as a first
4455 class command. For example in Tk, one can create a button and later
4456 configure it like this:
4460 button .foobar -background red -command @{ foo @}
4462 .foobar configure -foreground blue
4464 set x [.foobar cget -background]
4466 puts [format "The button is %s" $x]
4469 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
4470 button, and its object commands are invoked the same way.
4473 str912.cpu mww 0x1234 0x42
4474 omap3530.cpu mww 0x5555 123
4477 The commands supported by OpenOCD target objects are:
4479 @deffn Command {$target_name arp_examine} @option{allow-defer}
4480 @deffnx Command {$target_name arp_halt}
4481 @deffnx Command {$target_name arp_poll}
4482 @deffnx Command {$target_name arp_reset}
4483 @deffnx Command {$target_name arp_waitstate}
4484 Internal OpenOCD scripts (most notably @file{startup.tcl})
4485 use these to deal with specific reset cases.
4486 They are not otherwise documented here.
4489 @deffn Command {$target_name array2mem} arrayname width address count
4490 @deffnx Command {$target_name mem2array} arrayname width address count
4491 These provide an efficient script-oriented interface to memory.
4492 The @code{array2mem} primitive writes bytes, halfwords, or words;
4493 while @code{mem2array} reads them.
4494 In both cases, the TCL side uses an array, and
4495 the target side uses raw memory.
4497 The efficiency comes from enabling the use of
4498 bulk JTAG data transfer operations.
4499 The script orientation comes from working with data
4500 values that are packaged for use by TCL scripts;
4501 @command{mdw} type primitives only print data they retrieve,
4502 and neither store nor return those values.
4505 @item @var{arrayname} ... is the name of an array variable
4506 @item @var{width} ... is 8/16/32 - indicating the memory access size
4507 @item @var{address} ... is the target memory address
4508 @item @var{count} ... is the number of elements to process
4512 @deffn Command {$target_name cget} queryparm
4513 Each configuration parameter accepted by
4514 @command{$target_name configure}
4515 can be individually queried, to return its current value.
4516 The @var{queryparm} is a parameter name
4517 accepted by that command, such as @code{-work-area-phys}.
4518 There are a few special cases:
4521 @item @code{-event} @var{event_name} -- returns the handler for the
4522 event named @var{event_name}.
4523 This is a special case because setting a handler requires
4525 @item @code{-type} -- returns the target type.
4526 This is a special case because this is set using
4527 @command{target create} and can't be changed
4528 using @command{$target_name configure}.
4531 For example, if you wanted to summarize information about
4532 all the targets you might use something like this:
4535 foreach name [target names] @{
4536 set y [$name cget -endian]
4537 set z [$name cget -type]
4538 puts [format "Chip %d is %s, Endian: %s, type: %s" \
4544 @anchor{targetcurstate}
4545 @deffn Command {$target_name curstate}
4546 Displays the current target state:
4547 @code{debug-running},
4550 @code{running}, or @code{unknown}.
4551 (Also, @pxref{eventpolling,,Event Polling}.)
4554 @deffn Command {$target_name eventlist}
4555 Displays a table listing all event handlers
4556 currently associated with this target.
4557 @xref{targetevents,,Target Events}.
4560 @deffn Command {$target_name invoke-event} event_name
4561 Invokes the handler for the event named @var{event_name}.
4562 (This is primarily intended for use by OpenOCD framework
4563 code, for example by the reset code in @file{startup.tcl}.)
4566 @deffn Command {$target_name mdw} addr [count]
4567 @deffnx Command {$target_name mdh} addr [count]
4568 @deffnx Command {$target_name mdb} addr [count]
4569 Display contents of address @var{addr}, as
4570 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
4571 or 8-bit bytes (@command{mdb}).
4572 If @var{count} is specified, displays that many units.
4573 (If you want to manipulate the data instead of displaying it,
4574 see the @code{mem2array} primitives.)
4577 @deffn Command {$target_name mww} addr word
4578 @deffnx Command {$target_name mwh} addr halfword
4579 @deffnx Command {$target_name mwb} addr byte
4580 Writes the specified @var{word} (32 bits),
4581 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4582 at the specified address @var{addr}.
4585 @anchor{targetevents}
4586 @section Target Events
4587 @cindex target events
4589 At various times, certain things can happen, or you want them to happen.
4592 @item What should happen when GDB connects? Should your target reset?
4593 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
4594 @item Is using SRST appropriate (and possible) on your system?
4595 Or instead of that, do you need to issue JTAG commands to trigger reset?
4596 SRST usually resets everything on the scan chain, which can be inappropriate.
4597 @item During reset, do you need to write to certain memory locations
4598 to set up system clocks or
4599 to reconfigure the SDRAM?
4600 How about configuring the watchdog timer, or other peripherals,
4601 to stop running while you hold the core stopped for debugging?
4604 All of the above items can be addressed by target event handlers.
4605 These are set up by @command{$target_name configure -event} or
4606 @command{target create ... -event}.
4608 The programmer's model matches the @code{-command} option used in Tcl/Tk
4609 buttons and events. The two examples below act the same, but one creates
4610 and invokes a small procedure while the other inlines it.
4613 proc my_init_proc @{ @} @{
4614 echo "Disabling watchdog..."
4615 mww 0xfffffd44 0x00008000
4617 mychip.cpu configure -event reset-init my_init_proc
4618 mychip.cpu configure -event reset-init @{
4619 echo "Disabling watchdog..."
4620 mww 0xfffffd44 0x00008000
4624 The following target events are defined:
4627 @item @b{debug-halted}
4628 @* The target has halted for debug reasons (i.e.: breakpoint)
4629 @item @b{debug-resumed}
4630 @* The target has resumed (i.e.: GDB said run)
4631 @item @b{early-halted}
4632 @* Occurs early in the halt process
4633 @item @b{examine-start}
4634 @* Before target examine is called.
4635 @item @b{examine-end}
4636 @* After target examine is called with no errors.
4637 @item @b{gdb-attach}
4638 @* When GDB connects. Issued before any GDB communication with the target
4639 starts. GDB expects the target is halted during attachment.
4640 @xref{gdbmeminspect,,GDB as a non-intrusive memory inspector}, how to
4641 connect GDB to running target.
4642 The event can be also used to set up the target so it is possible to probe flash.
4643 Probing flash is necessary during GDB connect if you want to use
4644 @pxref{programmingusinggdb,,programming using GDB}.
4645 Another use of the flash memory map is for GDB to automatically choose
4646 hardware or software breakpoints depending on whether the breakpoint
4647 is in RAM or read only memory.
4648 Default is @code{halt}
4649 @item @b{gdb-detach}
4650 @* When GDB disconnects
4652 @* When the target has halted and GDB is not doing anything (see early halt)
4653 @item @b{gdb-flash-erase-start}
4654 @* Before the GDB flash process tries to erase the flash (default is
4656 @item @b{gdb-flash-erase-end}
4657 @* After the GDB flash process has finished erasing the flash
4658 @item @b{gdb-flash-write-start}
4659 @* Before GDB writes to the flash
4660 @item @b{gdb-flash-write-end}
4661 @* After GDB writes to the flash (default is @code{reset halt})
4663 @* Before the target steps, GDB is trying to start/resume the target
4665 @* The target has halted
4666 @item @b{reset-assert-pre}
4667 @* Issued as part of @command{reset} processing
4668 after @command{reset-start} was triggered
4669 but before either SRST alone is asserted on the scan chain,
4670 or @code{reset-assert} is triggered.
4671 @item @b{reset-assert}
4672 @* Issued as part of @command{reset} processing
4673 after @command{reset-assert-pre} was triggered.
4674 When such a handler is present, cores which support this event will use
4675 it instead of asserting SRST.
4676 This support is essential for debugging with JTAG interfaces which
4677 don't include an SRST line (JTAG doesn't require SRST), and for
4678 selective reset on scan chains that have multiple targets.
4679 @item @b{reset-assert-post}
4680 @* Issued as part of @command{reset} processing
4681 after @code{reset-assert} has been triggered.
4682 or the target asserted SRST on the entire scan chain.
4683 @item @b{reset-deassert-pre}
4684 @* Issued as part of @command{reset} processing
4685 after @code{reset-assert-post} has been triggered.
4686 @item @b{reset-deassert-post}
4687 @* Issued as part of @command{reset} processing
4688 after @code{reset-deassert-pre} has been triggered
4689 and (if the target is using it) after SRST has been
4690 released on the scan chain.
4692 @* Issued as the final step in @command{reset} processing.
4693 @item @b{reset-init}
4694 @* Used by @b{reset init} command for board-specific initialization.
4695 This event fires after @emph{reset-deassert-post}.
4697 This is where you would configure PLLs and clocking, set up DRAM so
4698 you can download programs that don't fit in on-chip SRAM, set up pin
4699 multiplexing, and so on.
4700 (You may be able to switch to a fast JTAG clock rate here, after
4701 the target clocks are fully set up.)
4702 @item @b{reset-start}
4703 @* Issued as the first step in @command{reset} processing
4704 before @command{reset-assert-pre} is called.
4706 This is the most robust place to use @command{jtag_rclk}
4707 or @command{adapter_khz} to switch to a low JTAG clock rate,
4708 when reset disables PLLs needed to use a fast clock.
4709 @item @b{resume-start}
4710 @* Before any target is resumed
4711 @item @b{resume-end}
4712 @* After all targets have resumed
4714 @* Target has resumed
4715 @item @b{trace-config}
4716 @* After target hardware trace configuration was changed
4719 @node Flash Commands
4720 @chapter Flash Commands
4722 OpenOCD has different commands for NOR and NAND flash;
4723 the ``flash'' command works with NOR flash, while
4724 the ``nand'' command works with NAND flash.
4725 This partially reflects different hardware technologies:
4726 NOR flash usually supports direct CPU instruction and data bus access,
4727 while data from a NAND flash must be copied to memory before it can be
4728 used. (SPI flash must also be copied to memory before use.)
4729 However, the documentation also uses ``flash'' as a generic term;
4730 for example, ``Put flash configuration in board-specific files''.
4734 @item Configure via the command @command{flash bank}
4735 @* Do this in a board-specific configuration file,
4736 passing parameters as needed by the driver.
4737 @item Operate on the flash via @command{flash subcommand}
4738 @* Often commands to manipulate the flash are typed by a human, or run
4739 via a script in some automated way. Common tasks include writing a
4740 boot loader, operating system, or other data.
4742 @* Flashing via GDB requires the flash be configured via ``flash
4743 bank'', and the GDB flash features be enabled.
4744 @xref{gdbconfiguration,,GDB Configuration}.
4747 Many CPUs have the ablity to ``boot'' from the first flash bank.
4748 This means that misprogramming that bank can ``brick'' a system,
4749 so that it can't boot.
4750 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
4751 board by (re)installing working boot firmware.
4753 @anchor{norconfiguration}
4754 @section Flash Configuration Commands
4755 @cindex flash configuration
4757 @deffn {Config Command} {flash bank} name driver base size chip_width bus_width target [driver_options]
4758 Configures a flash bank which provides persistent storage
4759 for addresses from @math{base} to @math{base + size - 1}.
4760 These banks will often be visible to GDB through the target's memory map.
4761 In some cases, configuring a flash bank will activate extra commands;
4762 see the driver-specific documentation.
4765 @item @var{name} ... may be used to reference the flash bank
4766 in other flash commands. A number is also available.
4767 @item @var{driver} ... identifies the controller driver
4768 associated with the flash bank being declared.
4769 This is usually @code{cfi} for external flash, or else
4770 the name of a microcontroller with embedded flash memory.
4771 @xref{flashdriverlist,,Flash Driver List}.
4772 @item @var{base} ... Base address of the flash chip.
4773 @item @var{size} ... Size of the chip, in bytes.
4774 For some drivers, this value is detected from the hardware.
4775 @item @var{chip_width} ... Width of the flash chip, in bytes;
4776 ignored for most microcontroller drivers.
4777 @item @var{bus_width} ... Width of the data bus used to access the
4778 chip, in bytes; ignored for most microcontroller drivers.
4779 @item @var{target} ... Names the target used to issue
4780 commands to the flash controller.
4781 @comment Actually, it's currently a controller-specific parameter...
4782 @item @var{driver_options} ... drivers may support, or require,
4783 additional parameters. See the driver-specific documentation
4784 for more information.
4787 This command is not available after OpenOCD initialization has completed.
4788 Use it in board specific configuration files, not interactively.
4792 @comment the REAL name for this command is "ocd_flash_banks"
4793 @comment less confusing would be: "flash list" (like "nand list")
4794 @deffn Command {flash banks}
4795 Prints a one-line summary of each device that was
4796 declared using @command{flash bank}, numbered from zero.
4797 Note that this is the @emph{plural} form;
4798 the @emph{singular} form is a very different command.
4801 @deffn Command {flash list}
4802 Retrieves a list of associative arrays for each device that was
4803 declared using @command{flash bank}, numbered from zero.
4804 This returned list can be manipulated easily from within scripts.
4807 @deffn Command {flash probe} num
4808 Identify the flash, or validate the parameters of the configured flash. Operation
4809 depends on the flash type.
4810 The @var{num} parameter is a value shown by @command{flash banks}.
4811 Most flash commands will implicitly @emph{autoprobe} the bank;
4812 flash drivers can distinguish between probing and autoprobing,
4813 but most don't bother.
4816 @section Erasing, Reading, Writing to Flash
4817 @cindex flash erasing
4818 @cindex flash reading
4819 @cindex flash writing
4820 @cindex flash programming
4821 @anchor{flashprogrammingcommands}
4823 One feature distinguishing NOR flash from NAND or serial flash technologies
4824 is that for read access, it acts exactly like any other addressible memory.
4825 This means you can use normal memory read commands like @command{mdw} or
4826 @command{dump_image} with it, with no special @command{flash} subcommands.
4827 @xref{memoryaccess,,Memory access}, and @ref{imageaccess,,Image access}.
4829 Write access works differently. Flash memory normally needs to be erased
4830 before it's written. Erasing a sector turns all of its bits to ones, and
4831 writing can turn ones into zeroes. This is why there are special commands
4832 for interactive erasing and writing, and why GDB needs to know which parts
4833 of the address space hold NOR flash memory.
4836 Most of these erase and write commands leverage the fact that NOR flash
4837 chips consume target address space. They implicitly refer to the current
4838 JTAG target, and map from an address in that target's address space
4839 back to a flash bank.
4840 @comment In May 2009, those mappings may fail if any bank associated
4841 @comment with that target doesn't succesfuly autoprobe ... bug worth fixing?
4842 A few commands use abstract addressing based on bank and sector numbers,
4843 and don't depend on searching the current target and its address space.
4844 Avoid confusing the two command models.
4847 Some flash chips implement software protection against accidental writes,
4848 since such buggy writes could in some cases ``brick'' a system.
4849 For such systems, erasing and writing may require sector protection to be
4851 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
4852 and AT91SAM7 on-chip flash.
4853 @xref{flashprotect,,flash protect}.
4855 @deffn Command {flash erase_sector} num first last
4856 Erase sectors in bank @var{num}, starting at sector @var{first}
4857 up to and including @var{last}.
4858 Sector numbering starts at 0.
4859 Providing a @var{last} sector of @option{last}
4860 specifies "to the end of the flash bank".
4861 The @var{num} parameter is a value shown by @command{flash banks}.
4864 @deffn Command {flash erase_address} [@option{pad}] [@option{unlock}] address length
4865 Erase sectors starting at @var{address} for @var{length} bytes.
4866 Unless @option{pad} is specified, @math{address} must begin a
4867 flash sector, and @math{address + length - 1} must end a sector.
4868 Specifying @option{pad} erases extra data at the beginning and/or
4869 end of the specified region, as needed to erase only full sectors.
4870 The flash bank to use is inferred from the @var{address}, and
4871 the specified length must stay within that bank.
4872 As a special case, when @var{length} is zero and @var{address} is
4873 the start of the bank, the whole flash is erased.
4874 If @option{unlock} is specified, then the flash is unprotected
4875 before erase starts.
4878 @deffn Command {flash fillw} address word length
4879 @deffnx Command {flash fillh} address halfword length
4880 @deffnx Command {flash fillb} address byte length
4881 Fills flash memory with the specified @var{word} (32 bits),
4882 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4883 starting at @var{address} and continuing
4884 for @var{length} units (word/halfword/byte).
4885 No erasure is done before writing; when needed, that must be done
4886 before issuing this command.
4887 Writes are done in blocks of up to 1024 bytes, and each write is
4888 verified by reading back the data and comparing it to what was written.
4889 The flash bank to use is inferred from the @var{address} of
4890 each block, and the specified length must stay within that bank.
4892 @comment no current checks for errors if fill blocks touch multiple banks!
4894 @deffn Command {flash write_bank} num filename [offset]
4895 Write the binary @file{filename} to flash bank @var{num},
4896 starting at @var{offset} bytes from the beginning of the bank. If @var{offset}
4897 is omitted, start at the beginning of the flash bank.
4898 The @var{num} parameter is a value shown by @command{flash banks}.
4901 @deffn Command {flash read_bank} num filename [offset [length]]
4902 Read @var{length} bytes from the flash bank @var{num} starting at @var{offset}
4903 and write the contents to the binary @file{filename}. If @var{offset} is
4904 omitted, start at the beginning of the flash bank. If @var{length} is omitted,
4905 read the remaining bytes from the flash bank.
4906 The @var{num} parameter is a value shown by @command{flash banks}.
4909 @deffn Command {flash verify_bank} num filename [offset]
4910 Compare the contents of the binary file @var{filename} with the contents of the
4911 flash bank @var{num} starting at @var{offset}. If @var{offset} is omitted,
4912 start at the beginning of the flash bank. Fail if the contents do not match.
4913 The @var{num} parameter is a value shown by @command{flash banks}.
4916 @deffn Command {flash write_image} [erase] [unlock] filename [offset] [type]
4917 Write the image @file{filename} to the current target's flash bank(s).
4918 Only loadable sections from the image are written.
4919 A relocation @var{offset} may be specified, in which case it is added
4920 to the base address for each section in the image.
4921 The file [@var{type}] can be specified
4922 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
4923 @option{elf} (ELF file), @option{s19} (Motorola s19).
4924 @option{mem}, or @option{builder}.
4925 The relevant flash sectors will be erased prior to programming
4926 if the @option{erase} parameter is given. If @option{unlock} is
4927 provided, then the flash banks are unlocked before erase and
4928 program. The flash bank to use is inferred from the address of
4932 Be careful using the @option{erase} flag when the flash is holding
4933 data you want to preserve.
4934 Portions of the flash outside those described in the image's
4935 sections might be erased with no notice.
4938 When a section of the image being written does not fill out all the
4939 sectors it uses, the unwritten parts of those sectors are necessarily
4940 also erased, because sectors can't be partially erased.
4942 Data stored in sector "holes" between image sections are also affected.
4943 For example, "@command{flash write_image erase ...}" of an image with
4944 one byte at the beginning of a flash bank and one byte at the end
4945 erases the entire bank -- not just the two sectors being written.
4947 Also, when flash protection is important, you must re-apply it after
4948 it has been removed by the @option{unlock} flag.
4953 @section Other Flash commands
4954 @cindex flash protection
4956 @deffn Command {flash erase_check} num
4957 Check erase state of sectors in flash bank @var{num},
4958 and display that status.
4959 The @var{num} parameter is a value shown by @command{flash banks}.
4962 @deffn Command {flash info} num [sectors]
4963 Print info about flash bank @var{num}, a list of protection blocks
4964 and their status. Use @option{sectors} to show a list of sectors instead.
4966 The @var{num} parameter is a value shown by @command{flash banks}.
4967 This command will first query the hardware, it does not print cached
4968 and possibly stale information.
4971 @anchor{flashprotect}
4972 @deffn Command {flash protect} num first last (@option{on}|@option{off})
4973 Enable (@option{on}) or disable (@option{off}) protection of flash blocks
4974 in flash bank @var{num}, starting at protection block @var{first}
4975 and continuing up to and including @var{last}.
4976 Providing a @var{last} block of @option{last}
4977 specifies "to the end of the flash bank".
4978 The @var{num} parameter is a value shown by @command{flash banks}.
4979 The protection block is usually identical to a flash sector.
4980 Some devices may utilize a protection block distinct from flash sector.
4981 See @command{flash info} for a list of protection blocks.
4984 @deffn Command {flash padded_value} num value
4985 Sets the default value used for padding any image sections, This should
4986 normally match the flash bank erased value. If not specified by this
4987 comamnd or the flash driver then it defaults to 0xff.
4991 @deffn Command {program} filename [verify] [reset] [exit] [offset]
4992 This is a helper script that simplifies using OpenOCD as a standalone
4993 programmer. The only required parameter is @option{filename}, the others are optional.
4994 @xref{Flash Programming}.
4997 @anchor{flashdriverlist}
4998 @section Flash Driver List
4999 As noted above, the @command{flash bank} command requires a driver name,
5000 and allows driver-specific options and behaviors.
5001 Some drivers also activate driver-specific commands.
5003 @deffn {Flash Driver} virtual
5004 This is a special driver that maps a previously defined bank to another
5005 address. All bank settings will be copied from the master physical bank.
5007 The @var{virtual} driver defines one mandatory parameters,
5010 @item @var{master_bank} The bank that this virtual address refers to.
5013 So in the following example addresses 0xbfc00000 and 0x9fc00000 refer to
5014 the flash bank defined at address 0x1fc00000. Any cmds executed on
5015 the virtual banks are actually performed on the physical banks.
5017 flash bank $_FLASHNAME pic32mx 0x1fc00000 0 0 0 $_TARGETNAME
5018 flash bank vbank0 virtual 0xbfc00000 0 0 0 \
5019 $_TARGETNAME $_FLASHNAME
5020 flash bank vbank1 virtual 0x9fc00000 0 0 0 \
5021 $_TARGETNAME $_FLASHNAME
5025 @subsection External Flash
5027 @deffn {Flash Driver} cfi
5028 @cindex Common Flash Interface
5030 The ``Common Flash Interface'' (CFI) is the main standard for
5031 external NOR flash chips, each of which connects to a
5032 specific external chip select on the CPU.
5033 Frequently the first such chip is used to boot the system.
5034 Your board's @code{reset-init} handler might need to
5035 configure additional chip selects using other commands (like: @command{mww} to
5036 configure a bus and its timings), or
5037 perhaps configure a GPIO pin that controls the ``write protect'' pin
5039 The CFI driver can use a target-specific working area to significantly
5042 The CFI driver can accept the following optional parameters, in any order:
5045 @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
5046 like AM29LV010 and similar types.
5047 @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
5048 @item @var{bus_swap} ... when data bytes in a 16-bit flash needs to be swapped.
5049 @item @var{data_swap} ... when data bytes in a 16-bit flash needs to be
5050 swapped when writing data values (ie. not CFI commands).
5053 To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
5054 wide on a sixteen bit bus:
5057 flash bank $_FLASHNAME cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
5058 flash bank $_FLASHNAME cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
5061 To configure one bank of 32 MBytes
5062 built from two sixteen bit (two byte) wide parts wired in parallel
5063 to create a thirty-two bit (four byte) bus with doubled throughput:
5066 flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
5069 @c "cfi part_id" disabled
5072 @deffn {Flash Driver} jtagspi
5073 @cindex Generic JTAG2SPI driver
5077 Several FPGAs and CPLDs can retrieve their configuration (bitstream) from a
5078 SPI flash connected to them. To access this flash from the host, the device
5079 is first programmed with a special proxy bitstream that
5080 exposes the SPI flash on the device's JTAG interface. The flash can then be
5081 accessed through JTAG.
5083 Since signaling between JTAG and SPI is compatible, all that is required for
5084 a proxy bitstream is to connect TDI-MOSI, TDO-MISO, TCK-CLK and activate
5085 the flash chip select when the JTAG state machine is in SHIFT-DR. Such
5086 a bitstream for several Xilinx FPGAs can be found in
5087 @file{contrib/loaders/flash/fpga/xilinx_bscan_spi.py}. It requires
5088 @uref{https://github.com/m-labs/migen, migen} and a Xilinx toolchain to build.
5090 This flash bank driver requires a target on a JTAG tap and will access that
5091 tap directly. Since no support from the target is needed, the target can be a
5092 "testee" dummy. Since the target does not expose the flash memory
5093 mapping, target commands that would otherwise be expected to access the flash
5094 will not work. These include all @command{*_image} and
5095 @command{$target_name m*} commands as well as @command{program}. Equivalent
5096 functionality is available through the @command{flash write_bank},
5097 @command{flash read_bank}, and @command{flash verify_bank} commands.
5100 @item @var{ir} ... is loaded into the JTAG IR to map the flash as the JTAG DR.
5101 For the bitstreams generated from @file{xilinx_bscan_spi.py} this is the
5102 @var{USER1} instruction.
5106 target create $_TARGETNAME testee -chain-position $_CHIPNAME.fpga
5107 set _XILINX_USER1 0x02
5108 flash bank $_FLASHNAME spi 0x0 0 0 0 \
5109 $_TARGETNAME $_XILINX_USER1
5113 @deffn {Flash Driver} xcf
5114 @cindex Xilinx Platform flash driver
5116 Xilinx FPGAs can be configured from specialized flash ICs named Platform Flash.
5117 It is (almost) regular NOR flash with erase sectors, program pages, etc. The
5118 only difference is special registers controlling its FPGA specific behavior.
5119 They must be properly configured for successful FPGA loading using
5120 additional @var{xcf} driver command:
5122 @deffn Command {xcf ccb} <bank_id>
5123 command accepts additional parameters:
5125 @item @var{external|internal} ... selects clock source.
5126 @item @var{serial|parallel} ... selects serial or parallel data bus mode.
5127 @item @var{slave|master} ... selects slave of master mode for flash device.
5128 @item @var{40|20} ... selects clock frequency in MHz for internal clock
5132 xcf ccb 0 external parallel slave 40
5134 All of them must be specified even if clock frequency is pointless
5135 in slave mode. If only bank id specified than command prints current
5136 CCB register value. Note: there is no need to write this register
5137 every time you erase/program data sectors because it stores in
5141 @deffn Command {xcf configure} <bank_id>
5142 Initiates FPGA loading procedure. Useful if your board has no "configure"
5149 Additional driver notes:
5151 @item Only single revision supported.
5152 @item Driver automatically detects need of bit reverse, but
5153 only "bin" (raw binary, do not confuse it with "bit") and "mcs"
5154 (Intel hex) file types supported.
5155 @item For additional info check xapp972.pdf and ug380.pdf.
5159 @deffn {Flash Driver} lpcspifi
5160 @cindex NXP SPI Flash Interface
5163 NXP's LPC43xx and LPC18xx families include a proprietary SPI
5164 Flash Interface (SPIFI) peripheral that can drive and provide
5165 memory mapped access to external SPI flash devices.
5167 The lpcspifi driver initializes this interface and provides
5168 program and erase functionality for these serial flash devices.
5169 Use of this driver @b{requires} a working area of at least 1kB
5170 to be configured on the target device; more than this will
5171 significantly reduce flash programming times.
5173 The setup command only requires the @var{base} parameter. All
5174 other parameters are ignored, and the flash size and layout
5175 are configured by the driver.
5178 flash bank $_FLASHNAME lpcspifi 0x14000000 0 0 0 $_TARGETNAME
5183 @deffn {Flash Driver} stmsmi
5184 @cindex STMicroelectronics Serial Memory Interface
5187 Some devices form STMicroelectronics (e.g. STR75x MCU family,
5188 SPEAr MPU family) include a proprietary
5189 ``Serial Memory Interface'' (SMI) controller able to drive external
5191 Depending on specific device and board configuration, up to 4 external
5192 flash devices can be connected.
5194 SMI makes the flash content directly accessible in the CPU address
5195 space; each external device is mapped in a memory bank.
5196 CPU can directly read data, execute code and boot from SMI banks.
5197 Normal OpenOCD commands like @command{mdw} can be used to display
5200 The setup command only requires the @var{base} parameter in order
5201 to identify the memory bank.
5202 All other parameters are ignored. Additional information, like
5203 flash size, are detected automatically.
5206 flash bank $_FLASHNAME stmsmi 0xf8000000 0 0 0 $_TARGETNAME
5211 @deffn {Flash Driver} mrvlqspi
5212 This driver supports QSPI flash controller of Marvell's Wireless
5213 Microcontroller platform.
5215 The flash size is autodetected based on the table of known JEDEC IDs
5216 hardcoded in the OpenOCD sources.
5219 flash bank $_FLASHNAME mrvlqspi 0x0 0 0 0 $_TARGETNAME 0x46010000
5224 @deffn {Flash Driver} ath79
5225 @cindex Atheros ath79 SPI driver
5227 Members of ATH79 SoC family from Atheros include a SPI interface with 3
5229 On reset a SPI flash connected to the first chip select (CS0) is made
5230 directly read-accessible in the CPU address space (up to 16MBytes)
5231 and is usually used to store the bootloader and operating system.
5232 Normal OpenOCD commands like @command{mdw} can be used to display
5233 the flash content while it is in memory-mapped mode (only the first
5234 4MBytes are accessible without additional configuration on reset).
5236 The setup command only requires the @var{base} parameter in order
5237 to identify the memory bank. The actual value for the base address
5238 is not otherwise used by the driver. However the mapping is passed
5239 to gdb. Thus for the memory mapped flash (chipselect CS0) the base
5240 address should be the actual memory mapped base address. For unmapped
5241 chipselects (CS1 and CS2) care should be taken to use a base address
5242 that does not overlap with real memory regions.
5243 Additional information, like flash size, are detected automatically.
5244 An optional additional parameter sets the chipselect for the bank,
5245 with the default CS0.
5246 CS1 and CS2 require additional GPIO setup before they can be used
5247 since the alternate function must be enabled on the GPIO pin
5248 CS1/CS2 is routed to on the given SoC.
5251 flash bank $_FLASHNAME ath79 0 0 0 0 $_TARGETNAME
5253 # When using multiple chipselects the base should be different for each,
5254 # otherwise the write_image command is not able to distinguish the
5256 flash bank flash0 ath79 0x00000000 0 0 0 $_TARGETNAME cs0
5257 flash bank flash1 ath79 0x10000000 0 0 0 $_TARGETNAME cs1
5258 flash bank flash2 ath79 0x20000000 0 0 0 $_TARGETNAME cs2
5263 @subsection Internal Flash (Microcontrollers)
5265 @deffn {Flash Driver} aduc702x
5266 The ADUC702x analog microcontrollers from Analog Devices
5267 include internal flash and use ARM7TDMI cores.
5268 The aduc702x flash driver works with models ADUC7019 through ADUC7028.
5269 The setup command only requires the @var{target} argument
5270 since all devices in this family have the same memory layout.
5273 flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME
5277 @deffn {Flash Driver} ambiqmicro
5280 All members of the Apollo microcontroller family from
5281 Ambiq Micro include internal flash and use ARM's Cortex-M4 core.
5282 The host connects over USB to an FTDI interface that communicates
5283 with the target using SWD.
5285 The @var{ambiqmicro} driver reads the Chip Information Register detect
5286 the device class of the MCU.
5287 The Flash and Sram sizes directly follow device class, and are used
5288 to set up the flash banks.
5289 If this fails, the driver will use default values set to the minimum
5290 sizes of an Apollo chip.
5292 All Apollo chips have two flash banks of the same size.
5293 In all cases the first flash bank starts at location 0,
5294 and the second bank starts after the first.
5298 flash bank $_FLASHNAME ambiqmicro 0 0x00040000 0 0 $_TARGETNAME
5299 # Flash bank 1 - same size as bank0, starts after bank 0.
5300 flash bank $_FLASHNAME ambiqmicro 0x00040000 0x00040000 0 0 \
5304 Flash is programmed using custom entry points into the bootloader.
5305 This is the only way to program the flash as no flash control registers
5306 are available to the user.
5308 The @var{ambiqmicro} driver adds some additional commands:
5310 @deffn Command {ambiqmicro mass_erase} <bank>
5313 @deffn Command {ambiqmicro page_erase} <bank> <first> <last>
5316 @deffn Command {ambiqmicro program_otp} <bank> <offset> <count>
5317 Program OTP is a one time operation to create write protected flash.
5318 The user writes sectors to sram starting at 0x10000010.
5319 Program OTP will write these sectors from sram to flash, and write protect
5325 @deffn {Flash Driver} at91samd
5327 All members of the ATSAMD, ATSAMR, ATSAML and ATSAMC microcontroller
5328 families from Atmel include internal flash and use ARM's Cortex-M0+ core.
5329 This driver uses the same cmd names/syntax as @xref{at91sam3}.
5331 @deffn Command {at91samd chip-erase}
5332 Issues a complete Flash erase via the Device Service Unit (DSU). This can be
5333 used to erase a chip back to its factory state and does not require the
5334 processor to be halted.
5337 @deffn Command {at91samd set-security}
5338 Secures the Flash via the Set Security Bit (SSB) command. This prevents access
5339 to the Flash and can only be undone by using the chip-erase command which
5340 erases the Flash contents and turns off the security bit. Warning: at this
5341 time, openocd will not be able to communicate with a secured chip and it is
5342 therefore not possible to chip-erase it without using another tool.
5345 at91samd set-security enable
5349 @deffn Command {at91samd eeprom}
5350 Shows or sets the EEPROM emulation size configuration, stored in the User Row
5351 of the Flash. When setting, the EEPROM size must be specified in bytes and it
5352 must be one of the permitted sizes according to the datasheet. Settings are
5353 written immediately but only take effect on MCU reset. EEPROM emulation
5354 requires additional firmware support and the minumum EEPROM size may not be
5355 the same as the minimum that the hardware supports. Set the EEPROM size to 0
5356 in order to disable this feature.
5360 at91samd eeprom 1024
5364 @deffn Command {at91samd bootloader}
5365 Shows or sets the bootloader size configuration, stored in the User Row of the
5366 Flash. This is called the BOOTPROT region. When setting, the bootloader size
5367 must be specified in bytes and it must be one of the permitted sizes according
5368 to the datasheet. Settings are written immediately but only take effect on
5369 MCU reset. Setting the bootloader size to 0 disables bootloader protection.
5373 at91samd bootloader 16384
5377 @deffn Command {at91samd dsu_reset_deassert}
5378 This command releases internal reset held by DSU
5379 and prepares reset vector catch in case of reset halt.
5380 Command is used internally in event event reset-deassert-post.
5383 @deffn Command {at91samd nvmuserrow}
5384 Writes or reads the entire 64 bit wide NVM user row register which is located at
5385 0x804000. This register includes various fuses lock-bits and factory calibration
5386 data. Reading the register is done by invoking this command without any
5387 arguments. Writing is possible by giving 1 or 2 hex values. The first argument
5388 is the register value to be written and the second one is an optional changemask.
5389 Every bit which value in changemask is 0 will stay unchanged. The lock- and
5390 reserved-bits are masked out and cannot be changed.
5394 >at91samd nvmuserrow
5395 NVMUSERROW: 0xFFFFFC5DD8E0C788
5396 # Write 0xFFFFFC5DD8E0C788 to user row
5397 >at91samd nvmuserrow 0xFFFFFC5DD8E0C788
5398 # Write 0x12300 to user row but leave other bits and low byte unchanged
5399 >at91samd nvmuserrow 0x12345 0xFFF00
5406 @deffn {Flash Driver} at91sam3
5408 All members of the AT91SAM3 microcontroller family from
5409 Atmel include internal flash and use ARM's Cortex-M3 core. The driver
5410 currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
5411 that the driver was orginaly developed and tested using the
5412 AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in
5413 the family was cribbed from the data sheet. @emph{Note to future
5414 readers/updaters: Please remove this worrysome comment after other
5415 chips are confirmed.}
5417 The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
5418 have one flash bank. In all cases the flash banks are at
5419 the following fixed locations:
5422 # Flash bank 0 - all chips
5423 flash bank $_FLASHNAME at91sam3 0x00080000 0 1 1 $_TARGETNAME
5424 # Flash bank 1 - only 256K chips
5425 flash bank $_FLASHNAME at91sam3 0x00100000 0 1 1 $_TARGETNAME
5428 Internally, the AT91SAM3 flash memory is organized as follows.
5429 Unlike the AT91SAM7 chips, these are not used as parameters
5430 to the @command{flash bank} command:
5433 @item @emph{N-Banks:} 256K chips have 2 banks, others have 1 bank.
5434 @item @emph{Bank Size:} 128K/64K Per flash bank
5435 @item @emph{Sectors:} 16 or 8 per bank
5436 @item @emph{SectorSize:} 8K Per Sector
5437 @item @emph{PageSize:} 256 bytes per page. Note that OpenOCD operates on 'sector' sizes, not page sizes.
5440 The AT91SAM3 driver adds some additional commands:
5442 @deffn Command {at91sam3 gpnvm}
5443 @deffnx Command {at91sam3 gpnvm clear} number
5444 @deffnx Command {at91sam3 gpnvm set} number
5445 @deffnx Command {at91sam3 gpnvm show} [@option{all}|number]
5446 With no parameters, @command{show} or @command{show all},
5447 shows the status of all GPNVM bits.
5448 With @command{show} @var{number}, displays that bit.
5450 With @command{set} @var{number} or @command{clear} @var{number},
5451 modifies that GPNVM bit.
5454 @deffn Command {at91sam3 info}
5455 This command attempts to display information about the AT91SAM3
5456 chip. @emph{First} it read the @code{CHIPID_CIDR} [address 0x400e0740, see
5457 Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
5458 document id: doc6430A] and decodes the values. @emph{Second} it reads the
5459 various clock configuration registers and attempts to display how it
5460 believes the chip is configured. By default, the SLOWCLK is assumed to
5461 be 32768 Hz, see the command @command{at91sam3 slowclk}.
5464 @deffn Command {at91sam3 slowclk} [value]
5465 This command shows/sets the slow clock frequency used in the
5466 @command{at91sam3 info} command calculations above.
5470 @deffn {Flash Driver} at91sam4
5472 All members of the AT91SAM4 microcontroller family from
5473 Atmel include internal flash and use ARM's Cortex-M4 core.
5474 This driver uses the same cmd names/syntax as @xref{at91sam3}.
5477 @deffn {Flash Driver} at91sam4l
5479 All members of the AT91SAM4L microcontroller family from
5480 Atmel include internal flash and use ARM's Cortex-M4 core.
5481 This driver uses the same cmd names/syntax as @xref{at91sam3}.
5483 The AT91SAM4L driver adds some additional commands:
5484 @deffn Command {at91sam4l smap_reset_deassert}
5485 This command releases internal reset held by SMAP
5486 and prepares reset vector catch in case of reset halt.
5487 Command is used internally in event event reset-deassert-post.
5491 @deffn {Flash Driver} atsamv
5493 All members of the ATSAMV, ATSAMS, and ATSAME families from
5494 Atmel include internal flash and use ARM's Cortex-M7 core.
5495 This driver uses the same cmd names/syntax as @xref{at91sam3}.
5498 @deffn {Flash Driver} at91sam7
5499 All members of the AT91SAM7 microcontroller family from Atmel include
5500 internal flash and use ARM7TDMI cores. The driver automatically
5501 recognizes a number of these chips using the chip identification
5502 register, and autoconfigures itself.
5505 flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME
5508 For chips which are not recognized by the controller driver, you must
5509 provide additional parameters in the following order:
5512 @item @var{chip_model} ... label used with @command{flash info}
5514 @item @var{sectors_per_bank}
5515 @item @var{pages_per_sector}
5516 @item @var{pages_size}
5517 @item @var{num_nvm_bits}
5518 @item @var{freq_khz} ... required if an external clock is provided,
5519 optional (but recommended) when the oscillator frequency is known
5522 It is recommended that you provide zeroes for all of those values
5523 except the clock frequency, so that everything except that frequency
5524 will be autoconfigured.
5525 Knowing the frequency helps ensure correct timings for flash access.
5527 The flash controller handles erases automatically on a page (128/256 byte)
5528 basis, so explicit erase commands are not necessary for flash programming.
5529 However, there is an ``EraseAll`` command that can erase an entire flash
5530 plane (of up to 256KB), and it will be used automatically when you issue
5531 @command{flash erase_sector} or @command{flash erase_address} commands.
5533 @deffn Command {at91sam7 gpnvm} bitnum (@option{set}|@option{clear})
5534 Set or clear a ``General Purpose Non-Volatile Memory'' (GPNVM)
5535 bit for the processor. Each processor has a number of such bits,
5536 used for controlling features such as brownout detection (so they
5537 are not truly general purpose).
5539 This assumes that the first flash bank (number 0) is associated with
5540 the appropriate at91sam7 target.
5545 @deffn {Flash Driver} avr
5546 The AVR 8-bit microcontrollers from Atmel integrate flash memory.
5547 @emph{The current implementation is incomplete.}
5548 @comment - defines mass_erase ... pointless given flash_erase_address
5551 @deffn {Flash Driver} bluenrg-x
5552 STMicroelectronics BlueNRG-1 and BlueNRG-2 Bluetooth low energy wireless system-on-chip. They include ARM Cortex-M0 core and internal flash memory.
5553 The driver automatically recognizes these chips using
5554 the chip identification registers, and autoconfigures itself.
5557 flash bank $_FLASHNAME bluenrg-x 0 0 0 0 $_TARGETNAME
5560 Note that when users ask to erase all the sectors of the flash, a mass erase command is used which is faster than erasing
5561 each single sector one by one.
5564 flash erase_sector 0 0 79 # It will perform a mass erase on BlueNRG-1
5568 flash erase_sector 0 0 127 # It will perform a mass erase on BlueNRG-2
5571 Triggering a mass erase is also useful when users want to disable readout protection.
5575 @deffn {Flash Driver} efm32
5576 All members of the EFM32 microcontroller family from Energy Micro include
5577 internal flash and use ARM Cortex-M3 cores. The driver automatically recognizes
5578 a number of these chips using the chip identification register, and
5579 autoconfigures itself.
5581 flash bank $_FLASHNAME efm32 0 0 0 0 $_TARGETNAME
5583 A special feature of efm32 controllers is that it is possible to completely disable the
5584 debug interface by writing the correct values to the 'Debug Lock Word'. OpenOCD supports
5585 this via the following command:
5589 The @var{num} parameter is a value shown by @command{flash banks}.
5590 Note that in order for this command to take effect, the target needs to be reset.
5591 @emph{The current implementation is incomplete. Unprotecting flash pages is not
5595 @deffn {Flash Driver} fm3
5596 All members of the FM3 microcontroller family from Fujitsu
5597 include internal flash and use ARM Cortex-M3 cores.
5598 The @var{fm3} driver uses the @var{target} parameter to select the
5599 correct bank config, it can currently be one of the following:
5600 @code{mb9bfxx1.cpu}, @code{mb9bfxx2.cpu}, @code{mb9bfxx3.cpu},
5601 @code{mb9bfxx4.cpu}, @code{mb9bfxx5.cpu} or @code{mb9bfxx6.cpu}.
5604 flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME
5608 @deffn {Flash Driver} fm4
5609 All members of the FM4 microcontroller family from Spansion (formerly Fujitsu)
5610 include internal flash and use ARM Cortex-M4 cores.
5611 The @var{fm4} driver uses a @var{family} parameter to select the
5612 correct bank config, it can currently be one of the following:
5613 @code{MB9BFx64}, @code{MB9BFx65}, @code{MB9BFx66}, @code{MB9BFx67}, @code{MB9BFx68},
5614 @code{S6E2Cx8}, @code{S6E2Cx9}, @code{S6E2CxA} or @code{S6E2Dx},
5615 with @code{x} treated as wildcard and otherwise case (and any trailing
5616 characters) ignored.
5619 flash bank $@{_FLASHNAME@}0 fm4 0x00000000 0 0 0 \
5620 $_TARGETNAME S6E2CCAJ0A
5621 flash bank $@{_FLASHNAME@}1 fm4 0x00100000 0 0 0 \
5622 $_TARGETNAME S6E2CCAJ0A
5624 @emph{The current implementation is incomplete. Protection is not supported,
5625 nor is Chip Erase (only Sector Erase is implemented).}
5628 @deffn {Flash Driver} kinetis
5630 Kx, KLx, KVx and KE1x members of the Kinetis microcontroller family
5631 from NXP (former Freescale) include
5632 internal flash and use ARM Cortex-M0+ or M4 cores. The driver automatically
5633 recognizes flash size and a number of flash banks (1-4) using the chip
5634 identification register, and autoconfigures itself.
5635 Use kinetis_ke driver for KE0x and KEAx devices.
5637 The @var{kinetis} driver defines option:
5639 @item -sim-base @var{addr} ... base of System Integration Module where chip identification resides. Driver tries two known locations if option is omitted.
5643 flash bank $_FLASHNAME kinetis 0 0 0 0 $_TARGETNAME
5646 @deffn Command {kinetis create_banks}
5647 Configuration command enables automatic creation of additional flash banks
5648 based on real flash layout of device. Banks are created during device probe.
5649 Use 'flash probe 0' to force probe.
5652 @deffn Command {kinetis fcf_source} [protection|write]
5653 Select what source is used when writing to a Flash Configuration Field.
5654 @option{protection} mode builds FCF content from protection bits previously
5655 set by 'flash protect' command.
5656 This mode is default. MCU is protected from unwanted locking by immediate
5657 writing FCF after erase of relevant sector.
5658 @option{write} mode enables direct write to FCF.
5659 Protection cannot be set by 'flash protect' command. FCF is written along
5660 with the rest of a flash image.
5661 @emph{BEWARE: Incorrect flash configuration may permanently lock the device!}
5664 @deffn Command {kinetis fopt} [num]
5665 Set value to write to FOPT byte of Flash Configuration Field.
5666 Used in kinetis 'fcf_source protection' mode only.
5669 @deffn Command {kinetis mdm check_security}
5670 Checks status of device security lock. Used internally in examine-end event.
5673 @deffn Command {kinetis mdm halt}
5674 Issues a halt via the MDM-AP. This command can be used to break a watchdog reset
5675 loop when connecting to an unsecured target.
5678 @deffn Command {kinetis mdm mass_erase}
5679 Issues a complete flash erase via the MDM-AP. This can be used to erase a chip
5680 back to its factory state, removing security. It does not require the processor
5681 to be halted, however the target will remain in a halted state after this
5685 @deffn Command {kinetis nvm_partition}
5686 For FlexNVM devices only (KxxDX and KxxFX).
5687 Command shows or sets data flash or EEPROM backup size in kilobytes,
5688 sets two EEPROM blocks sizes in bytes and enables/disables loading
5689 of EEPROM contents to FlexRAM during reset.
5691 For details see device reference manual, Flash Memory Module,
5692 Program Partition command.
5694 Setting is possible only once after mass_erase.
5695 Reset the device after partition setting.
5697 Show partition size:
5699 kinetis nvm_partition info
5702 Set 32 KB data flash, rest of FlexNVM is EEPROM backup. EEPROM has two blocks
5703 of 512 and 1536 bytes and its contents is loaded to FlexRAM during reset:
5705 kinetis nvm_partition dataflash 32 512 1536 on
5708 Set 16 KB EEPROM backup, rest of FlexNVM is a data flash. EEPROM has two blocks
5709 of 1024 bytes and its contents is not loaded to FlexRAM during reset:
5711 kinetis nvm_partition eebkp 16 1024 1024 off
5715 @deffn Command {kinetis mdm reset}
5716 Issues a reset via the MDM-AP. This causes the MCU to output a low pulse on the
5717 RESET pin, which can be used to reset other hardware on board.
5720 @deffn Command {kinetis disable_wdog}
5721 For Kx devices only (KLx has different COP watchdog, it is not supported).
5722 Command disables watchdog timer.
5726 @deffn {Flash Driver} kinetis_ke
5728 KE0x and KEAx members of the Kinetis microcontroller family from NXP include
5729 internal flash and use ARM Cortex-M0+. The driver automatically recognizes
5730 the KE0x sub-family using the chip identification register, and
5731 autoconfigures itself.
5732 Use kinetis (not kinetis_ke) driver for KE1x devices.
5735 flash bank $_FLASHNAME kinetis_ke 0 0 0 0 $_TARGETNAME
5738 @deffn Command {kinetis_ke mdm check_security}
5739 Checks status of device security lock. Used internally in examine-end event.
5742 @deffn Command {kinetis_ke mdm mass_erase}
5743 Issues a complete Flash erase via the MDM-AP.
5744 This can be used to erase a chip back to its factory state.
5745 Command removes security lock from a device (use of SRST highly recommended).
5746 It does not require the processor to be halted.
5749 @deffn Command {kinetis_ke disable_wdog}
5750 Command disables watchdog timer.
5754 @deffn {Flash Driver} lpc2000
5755 This is the driver to support internal flash of all members of the
5756 LPC11(x)00 and LPC1300 microcontroller families and most members of
5757 the LPC800, LPC1500, LPC1700, LPC1800, LPC2000, LPC4000 and LPC54100
5758 microcontroller families from NXP.
5761 There are LPC2000 devices which are not supported by the @var{lpc2000}
5763 The LPC2888 is supported by the @var{lpc288x} driver.
5764 The LPC29xx family is supported by the @var{lpc2900} driver.
5767 The @var{lpc2000} driver defines two mandatory and one optional parameters,
5768 which must appear in the following order:
5771 @item @var{variant} ... required, may be
5772 @option{lpc2000_v1} (older LPC21xx and LPC22xx)
5773 @option{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
5774 @option{lpc1700} (LPC175x and LPC176x and LPC177x/8x)
5775 @option{lpc4300} - available also as @option{lpc1800} alias (LPC18x[2357] and
5777 @option{lpc800} (LPC8xx)
5778 @option{lpc1100} (LPC11(x)xx and LPC13xx)
5779 @option{lpc1500} (LPC15xx)
5780 @option{lpc54100} (LPC541xx)
5781 @option{lpc4000} (LPC40xx)
5782 or @option{auto} - automatically detects flash variant and size for LPC11(x)00,
5783 LPC8xx, LPC13xx, LPC17xx and LPC40xx
5784 @item @var{clock_kHz} ... the frequency, in kiloHertz,
5785 at which the core is running
5786 @item @option{calc_checksum} ... optional (but you probably want to provide this!),
5787 telling the driver to calculate a valid checksum for the exception vector table.
5789 If you don't provide @option{calc_checksum} when you're writing the vector
5790 table, the boot ROM will almost certainly ignore your flash image.
5791 However, if you do provide it,
5792 with most tool chains @command{verify_image} will fail.
5796 LPC flashes don't require the chip and bus width to be specified.
5799 flash bank $_FLASHNAME lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
5800 lpc2000_v2 14765 calc_checksum
5803 @deffn {Command} {lpc2000 part_id} bank
5804 Displays the four byte part identifier associated with
5805 the specified flash @var{bank}.
5809 @deffn {Flash Driver} lpc288x
5810 The LPC2888 microcontroller from NXP needs slightly different flash
5811 support from its lpc2000 siblings.
5812 The @var{lpc288x} driver defines one mandatory parameter,
5813 the programming clock rate in Hz.
5814 LPC flashes don't require the chip and bus width to be specified.
5817 flash bank $_FLASHNAME lpc288x 0 0 0 0 $_TARGETNAME 12000000
5821 @deffn {Flash Driver} lpc2900
5822 This driver supports the LPC29xx ARM968E based microcontroller family
5825 The predefined parameters @var{base}, @var{size}, @var{chip_width} and
5826 @var{bus_width} of the @code{flash bank} command are ignored. Flash size and
5827 sector layout are auto-configured by the driver.
5828 The driver has one additional mandatory parameter: The CPU clock rate
5829 (in kHz) at the time the flash operations will take place. Most of the time this
5830 will not be the crystal frequency, but a higher PLL frequency. The
5831 @code{reset-init} event handler in the board script is usually the place where
5834 The driver rejects flashless devices (currently the LPC2930).
5836 The EEPROM in LPC2900 devices is not mapped directly into the address space.
5837 It must be handled much more like NAND flash memory, and will therefore be
5838 handled by a separate @code{lpc2900_eeprom} driver (not yet available).
5840 Sector protection in terms of the LPC2900 is handled transparently. Every time a
5841 sector needs to be erased or programmed, it is automatically unprotected.
5842 What is shown as protection status in the @code{flash info} command, is
5843 actually the LPC2900 @emph{sector security}. This is a mechanism to prevent a
5844 sector from ever being erased or programmed again. As this is an irreversible
5845 mechanism, it is handled by a special command (@code{lpc2900 secure_sector}),
5846 and not by the standard @code{flash protect} command.
5848 Example for a 125 MHz clock frequency:
5850 flash bank $_FLASHNAME lpc2900 0 0 0 0 $_TARGETNAME 125000
5853 Some @code{lpc2900}-specific commands are defined. In the following command list,
5854 the @var{bank} parameter is the bank number as obtained by the
5855 @code{flash banks} command.
5857 @deffn Command {lpc2900 signature} bank
5858 Calculates a 128-bit hash value, the @emph{signature}, from the whole flash
5859 content. This is a hardware feature of the flash block, hence the calculation is
5860 very fast. You may use this to verify the content of a programmed device against
5865 signature: 0x5f40cdc8:0xc64e592e:0x10490f89:0x32a0f317
5869 @deffn Command {lpc2900 read_custom} bank filename
5870 Reads the 912 bytes of customer information from the flash index sector, and
5871 saves it to a file in binary format.
5874 lpc2900 read_custom 0 /path_to/customer_info.bin
5878 The index sector of the flash is a @emph{write-only} sector. It cannot be
5879 erased! In order to guard against unintentional write access, all following
5880 commands need to be preceeded by a successful call to the @code{password}
5883 @deffn Command {lpc2900 password} bank password
5884 You need to use this command right before each of the following commands:
5885 @code{lpc2900 write_custom}, @code{lpc2900 secure_sector},
5886 @code{lpc2900 secure_jtag}.
5888 The password string is fixed to "I_know_what_I_am_doing".
5891 lpc2900 password 0 I_know_what_I_am_doing
5892 Potentially dangerous operation allowed in next command!
5896 @deffn Command {lpc2900 write_custom} bank filename type
5897 Writes the content of the file into the customer info space of the flash index
5898 sector. The filetype can be specified with the @var{type} field. Possible values
5899 for @var{type} are: @var{bin} (binary), @var{ihex} (Intel hex format),
5900 @var{elf} (ELF binary) or @var{s19} (Motorola S-records). The file must
5901 contain a single section, and the contained data length must be exactly
5903 @quotation Attention
5904 This cannot be reverted! Be careful!
5908 lpc2900 write_custom 0 /path_to/customer_info.bin bin
5912 @deffn Command {lpc2900 secure_sector} bank first last
5913 Secures the sector range from @var{first} to @var{last} (including) against
5914 further program and erase operations. The sector security will be effective
5915 after the next power cycle.
5916 @quotation Attention
5917 This cannot be reverted! Be careful!
5919 Secured sectors appear as @emph{protected} in the @code{flash info} command.
5922 lpc2900 secure_sector 0 1 1
5924 #0 : lpc2900 at 0x20000000, size 0x000c0000, (...)
5925 # 0: 0x00000000 (0x2000 8kB) not protected
5926 # 1: 0x00002000 (0x2000 8kB) protected
5927 # 2: 0x00004000 (0x2000 8kB) not protected
5931 @deffn Command {lpc2900 secure_jtag} bank
5932 Irreversibly disable the JTAG port. The new JTAG security setting will be
5933 effective after the next power cycle.
5934 @quotation Attention
5935 This cannot be reverted! Be careful!
5939 lpc2900 secure_jtag 0
5944 @deffn {Flash Driver} mdr
5945 This drivers handles the integrated NOR flash on Milandr Cortex-M
5946 based controllers. A known limitation is that the Info memory can't be
5947 read or verified as it's not memory mapped.
5950 flash bank <name> mdr <base> <size> \
5951 0 0 <target#> @var{type} @var{page_count} @var{sec_count}
5955 @item @var{type} - 0 for main memory, 1 for info memory
5956 @item @var{page_count} - total number of pages
5957 @item @var{sec_count} - number of sector per page count
5962 if @{ [info exists IMEMORY] && [string equal $IMEMORY true] @} @{
5963 flash bank $@{_CHIPNAME@}_info.flash mdr 0x00000000 0x01000 \
5964 0 0 $_TARGETNAME 1 1 4
5966 flash bank $_CHIPNAME.flash mdr 0x00000000 0x20000 \
5967 0 0 $_TARGETNAME 0 32 4
5972 @deffn {Flash Driver} niietcm4
5973 This drivers handles the integrated NOR flash on NIIET Cortex-M4
5974 based controllers. Flash size and sector layout are auto-configured by the driver.
5975 Main flash memory is called "Bootflash" and has main region and info region.
5976 Info region is NOT memory mapped by default,
5977 but it can replace first part of main region if needed.
5978 Full erase, single and block writes are supported for both main and info regions.
5979 There is additional not memory mapped flash called "Userflash", which
5980 also have division into regions: main and info.
5981 Purpose of userflash - to store system and user settings.
5982 Driver has special commands to perform operations with this memmory.
5985 flash bank $_FLASHNAME niietcm4 0 0 0 0 $_TARGETNAME
5988 Some niietcm4-specific commands are defined:
5990 @deffn Command {niietcm4 uflash_read_byte} bank ('main'|'info') address
5991 Read byte from main or info userflash region.
5994 @deffn Command {niietcm4 uflash_write_byte} bank ('main'|'info') address value
5995 Write byte to main or info userflash region.
5998 @deffn Command {niietcm4 uflash_full_erase} bank
5999 Erase all userflash including info region.
6002 @deffn Command {niietcm4 uflash_erase} bank ('main'|'info') first_sector last_sector
6003 Erase sectors of main or info userflash region, starting at sector first up to and including last.
6006 @deffn Command {niietcm4 uflash_protect_check} bank ('main'|'info')
6007 Check sectors protect.
6010 @deffn Command {niietcm4 uflash_protect} bank ('main'|'info') first_sector last_sector ('on'|'off')
6011 Protect sectors of main or info userflash region, starting at sector first up to and including last.
6014 @deffn Command {niietcm4 bflash_info_remap} bank ('on'|'off')
6015 Enable remapping bootflash info region to 0x00000000 (or 0x40000000 if external memory boot used).
6018 @deffn Command {niietcm4 extmem_cfg} bank ('gpioa'|'gpiob'|'gpioc'|'gpiod'|'gpioe'|'gpiof'|'gpiog'|'gpioh') pin_num ('func1'|'func3')
6019 Configure external memory interface for boot.
6022 @deffn Command {niietcm4 service_mode_erase} bank
6023 Perform emergency erase of all flash (bootflash and userflash).
6026 @deffn Command {niietcm4 driver_info} bank
6027 Show information about flash driver.
6032 @deffn {Flash Driver} nrf5
6033 All members of the nRF51 microcontroller families from Nordic Semiconductor
6034 include internal flash and use ARM Cortex-M0 core.
6035 Also, the nRF52832 microcontroller from Nordic Semiconductor, which include
6036 internal flash and use an ARM Cortex-M4F core.
6039 flash bank $_FLASHNAME nrf5 0 0x00000000 0 0 $_TARGETNAME
6042 Some nrf5-specific commands are defined:
6044 @deffn Command {nrf5 mass_erase}
6045 Erases the contents of the code memory and user information
6046 configuration registers as well. It must be noted that this command
6047 works only for chips that do not have factory pre-programmed region 0
6053 @deffn {Flash Driver} ocl
6054 This driver is an implementation of the ``on chip flash loader''
6055 protocol proposed by Pavel Chromy.
6057 It is a minimalistic command-response protocol intended to be used
6058 over a DCC when communicating with an internal or external flash
6059 loader running from RAM. An example implementation for AT91SAM7x is
6060 available in @file{contrib/loaders/flash/at91sam7x/}.
6063 flash bank $_FLASHNAME ocl 0 0 0 0 $_TARGETNAME
6067 @deffn {Flash Driver} pic32mx
6068 The PIC32MX microcontrollers are based on the MIPS 4K cores,
6069 and integrate flash memory.
6072 flash bank $_FLASHNAME pix32mx 0x1fc00000 0 0 0 $_TARGETNAME
6073 flash bank $_FLASHNAME pix32mx 0x1d000000 0 0 0 $_TARGETNAME
6076 @comment numerous *disabled* commands are defined:
6077 @comment - chip_erase ... pointless given flash_erase_address
6078 @comment - lock, unlock ... pointless given protect on/off (yes?)
6079 @comment - pgm_word ... shouldn't bank be deduced from address??
6080 Some pic32mx-specific commands are defined:
6081 @deffn Command {pic32mx pgm_word} address value bank
6082 Programs the specified 32-bit @var{value} at the given @var{address}
6083 in the specified chip @var{bank}.
6085 @deffn Command {pic32mx unlock} bank
6086 Unlock and erase specified chip @var{bank}.
6087 This will remove any Code Protection.
6091 @deffn {Flash Driver} psoc4
6092 All members of the PSoC 41xx/42xx microcontroller family from Cypress
6093 include internal flash and use ARM Cortex-M0 cores.
6094 The driver automatically recognizes a number of these chips using
6095 the chip identification register, and autoconfigures itself.
6097 Note: Erased internal flash reads as 00.
6098 System ROM of PSoC 4 does not implement erase of a flash sector.
6101 flash bank $_FLASHNAME psoc4 0 0 0 0 $_TARGETNAME
6104 psoc4-specific commands
6105 @deffn Command {psoc4 flash_autoerase} num (on|off)
6106 Enables or disables autoerase mode for a flash bank.
6108 If flash_autoerase is off, use mass_erase before flash programming.
6109 Flash erase command fails if region to erase is not whole flash memory.
6111 If flash_autoerase is on, a sector is both erased and programmed in one
6112 system ROM call. Flash erase command is ignored.
6113 This mode is suitable for gdb load.
6115 The @var{num} parameter is a value shown by @command{flash banks}.
6118 @deffn Command {psoc4 mass_erase} num
6119 Erases the contents of the flash memory, protection and security lock.
6121 The @var{num} parameter is a value shown by @command{flash banks}.
6125 @deffn {Flash Driver} psoc6
6126 Supports PSoC6 (CY8C6xxx) family of Cypress microcontrollers.
6127 PSoC6 is a dual-core device with CM0+ and CM4 cores. Both cores share
6128 the same Flash/RAM/MMIO address space.
6130 Flash in PSoC6 is split into three regions:
6132 @item Main Flash - this is the main storage for user application.
6133 Total size varies among devices, sector size: 256 kBytes, row size:
6134 512 bytes. Supports erase operation on individual rows.
6135 @item Work Flash - intended to be used as storage for user data
6136 (e.g. EEPROM emulation). Total size: 32 KBytes, sector size: 32 KBytes,
6137 row size: 512 bytes.
6138 @item Supervisory Flash - special region which contains device-specific
6139 service data. This region does not support erase operation. Only few rows can
6140 be programmed by the user, most of the rows are read only. Programming
6141 operation will erase row automatically.
6144 All three flash regions are supported by the driver. Flash geometry is detected
6145 automatically by parsing data in SPCIF_GEOMETRY register.
6147 PSoC6 is equipped with NOR Flash so erased Flash reads as 0x00.
6150 flash bank main_flash_cm0 psoc6 0x10000000 0 0 0 $@{TARGET@}.cm0
6151 flash bank work_flash_cm0 psoc6 0x14000000 0 0 0 $@{TARGET@}.cm0
6152 flash bank super_flash_user_cm0 psoc6 0x16000800 0 0 0 $@{TARGET@}.cm0
6153 flash bank super_flash_nar_cm0 psoc6 0x16001A00 0 0 0 $@{TARGET@}.cm0
6154 flash bank super_flash_key_cm0 psoc6 0x16005A00 0 0 0 $@{TARGET@}.cm0
6155 flash bank super_flash_toc2_cm0 psoc6 0x16007C00 0 0 0 $@{TARGET@}.cm0
6157 flash bank main_flash_cm4 psoc6 0x10000000 0 0 0 $@{TARGET@}.cm4
6158 flash bank work_flash_cm4 psoc6 0x14000000 0 0 0 $@{TARGET@}.cm4
6159 flash bank super_flash_user_cm4 psoc6 0x16000800 0 0 0 $@{TARGET@}.cm4
6160 flash bank super_flash_nar_cm4 psoc6 0x16001A00 0 0 0 $@{TARGET@}.cm4
6161 flash bank super_flash_key_cm4 psoc6 0x16005A00 0 0 0 $@{TARGET@}.cm4
6162 flash bank super_flash_toc2_cm4 psoc6 0x16007C00 0 0 0 $@{TARGET@}.cm4
6165 psoc6-specific commands
6166 @deffn Command {psoc6 reset_halt}
6167 Command can be used to simulate broken Vector Catch from gdbinit or tcl scripts.
6168 When invoked for CM0+ target, it will set break point at application entry point
6169 and issue SYSRESETREQ. This will reset both cores and all peripherals. CM0+ will
6170 reset CM4 during boot anyway so this is safe. On CM4 target, VECTRESET is used
6171 instead of SYSRESETREQ to avoid unwanted reset of CM0+;
6174 @deffn Command {psoc6 mass_erase} num
6175 Erases the contents given flash bank. The @var{num} parameter is a value shown
6176 by @command{flash banks}.
6177 Note: only Main and Work flash regions support Erase operation.
6181 @deffn {Flash Driver} sim3x
6182 All members of the SiM3 microcontroller family from Silicon Laboratories
6183 include internal flash and use ARM Cortex-M3 cores. It supports both JTAG
6185 The @var{sim3x} driver tries to probe the device to auto detect the MCU.
6186 If this failes, it will use the @var{size} parameter as the size of flash bank.
6189 flash bank $_FLASHNAME sim3x 0 $_CPUROMSIZE 0 0 $_TARGETNAME
6192 There are 2 commands defined in the @var{sim3x} driver:
6194 @deffn Command {sim3x mass_erase}
6195 Erases the complete flash. This is used to unlock the flash.
6196 And this command is only possible when using the SWD interface.
6199 @deffn Command {sim3x lock}
6200 Lock the flash. To unlock use the @command{sim3x mass_erase} command.
6204 @deffn {Flash Driver} stellaris
6205 All members of the Stellaris LM3Sxxx, LM4x and Tiva C microcontroller
6206 families from Texas Instruments include internal flash. The driver
6207 automatically recognizes a number of these chips using the chip
6208 identification register, and autoconfigures itself.
6211 flash bank $_FLASHNAME stellaris 0 0 0 0 $_TARGETNAME
6214 @deffn Command {stellaris recover}
6215 Performs the @emph{Recovering a "Locked" Device} procedure to restore
6216 the flash and its associated nonvolatile registers to their factory
6217 default values (erased). This is the only way to remove flash
6218 protection or re-enable debugging if that capability has been
6221 Note that the final "power cycle the chip" step in this procedure
6222 must be performed by hand, since OpenOCD can't do it.
6224 if more than one Stellaris chip is connected, the procedure is
6225 applied to all of them.
6230 @deffn {Flash Driver} stm32f1x
6231 All members of the STM32F0, STM32F1 and STM32F3 microcontroller families
6232 from ST Microelectronics include internal flash and use ARM Cortex-M0/M3/M4 cores.
6233 The driver automatically recognizes a number of these chips using
6234 the chip identification register, and autoconfigures itself.
6237 flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
6240 Note that some devices have been found that have a flash size register that contains
6241 an invalid value, to workaround this issue you can override the probed value used by
6245 flash bank $_FLASHNAME stm32f1x 0 0x20000 0 0 $_TARGETNAME
6248 If you have a target with dual flash banks then define the second bank
6249 as per the following example.
6251 flash bank $_FLASHNAME stm32f1x 0x08080000 0 0 0 $_TARGETNAME
6254 Some stm32f1x-specific commands are defined:
6256 @deffn Command {stm32f1x lock} num
6257 Locks the entire stm32 device.
6258 The @var{num} parameter is a value shown by @command{flash banks}.
6261 @deffn Command {stm32f1x unlock} num
6262 Unlocks the entire stm32 device.
6263 The @var{num} parameter is a value shown by @command{flash banks}.
6266 @deffn Command {stm32f1x mass_erase} num
6267 Mass erases the entire stm32f1x device.
6268 The @var{num} parameter is a value shown by @command{flash banks}.
6271 @deffn Command {stm32f1x options_read} num
6272 Read and display the stm32 option bytes written by
6273 the @command{stm32f1x options_write} command.
6274 The @var{num} parameter is a value shown by @command{flash banks}.
6277 @deffn Command {stm32f1x options_write} num (@option{SWWDG}|@option{HWWDG}) (@option{RSTSTNDBY}|@option{NORSTSTNDBY}) (@option{RSTSTOP}|@option{NORSTSTOP})
6278 Writes the stm32 option byte with the specified values.
6279 The @var{num} parameter is a value shown by @command{flash banks}.
6283 @deffn {Flash Driver} stm32f2x
6284 All members of the STM32F2, STM32F4 and STM32F7 microcontroller families from ST Microelectronics
6285 include internal flash and use ARM Cortex-M3/M4/M7 cores.
6286 The driver automatically recognizes a number of these chips using
6287 the chip identification register, and autoconfigures itself.
6290 flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
6293 Note that some devices have been found that have a flash size register that contains
6294 an invalid value, to workaround this issue you can override the probed value used by
6298 flash bank $_FLASHNAME stm32f2x 0 0x20000 0 0 $_TARGETNAME
6301 Some stm32f2x-specific commands are defined:
6303 @deffn Command {stm32f2x lock} num
6304 Locks the entire stm32 device.
6305 The @var{num} parameter is a value shown by @command{flash banks}.
6308 @deffn Command {stm32f2x unlock} num
6309 Unlocks the entire stm32 device.
6310 The @var{num} parameter is a value shown by @command{flash banks}.
6313 @deffn Command {stm32f2x mass_erase} num
6314 Mass erases the entire stm32f2x device.
6315 The @var{num} parameter is a value shown by @command{flash banks}.
6318 @deffn Command {stm32f2x options_read} num
6319 Reads and displays user options and (where implemented) boot_addr0, boot_addr1, optcr2.
6320 The @var{num} parameter is a value shown by @command{flash banks}.
6323 @deffn Command {stm32f2x options_write} num user_options boot_addr0 boot_addr1
6324 Writes user options and (where implemented) boot_addr0 and boot_addr1 in raw format.
6325 Warning: The meaning of the various bits depends on the device, always check datasheet!
6326 The @var{num} parameter is a value shown by @command{flash banks}, @var{user_options} a
6327 12 bit value, consisting of bits 31-28 and 7-0 of FLASH_OPTCR, @var{boot_addr0} and
6328 @var{boot_addr1} two halfwords (of FLASH_OPTCR1).
6331 @deffn Command {stm32f2x optcr2_write} num optcr2
6332 Writes FLASH_OPTCR2 options. Warning: Clearing PCROPi bits requires a full mass erase!
6333 The @var{num} parameter is a value shown by @command{flash banks}, @var{optcr2} a 32-bit word.
6337 @deffn {Flash Driver} stm32h7x
6338 All members of the STM32H7 microcontroller families from ST Microelectronics
6339 include internal flash and use ARM Cortex-M7 core.
6340 The driver automatically recognizes a number of these chips using
6341 the chip identification register, and autoconfigures itself.
6344 flash bank $_FLASHNAME stm32h7x 0 0 0 0 $_TARGETNAME
6347 Note that some devices have been found that have a flash size register that contains
6348 an invalid value, to workaround this issue you can override the probed value used by
6352 flash bank $_FLASHNAME stm32h7x 0 0x20000 0 0 $_TARGETNAME
6355 Some stm32h7x-specific commands are defined:
6357 @deffn Command {stm32h7x lock} num
6358 Locks the entire stm32 device.
6359 The @var{num} parameter is a value shown by @command{flash banks}.
6362 @deffn Command {stm32h7x unlock} num
6363 Unlocks the entire stm32 device.
6364 The @var{num} parameter is a value shown by @command{flash banks}.
6367 @deffn Command {stm32h7x mass_erase} num
6368 Mass erases the entire stm32h7x device.
6369 The @var{num} parameter is a value shown by @command{flash banks}.
6373 @deffn {Flash Driver} stm32lx
6374 All members of the STM32L microcontroller families from ST Microelectronics
6375 include internal flash and use ARM Cortex-M3 and Cortex-M0+ cores.
6376 The driver automatically recognizes a number of these chips using
6377 the chip identification register, and autoconfigures itself.
6380 flash bank $_FLASHNAME stm32lx 0 0 0 0 $_TARGETNAME
6383 Note that some devices have been found that have a flash size register that contains
6384 an invalid value, to workaround this issue you can override the probed value used by
6385 the flash driver. If you use 0 as the bank base address, it tells the
6386 driver to autodetect the bank location assuming you're configuring the
6390 flash bank $_FLASHNAME stm32lx 0x08000000 0x20000 0 0 $_TARGETNAME
6393 Some stm32lx-specific commands are defined:
6395 @deffn Command {stm32lx lock} num
6396 Locks the entire stm32 device.
6397 The @var{num} parameter is a value shown by @command{flash banks}.
6400 @deffn Command {stm32lx unlock} num
6401 Unlocks the entire stm32 device.
6402 The @var{num} parameter is a value shown by @command{flash banks}.
6405 @deffn Command {stm32lx mass_erase} num
6406 Mass erases the entire stm32lx device (all flash banks and EEPROM
6407 data). This is the only way to unlock a protected flash (unless RDP
6408 Level is 2 which can't be unlocked at all).
6409 The @var{num} parameter is a value shown by @command{flash banks}.
6413 @deffn {Flash Driver} stm32l4x
6414 All members of the STM32L4 microcontroller families from ST Microelectronics
6415 include internal flash and use ARM Cortex-M4 cores.
6416 The driver automatically recognizes a number of these chips using
6417 the chip identification register, and autoconfigures itself.
6420 flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME
6423 Note that some devices have been found that have a flash size register that contains
6424 an invalid value, to workaround this issue you can override the probed value used by
6428 flash bank $_FLASHNAME stm32l4x 0x08000000 0x40000 0 0 $_TARGETNAME
6431 Some stm32l4x-specific commands are defined:
6433 @deffn Command {stm32l4x lock} num
6434 Locks the entire stm32 device.
6435 The @var{num} parameter is a value shown by @command{flash banks}.
6438 @deffn Command {stm32l4x unlock} num
6439 Unlocks the entire stm32 device.
6440 The @var{num} parameter is a value shown by @command{flash banks}.
6443 @deffn Command {stm32l4x mass_erase} num
6444 Mass erases the entire stm32l4x device.
6445 The @var{num} parameter is a value shown by @command{flash banks}.
6449 @deffn {Flash Driver} str7x
6450 All members of the STR7 microcontroller family from ST Microelectronics
6451 include internal flash and use ARM7TDMI cores.
6452 The @var{str7x} driver defines one mandatory parameter, @var{variant},
6453 which is either @code{STR71x}, @code{STR73x} or @code{STR75x}.
6456 flash bank $_FLASHNAME str7x \
6457 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
6460 @deffn Command {str7x disable_jtag} bank
6461 Activate the Debug/Readout protection mechanism
6462 for the specified flash bank.
6466 @deffn {Flash Driver} str9x
6467 Most members of the STR9 microcontroller family from ST Microelectronics
6468 include internal flash and use ARM966E cores.
6469 The str9 needs the flash controller to be configured using
6470 the @command{str9x flash_config} command prior to Flash programming.
6473 flash bank $_FLASHNAME str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
6474 str9x flash_config 0 4 2 0 0x80000
6477 @deffn Command {str9x flash_config} num bbsr nbbsr bbadr nbbadr
6478 Configures the str9 flash controller.
6479 The @var{num} parameter is a value shown by @command{flash banks}.
6482 @item @var{bbsr} - Boot Bank Size register
6483 @item @var{nbbsr} - Non Boot Bank Size register
6484 @item @var{bbadr} - Boot Bank Start Address register
6485 @item @var{nbbadr} - Boot Bank Start Address register
6491 @deffn {Flash Driver} str9xpec
6494 Only use this driver for locking/unlocking the device or configuring the option bytes.
6495 Use the standard str9 driver for programming.
6496 Before using the flash commands the turbo mode must be enabled using the
6497 @command{str9xpec enable_turbo} command.
6499 Here is some background info to help
6500 you better understand how this driver works. OpenOCD has two flash drivers for
6504 Standard driver @option{str9x} programmed via the str9 core. Normally used for
6505 flash programming as it is faster than the @option{str9xpec} driver.
6507 Direct programming @option{str9xpec} using the flash controller. This is an
6508 ISC compilant (IEEE 1532) tap connected in series with the str9 core. The str9
6509 core does not need to be running to program using this flash driver. Typical use
6510 for this driver is locking/unlocking the target and programming the option bytes.
6513 Before we run any commands using the @option{str9xpec} driver we must first disable
6514 the str9 core. This example assumes the @option{str9xpec} driver has been
6515 configured for flash bank 0.
6517 # assert srst, we do not want core running
6518 # while accessing str9xpec flash driver
6520 # turn off target polling
6523 str9xpec enable_turbo 0
6525 str9xpec options_read 0
6526 # re-enable str9 core
6527 str9xpec disable_turbo 0
6531 The above example will read the str9 option bytes.
6532 When performing a unlock remember that you will not be able to halt the str9 - it
6533 has been locked. Halting the core is not required for the @option{str9xpec} driver
6534 as mentioned above, just issue the commands above manually or from a telnet prompt.
6536 Several str9xpec-specific commands are defined:
6538 @deffn Command {str9xpec disable_turbo} num
6539 Restore the str9 into JTAG chain.
6542 @deffn Command {str9xpec enable_turbo} num
6543 Enable turbo mode, will simply remove the str9 from the chain and talk
6544 directly to the embedded flash controller.
6547 @deffn Command {str9xpec lock} num
6548 Lock str9 device. The str9 will only respond to an unlock command that will
6552 @deffn Command {str9xpec part_id} num
6553 Prints the part identifier for bank @var{num}.
6556 @deffn Command {str9xpec options_cmap} num (@option{bank0}|@option{bank1})
6557 Configure str9 boot bank.
6560 @deffn Command {str9xpec options_lvdsel} num (@option{vdd}|@option{vdd_vddq})
6561 Configure str9 lvd source.
6564 @deffn Command {str9xpec options_lvdthd} num (@option{2.4v}|@option{2.7v})
6565 Configure str9 lvd threshold.
6568 @deffn Command {str9xpec options_lvdwarn} bank (@option{vdd}|@option{vdd_vddq})
6569 Configure str9 lvd reset warning source.
6572 @deffn Command {str9xpec options_read} num
6573 Read str9 option bytes.
6576 @deffn Command {str9xpec options_write} num
6577 Write str9 option bytes.
6580 @deffn Command {str9xpec unlock} num
6586 @deffn {Flash Driver} tms470
6587 Most members of the TMS470 microcontroller family from Texas Instruments
6588 include internal flash and use ARM7TDMI cores.
6589 This driver doesn't require the chip and bus width to be specified.
6591 Some tms470-specific commands are defined:
6593 @deffn Command {tms470 flash_keyset} key0 key1 key2 key3
6594 Saves programming keys in a register, to enable flash erase and write commands.
6597 @deffn Command {tms470 osc_mhz} clock_mhz
6598 Reports the clock speed, which is used to calculate timings.
6601 @deffn Command {tms470 plldis} (0|1)
6602 Disables (@var{1}) or enables (@var{0}) use of the PLL to speed up
6607 @deffn {Flash Driver} xmc1xxx
6608 All members of the XMC1xxx microcontroller family from Infineon.
6609 This driver does not require the chip and bus width to be specified.
6612 @deffn {Flash Driver} xmc4xxx
6613 All members of the XMC4xxx microcontroller family from Infineon.
6614 This driver does not require the chip and bus width to be specified.
6616 Some xmc4xxx-specific commands are defined:
6618 @deffn Command {xmc4xxx flash_password} bank_id passwd1 passwd2
6619 Saves flash protection passwords which are used to lock the user flash
6622 @deffn Command {xmc4xxx flash_unprotect} bank_id user_level[0-1]
6623 Removes Flash write protection from the selected user bank
6628 @section NAND Flash Commands
6631 Compared to NOR or SPI flash, NAND devices are inexpensive
6632 and high density. Today's NAND chips, and multi-chip modules,
6633 commonly hold multiple GigaBytes of data.
6635 NAND chips consist of a number of ``erase blocks'' of a given
6636 size (such as 128 KBytes), each of which is divided into a
6637 number of pages (of perhaps 512 or 2048 bytes each). Each
6638 page of a NAND flash has an ``out of band'' (OOB) area to hold
6639 Error Correcting Code (ECC) and other metadata, usually 16 bytes
6640 of OOB for every 512 bytes of page data.
6642 One key characteristic of NAND flash is that its error rate
6643 is higher than that of NOR flash. In normal operation, that
6644 ECC is used to correct and detect errors. However, NAND
6645 blocks can also wear out and become unusable; those blocks
6646 are then marked "bad". NAND chips are even shipped from the
6647 manufacturer with a few bad blocks. The highest density chips
6648 use a technology (MLC) that wears out more quickly, so ECC
6649 support is increasingly important as a way to detect blocks
6650 that have begun to fail, and help to preserve data integrity
6651 with techniques such as wear leveling.
6653 Software is used to manage the ECC. Some controllers don't
6654 support ECC directly; in those cases, software ECC is used.
6655 Other controllers speed up the ECC calculations with hardware.
6656 Single-bit error correction hardware is routine. Controllers
6657 geared for newer MLC chips may correct 4 or more errors for
6658 every 512 bytes of data.
6660 You will need to make sure that any data you write using
6661 OpenOCD includes the apppropriate kind of ECC. For example,
6662 that may mean passing the @code{oob_softecc} flag when
6663 writing NAND data, or ensuring that the correct hardware
6666 The basic steps for using NAND devices include:
6668 @item Declare via the command @command{nand device}
6669 @* Do this in a board-specific configuration file,
6670 passing parameters as needed by the controller.
6671 @item Configure each device using @command{nand probe}.
6672 @* Do this only after the associated target is set up,
6673 such as in its reset-init script or in procures defined
6674 to access that device.
6675 @item Operate on the flash via @command{nand subcommand}
6676 @* Often commands to manipulate the flash are typed by a human, or run
6677 via a script in some automated way. Common task include writing a
6678 boot loader, operating system, or other data needed to initialize or
6682 @b{NOTE:} At the time this text was written, the largest NAND
6683 flash fully supported by OpenOCD is 2 GiBytes (16 GiBits).
6684 This is because the variables used to hold offsets and lengths
6685 are only 32 bits wide.
6686 (Larger chips may work in some cases, unless an offset or length
6687 is larger than 0xffffffff, the largest 32-bit unsigned integer.)
6688 Some larger devices will work, since they are actually multi-chip
6689 modules with two smaller chips and individual chipselect lines.
6691 @anchor{nandconfiguration}
6692 @subsection NAND Configuration Commands
6693 @cindex NAND configuration
6695 NAND chips must be declared in configuration scripts,
6696 plus some additional configuration that's done after
6697 OpenOCD has initialized.
6699 @deffn {Config Command} {nand device} name driver target [configparams...]
6700 Declares a NAND device, which can be read and written to
6701 after it has been configured through @command{nand probe}.
6702 In OpenOCD, devices are single chips; this is unlike some
6703 operating systems, which may manage multiple chips as if
6704 they were a single (larger) device.
6705 In some cases, configuring a device will activate extra
6706 commands; see the controller-specific documentation.
6708 @b{NOTE:} This command is not available after OpenOCD
6709 initialization has completed. Use it in board specific
6710 configuration files, not interactively.
6713 @item @var{name} ... may be used to reference the NAND bank
6714 in most other NAND commands. A number is also available.
6715 @item @var{driver} ... identifies the NAND controller driver
6716 associated with the NAND device being declared.
6717 @xref{nanddriverlist,,NAND Driver List}.
6718 @item @var{target} ... names the target used when issuing
6719 commands to the NAND controller.
6720 @comment Actually, it's currently a controller-specific parameter...
6721 @item @var{configparams} ... controllers may support, or require,
6722 additional parameters. See the controller-specific documentation
6723 for more information.
6727 @deffn Command {nand list}
6728 Prints a summary of each device declared
6729 using @command{nand device}, numbered from zero.
6730 Note that un-probed devices show no details.
6733 #0: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
6734 blocksize: 131072, blocks: 8192
6735 #1: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
6736 blocksize: 131072, blocks: 8192
6741 @deffn Command {nand probe} num
6742 Probes the specified device to determine key characteristics
6743 like its page and block sizes, and how many blocks it has.
6744 The @var{num} parameter is the value shown by @command{nand list}.
6745 You must (successfully) probe a device before you can use
6746 it with most other NAND commands.
6749 @subsection Erasing, Reading, Writing to NAND Flash
6751 @deffn Command {nand dump} num filename offset length [oob_option]
6752 @cindex NAND reading
6753 Reads binary data from the NAND device and writes it to the file,
6754 starting at the specified offset.
6755 The @var{num} parameter is the value shown by @command{nand list}.
6757 Use a complete path name for @var{filename}, so you don't depend
6758 on the directory used to start the OpenOCD server.
6760 The @var{offset} and @var{length} must be exact multiples of the
6761 device's page size. They describe a data region; the OOB data
6762 associated with each such page may also be accessed.
6764 @b{NOTE:} At the time this text was written, no error correction
6765 was done on the data that's read, unless raw access was disabled
6766 and the underlying NAND controller driver had a @code{read_page}
6767 method which handled that error correction.
6769 By default, only page data is saved to the specified file.
6770 Use an @var{oob_option} parameter to save OOB data:
6772 @item no oob_* parameter
6773 @*Output file holds only page data; OOB is discarded.
6774 @item @code{oob_raw}
6775 @*Output file interleaves page data and OOB data;
6776 the file will be longer than "length" by the size of the
6777 spare areas associated with each data page.
6778 Note that this kind of "raw" access is different from
6779 what's implied by @command{nand raw_access}, which just
6780 controls whether a hardware-aware access method is used.
6781 @item @code{oob_only}
6782 @*Output file has only raw OOB data, and will
6783 be smaller than "length" since it will contain only the
6784 spare areas associated with each data page.
6788 @deffn Command {nand erase} num [offset length]
6789 @cindex NAND erasing
6790 @cindex NAND programming
6791 Erases blocks on the specified NAND device, starting at the
6792 specified @var{offset} and continuing for @var{length} bytes.
6793 Both of those values must be exact multiples of the device's
6794 block size, and the region they specify must fit entirely in the chip.
6795 If those parameters are not specified,
6796 the whole NAND chip will be erased.
6797 The @var{num} parameter is the value shown by @command{nand list}.
6799 @b{NOTE:} This command will try to erase bad blocks, when told
6800 to do so, which will probably invalidate the manufacturer's bad
6802 For the remainder of the current server session, @command{nand info}
6803 will still report that the block ``is'' bad.
6806 @deffn Command {nand write} num filename offset [option...]
6807 @cindex NAND writing
6808 @cindex NAND programming
6809 Writes binary data from the file into the specified NAND device,
6810 starting at the specified offset. Those pages should already
6811 have been erased; you can't change zero bits to one bits.
6812 The @var{num} parameter is the value shown by @command{nand list}.
6814 Use a complete path name for @var{filename}, so you don't depend
6815 on the directory used to start the OpenOCD server.
6817 The @var{offset} must be an exact multiple of the device's page size.
6818 All data in the file will be written, assuming it doesn't run
6819 past the end of the device.
6820 Only full pages are written, and any extra space in the last
6821 page will be filled with 0xff bytes. (That includes OOB data,
6822 if that's being written.)
6824 @b{NOTE:} At the time this text was written, bad blocks are
6825 ignored. That is, this routine will not skip bad blocks,
6826 but will instead try to write them. This can cause problems.
6828 Provide at most one @var{option} parameter. With some
6829 NAND drivers, the meanings of these parameters may change
6830 if @command{nand raw_access} was used to disable hardware ECC.
6832 @item no oob_* parameter
6833 @*File has only page data, which is written.
6834 If raw acccess is in use, the OOB area will not be written.
6835 Otherwise, if the underlying NAND controller driver has
6836 a @code{write_page} routine, that routine may write the OOB
6837 with hardware-computed ECC data.
6838 @item @code{oob_only}
6839 @*File has only raw OOB data, which is written to the OOB area.
6840 Each page's data area stays untouched. @i{This can be a dangerous
6841 option}, since it can invalidate the ECC data.
6842 You may need to force raw access to use this mode.
6843 @item @code{oob_raw}
6844 @*File interleaves data and OOB data, both of which are written
6845 If raw access is enabled, the data is written first, then the
6847 Otherwise, if the underlying NAND controller driver has
6848 a @code{write_page} routine, that routine may modify the OOB
6849 before it's written, to include hardware-computed ECC data.
6850 @item @code{oob_softecc}
6851 @*File has only page data, which is written.
6852 The OOB area is filled with 0xff, except for a standard 1-bit
6853 software ECC code stored in conventional locations.
6854 You might need to force raw access to use this mode, to prevent
6855 the underlying driver from applying hardware ECC.
6856 @item @code{oob_softecc_kw}
6857 @*File has only page data, which is written.
6858 The OOB area is filled with 0xff, except for a 4-bit software ECC
6859 specific to the boot ROM in Marvell Kirkwood SoCs.
6860 You might need to force raw access to use this mode, to prevent
6861 the underlying driver from applying hardware ECC.
6865 @deffn Command {nand verify} num filename offset [option...]
6866 @cindex NAND verification
6867 @cindex NAND programming
6868 Verify the binary data in the file has been programmed to the
6869 specified NAND device, starting at the specified offset.
6870 The @var{num} parameter is the value shown by @command{nand list}.
6872 Use a complete path name for @var{filename}, so you don't depend
6873 on the directory used to start the OpenOCD server.
6875 The @var{offset} must be an exact multiple of the device's page size.
6876 All data in the file will be read and compared to the contents of the
6877 flash, assuming it doesn't run past the end of the device.
6878 As with @command{nand write}, only full pages are verified, so any extra
6879 space in the last page will be filled with 0xff bytes.
6881 The same @var{options} accepted by @command{nand write},
6882 and the file will be processed similarly to produce the buffers that
6883 can be compared against the contents produced from @command{nand dump}.
6885 @b{NOTE:} This will not work when the underlying NAND controller
6886 driver's @code{write_page} routine must update the OOB with a
6887 hardward-computed ECC before the data is written. This limitation may
6888 be removed in a future release.
6891 @subsection Other NAND commands
6892 @cindex NAND other commands
6894 @deffn Command {nand check_bad_blocks} num [offset length]
6895 Checks for manufacturer bad block markers on the specified NAND
6896 device. If no parameters are provided, checks the whole
6897 device; otherwise, starts at the specified @var{offset} and
6898 continues for @var{length} bytes.
6899 Both of those values must be exact multiples of the device's
6900 block size, and the region they specify must fit entirely in the chip.
6901 The @var{num} parameter is the value shown by @command{nand list}.
6903 @b{NOTE:} Before using this command you should force raw access
6904 with @command{nand raw_access enable} to ensure that the underlying
6905 driver will not try to apply hardware ECC.
6908 @deffn Command {nand info} num
6909 The @var{num} parameter is the value shown by @command{nand list}.
6910 This prints the one-line summary from "nand list", plus for
6911 devices which have been probed this also prints any known
6912 status for each block.
6915 @deffn Command {nand raw_access} num (@option{enable}|@option{disable})
6916 Sets or clears an flag affecting how page I/O is done.
6917 The @var{num} parameter is the value shown by @command{nand list}.
6919 This flag is cleared (disabled) by default, but changing that
6920 value won't affect all NAND devices. The key factor is whether
6921 the underlying driver provides @code{read_page} or @code{write_page}
6922 methods. If it doesn't provide those methods, the setting of
6923 this flag is irrelevant; all access is effectively ``raw''.
6925 When those methods exist, they are normally used when reading
6926 data (@command{nand dump} or reading bad block markers) or
6927 writing it (@command{nand write}). However, enabling
6928 raw access (setting the flag) prevents use of those methods,
6929 bypassing hardware ECC logic.
6930 @i{This can be a dangerous option}, since writing blocks
6931 with the wrong ECC data can cause them to be marked as bad.
6934 @anchor{nanddriverlist}
6935 @subsection NAND Driver List
6936 As noted above, the @command{nand device} command allows
6937 driver-specific options and behaviors.
6938 Some controllers also activate controller-specific commands.
6940 @deffn {NAND Driver} at91sam9
6941 This driver handles the NAND controllers found on AT91SAM9 family chips from
6942 Atmel. It takes two extra parameters: address of the NAND chip;
6943 address of the ECC controller.
6945 nand device $NANDFLASH at91sam9 $CHIPNAME 0x40000000 0xfffffe800
6947 AT91SAM9 chips support single-bit ECC hardware. The @code{write_page} and
6948 @code{read_page} methods are used to utilize the ECC hardware unless they are
6949 disabled by using the @command{nand raw_access} command. There are four
6950 additional commands that are needed to fully configure the AT91SAM9 NAND
6951 controller. Two are optional; most boards use the same wiring for ALE/CLE:
6952 @deffn Command {at91sam9 cle} num addr_line
6953 Configure the address line used for latching commands. The @var{num}
6954 parameter is the value shown by @command{nand list}.
6956 @deffn Command {at91sam9 ale} num addr_line
6957 Configure the address line used for latching addresses. The @var{num}
6958 parameter is the value shown by @command{nand list}.
6961 For the next two commands, it is assumed that the pins have already been
6962 properly configured for input or output.
6963 @deffn Command {at91sam9 rdy_busy} num pio_base_addr pin
6964 Configure the RDY/nBUSY input from the NAND device. The @var{num}
6965 parameter is the value shown by @command{nand list}. @var{pio_base_addr}
6966 is the base address of the PIO controller and @var{pin} is the pin number.
6968 @deffn Command {at91sam9 ce} num pio_base_addr pin
6969 Configure the chip enable input to the NAND device. The @var{num}
6970 parameter is the value shown by @command{nand list}. @var{pio_base_addr}
6971 is the base address of the PIO controller and @var{pin} is the pin number.
6975 @deffn {NAND Driver} davinci
6976 This driver handles the NAND controllers found on DaVinci family
6977 chips from Texas Instruments.
6978 It takes three extra parameters:
6979 address of the NAND chip;
6980 hardware ECC mode to use (@option{hwecc1},
6981 @option{hwecc4}, @option{hwecc4_infix});
6982 address of the AEMIF controller on this processor.
6984 nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000
6986 All DaVinci processors support the single-bit ECC hardware,
6987 and newer ones also support the four-bit ECC hardware.
6988 The @code{write_page} and @code{read_page} methods are used
6989 to implement those ECC modes, unless they are disabled using
6990 the @command{nand raw_access} command.
6993 @deffn {NAND Driver} lpc3180
6994 These controllers require an extra @command{nand device}
6995 parameter: the clock rate used by the controller.
6996 @deffn Command {lpc3180 select} num [mlc|slc]
6997 Configures use of the MLC or SLC controller mode.
6998 MLC implies use of hardware ECC.
6999 The @var{num} parameter is the value shown by @command{nand list}.
7002 At this writing, this driver includes @code{write_page}
7003 and @code{read_page} methods. Using @command{nand raw_access}
7004 to disable those methods will prevent use of hardware ECC
7005 in the MLC controller mode, but won't change SLC behavior.
7007 @comment current lpc3180 code won't issue 5-byte address cycles
7009 @deffn {NAND Driver} mx3
7010 This driver handles the NAND controller in i.MX31. The mxc driver
7011 should work for this chip aswell.
7014 @deffn {NAND Driver} mxc
7015 This driver handles the NAND controller found in Freescale i.MX
7016 chips. It has support for v1 (i.MX27 and i.MX31) and v2 (i.MX35).
7017 The driver takes 3 extra arguments, chip (@option{mx27},
7018 @option{mx31}, @option{mx35}), ecc (@option{noecc}, @option{hwecc})
7019 and optionally if bad block information should be swapped between
7020 main area and spare area (@option{biswap}), defaults to off.
7022 nand device mx35.nand mxc imx35.cpu mx35 hwecc biswap
7024 @deffn Command {mxc biswap} bank_num [enable|disable]
7025 Turns on/off bad block information swaping from main area,
7026 without parameter query status.
7030 @deffn {NAND Driver} orion
7031 These controllers require an extra @command{nand device}
7032 parameter: the address of the controller.
7034 nand device orion 0xd8000000
7036 These controllers don't define any specialized commands.
7037 At this writing, their drivers don't include @code{write_page}
7038 or @code{read_page} methods, so @command{nand raw_access} won't
7039 change any behavior.
7042 @deffn {NAND Driver} s3c2410
7043 @deffnx {NAND Driver} s3c2412
7044 @deffnx {NAND Driver} s3c2440
7045 @deffnx {NAND Driver} s3c2443
7046 @deffnx {NAND Driver} s3c6400
7047 These S3C family controllers don't have any special
7048 @command{nand device} options, and don't define any
7049 specialized commands.
7050 At this writing, their drivers don't include @code{write_page}
7051 or @code{read_page} methods, so @command{nand raw_access} won't
7052 change any behavior.
7057 @subsection mFlash Configuration
7058 @cindex mFlash Configuration
7060 @deffn {Config Command} {mflash bank} soc base RST_pin target
7061 Configures a mflash for @var{soc} host bank at
7063 The pin number format depends on the host GPIO naming convention.
7064 Currently, the mflash driver supports s3c2440 and pxa270.
7066 Example for s3c2440 mflash where @var{RST pin} is GPIO B1:
7069 mflash bank $_FLASHNAME s3c2440 0x10000000 1b 0
7072 Example for pxa270 mflash where @var{RST pin} is GPIO 43:
7075 mflash bank $_FLASHNAME pxa270 0x08000000 43 0
7079 @subsection mFlash commands
7080 @cindex mFlash commands
7082 @deffn Command {mflash config pll} frequency
7083 Configure mflash PLL.
7084 The @var{frequency} is the mflash input frequency, in Hz.
7085 Issuing this command will erase mflash's whole internal nand and write new pll.
7086 After this command, mflash needs power-on-reset for normal operation.
7087 If pll was newly configured, storage and boot(optional) info also need to be update.
7090 @deffn Command {mflash config boot}
7091 Configure bootable option.
7092 If bootable option is set, mflash offer the first 8 sectors
7096 @deffn Command {mflash config storage}
7097 Configure storage information.
7098 For the normal storage operation, this information must be
7102 @deffn Command {mflash dump} num filename offset size
7103 Dump @var{size} bytes, starting at @var{offset} bytes from the
7104 beginning of the bank @var{num}, to the file named @var{filename}.
7107 @deffn Command {mflash probe}
7111 @deffn Command {mflash write} num filename offset
7112 Write the binary file @var{filename} to mflash bank @var{num}, starting at
7113 @var{offset} bytes from the beginning of the bank.
7116 @node Flash Programming
7117 @chapter Flash Programming
7119 OpenOCD implements numerous ways to program the target flash, whether internal or external.
7120 Programming can be acheived by either using GDB @ref{programmingusinggdb,,Programming using GDB},
7121 or using the cmds given in @ref{flashprogrammingcommands,,Flash Programming Commands}.
7123 @*To simplify using the flash cmds directly a jimtcl script is available that handles the programming and verify stage.
7124 OpenOCD will program/verify/reset the target and optionally shutdown.
7126 The script is executed as follows and by default the following actions will be peformed.
7128 @item 'init' is executed.
7129 @item 'reset init' is called to reset and halt the target, any 'reset init' scripts are executed.
7130 @item @code{flash write_image} is called to erase and write any flash using the filename given.
7131 @item @code{verify_image} is called if @option{verify} parameter is given.
7132 @item @code{reset run} is called if @option{reset} parameter is given.
7133 @item OpenOCD is shutdown if @option{exit} parameter is given.
7136 An example of usage is given below. @xref{program}.
7139 # program and verify using elf/hex/s19. verify and reset
7140 # are optional parameters
7141 openocd -f board/stm32f3discovery.cfg \
7142 -c "program filename.elf verify reset exit"
7144 # binary files need the flash address passing
7145 openocd -f board/stm32f3discovery.cfg \
7146 -c "program filename.bin exit 0x08000000"
7149 @node PLD/FPGA Commands
7150 @chapter PLD/FPGA Commands
7154 Programmable Logic Devices (PLDs) and the more flexible
7155 Field Programmable Gate Arrays (FPGAs) are both types of programmable hardware.
7156 OpenOCD can support programming them.
7157 Although PLDs are generally restrictive (cells are less functional, and
7158 there are no special purpose cells for memory or computational tasks),
7159 they share the same OpenOCD infrastructure.
7160 Accordingly, both are called PLDs here.
7162 @section PLD/FPGA Configuration and Commands
7164 As it does for JTAG TAPs, debug targets, and flash chips (both NOR and NAND),
7165 OpenOCD maintains a list of PLDs available for use in various commands.
7166 Also, each such PLD requires a driver.
7168 They are referenced by the number shown by the @command{pld devices} command,
7169 and new PLDs are defined by @command{pld device driver_name}.
7171 @deffn {Config Command} {pld device} driver_name tap_name [driver_options]
7172 Defines a new PLD device, supported by driver @var{driver_name},
7173 using the TAP named @var{tap_name}.
7174 The driver may make use of any @var{driver_options} to configure its
7178 @deffn {Command} {pld devices}
7179 Lists the PLDs and their numbers.
7182 @deffn {Command} {pld load} num filename
7183 Loads the file @file{filename} into the PLD identified by @var{num}.
7184 The file format must be inferred by the driver.
7187 @section PLD/FPGA Drivers, Options, and Commands
7189 Drivers may support PLD-specific options to the @command{pld device}
7190 definition command, and may also define commands usable only with
7191 that particular type of PLD.
7193 @deffn {FPGA Driver} virtex2 [no_jstart]
7194 Virtex-II is a family of FPGAs sold by Xilinx.
7195 It supports the IEEE 1532 standard for In-System Configuration (ISC).
7197 If @var{no_jstart} is non-zero, the JSTART instruction is not used after
7198 loading the bitstream. While required for Series2, Series3, and Series6, it
7199 breaks bitstream loading on Series7.
7201 @deffn {Command} {virtex2 read_stat} num
7202 Reads and displays the Virtex-II status register (STAT)
7207 @node General Commands
7208 @chapter General Commands
7211 The commands documented in this chapter here are common commands that
7212 you, as a human, may want to type and see the output of. Configuration type
7213 commands are documented elsewhere.
7217 @item @b{Source Of Commands}
7218 @* OpenOCD commands can occur in a configuration script (discussed
7219 elsewhere) or typed manually by a human or supplied programatically,
7220 or via one of several TCP/IP Ports.
7222 @item @b{From the human}
7223 @* A human should interact with the telnet interface (default port: 4444)
7224 or via GDB (default port 3333).
7226 To issue commands from within a GDB session, use the @option{monitor}
7227 command, e.g. use @option{monitor poll} to issue the @option{poll}
7228 command. All output is relayed through the GDB session.
7230 @item @b{Machine Interface}
7231 The Tcl interface's intent is to be a machine interface. The default Tcl
7236 @section Server Commands
7238 @deffn {Command} exit
7239 Exits the current telnet session.
7242 @deffn {Command} help [string]
7243 With no parameters, prints help text for all commands.
7244 Otherwise, prints each helptext containing @var{string}.
7245 Not every command provides helptext.
7247 Configuration commands, and commands valid at any time, are
7248 explicitly noted in parenthesis.
7249 In most cases, no such restriction is listed; this indicates commands
7250 which are only available after the configuration stage has completed.
7253 @deffn Command sleep msec [@option{busy}]
7254 Wait for at least @var{msec} milliseconds before resuming.
7255 If @option{busy} is passed, busy-wait instead of sleeping.
7256 (This option is strongly discouraged.)
7257 Useful in connection with script files
7258 (@command{script} command and @command{target_name} configuration).
7261 @deffn Command shutdown [@option{error}]
7262 Close the OpenOCD server, disconnecting all clients (GDB, telnet,
7263 other). If option @option{error} is used, OpenOCD will return a
7264 non-zero exit code to the parent process.
7268 @deffn Command debug_level [n]
7269 @cindex message level
7270 Display debug level.
7271 If @var{n} (from 0..4) is provided, then set it to that level.
7272 This affects the kind of messages sent to the server log.
7273 Level 0 is error messages only;
7274 level 1 adds warnings;
7275 level 2 adds informational messages;
7276 level 3 adds debugging messages;
7277 and level 4 adds verbose low-level debug messages.
7278 The default is level 2, but that can be overridden on
7279 the command line along with the location of that log
7280 file (which is normally the server's standard output).
7284 @deffn Command echo [-n] message
7285 Logs a message at "user" priority.
7286 Output @var{message} to stdout.
7287 Option "-n" suppresses trailing newline.
7289 echo "Downloading kernel -- please wait"
7293 @deffn Command log_output [filename]
7294 Redirect logging to @var{filename};
7295 the initial log output channel is stderr.
7298 @deffn Command add_script_search_dir [directory]
7299 Add @var{directory} to the file/script search path.
7302 @deffn Command bindto [@var{name}]
7303 Specify hostname or IPv4 address on which to listen for incoming
7304 TCP/IP connections. By default, OpenOCD will listen on the loopback
7305 interface only. If your network environment is safe, @code{bindto
7306 0.0.0.0} can be used to cover all available interfaces.
7309 @anchor{targetstatehandling}
7310 @section Target State handling
7313 @cindex target initialization
7315 In this section ``target'' refers to a CPU configured as
7316 shown earlier (@pxref{CPU Configuration}).
7317 These commands, like many, implicitly refer to
7318 a current target which is used to perform the
7319 various operations. The current target may be changed
7320 by using @command{targets} command with the name of the
7321 target which should become current.
7323 @deffn Command reg [(number|name) [(value|'force')]]
7324 Access a single register by @var{number} or by its @var{name}.
7325 The target must generally be halted before access to CPU core
7326 registers is allowed. Depending on the hardware, some other
7327 registers may be accessible while the target is running.
7329 @emph{With no arguments}:
7330 list all available registers for the current target,
7331 showing number, name, size, value, and cache status.
7332 For valid entries, a value is shown; valid entries
7333 which are also dirty (and will be written back later)
7334 are flagged as such.
7336 @emph{With number/name}: display that register's value.
7337 Use @var{force} argument to read directly from the target,
7338 bypassing any internal cache.
7340 @emph{With both number/name and value}: set register's value.
7341 Writes may be held in a writeback cache internal to OpenOCD,
7342 so that setting the value marks the register as dirty instead
7343 of immediately flushing that value. Resuming CPU execution
7344 (including by single stepping) or otherwise activating the
7345 relevant module will flush such values.
7347 Cores may have surprisingly many registers in their
7348 Debug and trace infrastructure:
7353 (0) r0 (/32): 0x0000D3C2 (dirty)
7354 (1) r1 (/32): 0xFD61F31C
7357 (164) ETM_contextid_comparator_mask (/32)
7362 @deffn Command halt [ms]
7363 @deffnx Command wait_halt [ms]
7364 The @command{halt} command first sends a halt request to the target,
7365 which @command{wait_halt} doesn't.
7366 Otherwise these behave the same: wait up to @var{ms} milliseconds,
7367 or 5 seconds if there is no parameter, for the target to halt
7368 (and enter debug mode).
7369 Using 0 as the @var{ms} parameter prevents OpenOCD from waiting.
7372 On ARM cores, software using the @emph{wait for interrupt} operation
7373 often blocks the JTAG access needed by a @command{halt} command.
7374 This is because that operation also puts the core into a low
7375 power mode by gating the core clock;
7376 but the core clock is needed to detect JTAG clock transitions.
7378 One partial workaround uses adaptive clocking: when the core is
7379 interrupted the operation completes, then JTAG clocks are accepted
7380 at least until the interrupt handler completes.
7381 However, this workaround is often unusable since the processor, board,
7382 and JTAG adapter must all support adaptive JTAG clocking.
7383 Also, it can't work until an interrupt is issued.
7385 A more complete workaround is to not use that operation while you
7386 work with a JTAG debugger.
7387 Tasking environments generaly have idle loops where the body is the
7388 @emph{wait for interrupt} operation.
7389 (On older cores, it is a coprocessor action;
7390 newer cores have a @option{wfi} instruction.)
7391 Such loops can just remove that operation, at the cost of higher
7392 power consumption (because the CPU is needlessly clocked).
7397 @deffn Command resume [address]
7398 Resume the target at its current code position,
7399 or the optional @var{address} if it is provided.
7400 OpenOCD will wait 5 seconds for the target to resume.
7403 @deffn Command step [address]
7404 Single-step the target at its current code position,
7405 or the optional @var{address} if it is provided.
7408 @anchor{resetcommand}
7409 @deffn Command reset
7410 @deffnx Command {reset run}
7411 @deffnx Command {reset halt}
7412 @deffnx Command {reset init}
7413 Perform as hard a reset as possible, using SRST if possible.
7414 @emph{All defined targets will be reset, and target
7415 events will fire during the reset sequence.}
7417 The optional parameter specifies what should
7418 happen after the reset.
7419 If there is no parameter, a @command{reset run} is executed.
7420 The other options will not work on all systems.
7421 @xref{Reset Configuration}.
7424 @item @b{run} Let the target run
7425 @item @b{halt} Immediately halt the target
7426 @item @b{init} Immediately halt the target, and execute the reset-init script
7430 @deffn Command soft_reset_halt
7431 Requesting target halt and executing a soft reset. This is often used
7432 when a target cannot be reset and halted. The target, after reset is
7433 released begins to execute code. OpenOCD attempts to stop the CPU and
7434 then sets the program counter back to the reset vector. Unfortunately
7435 the code that was executed may have left the hardware in an unknown
7439 @section I/O Utilities
7441 These commands are available when
7442 OpenOCD is built with @option{--enable-ioutil}.
7443 They are mainly useful on embedded targets,
7445 Hosts with operating systems have complementary tools.
7447 @emph{Note:} there are several more such commands.
7449 @deffn Command append_file filename [string]*
7450 Appends the @var{string} parameters to
7451 the text file @file{filename}.
7452 Each string except the last one is followed by one space.
7453 The last string is followed by a newline.
7456 @deffn Command cat filename
7457 Reads and displays the text file @file{filename}.
7460 @deffn Command cp src_filename dest_filename
7461 Copies contents from the file @file{src_filename}
7462 into @file{dest_filename}.
7466 @emph{No description provided.}
7470 @emph{No description provided.}
7474 @emph{No description provided.}
7477 @deffn Command meminfo
7478 Display available RAM memory on OpenOCD host.
7479 Used in OpenOCD regression testing scripts.
7483 @emph{No description provided.}
7487 @emph{No description provided.}
7490 @deffn Command rm filename
7491 @c "rm" has both normal and Jim-level versions??
7492 Unlinks the file @file{filename}.
7495 @deffn Command trunc filename
7496 Removes all data in the file @file{filename}.
7499 @anchor{memoryaccess}
7500 @section Memory access commands
7501 @cindex memory access
7503 These commands allow accesses of a specific size to the memory
7504 system. Often these are used to configure the current target in some
7505 special way. For example - one may need to write certain values to the
7506 SDRAM controller to enable SDRAM.
7509 @item Use the @command{targets} (plural) command
7510 to change the current target.
7511 @item In system level scripts these commands are deprecated.
7512 Please use their TARGET object siblings to avoid making assumptions
7513 about what TAP is the current target, or about MMU configuration.
7516 @deffn Command mdw [phys] addr [count]
7517 @deffnx Command mdh [phys] addr [count]
7518 @deffnx Command mdb [phys] addr [count]
7519 Display contents of address @var{addr}, as
7520 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
7521 or 8-bit bytes (@command{mdb}).
7522 When the current target has an MMU which is present and active,
7523 @var{addr} is interpreted as a virtual address.
7524 Otherwise, or if the optional @var{phys} flag is specified,
7525 @var{addr} is interpreted as a physical address.
7526 If @var{count} is specified, displays that many units.
7527 (If you want to manipulate the data instead of displaying it,
7528 see the @code{mem2array} primitives.)
7531 @deffn Command mww [phys] addr word
7532 @deffnx Command mwh [phys] addr halfword
7533 @deffnx Command mwb [phys] addr byte
7534 Writes the specified @var{word} (32 bits),
7535 @var{halfword} (16 bits), or @var{byte} (8-bit) value,
7536 at the specified address @var{addr}.
7537 When the current target has an MMU which is present and active,
7538 @var{addr} is interpreted as a virtual address.
7539 Otherwise, or if the optional @var{phys} flag is specified,
7540 @var{addr} is interpreted as a physical address.
7543 @anchor{imageaccess}
7544 @section Image loading commands
7545 @cindex image loading
7546 @cindex image dumping
7548 @deffn Command {dump_image} filename address size
7549 Dump @var{size} bytes of target memory starting at @var{address} to the
7550 binary file named @var{filename}.
7553 @deffn Command {fast_load}
7554 Loads an image stored in memory by @command{fast_load_image} to the
7555 current target. Must be preceeded by fast_load_image.
7558 @deffn Command {fast_load_image} filename address [@option{bin}|@option{ihex}|@option{elf}|@option{s19}]
7559 Normally you should be using @command{load_image} or GDB load. However, for
7560 testing purposes or when I/O overhead is significant(OpenOCD running on an embedded
7561 host), storing the image in memory and uploading the image to the target
7562 can be a way to upload e.g. multiple debug sessions when the binary does not change.
7563 Arguments are the same as @command{load_image}, but the image is stored in OpenOCD host
7564 memory, i.e. does not affect target. This approach is also useful when profiling
7565 target programming performance as I/O and target programming can easily be profiled
7569 @deffn Command {load_image} filename address [[@option{bin}|@option{ihex}|@option{elf}|@option{s19}] @option{min_addr} @option{max_length}]
7570 Load image from file @var{filename} to target memory offset by @var{address} from its load address.
7571 The file format may optionally be specified
7572 (@option{bin}, @option{ihex}, @option{elf}, or @option{s19}).
7573 In addition the following arguments may be specifed:
7574 @var{min_addr} - ignore data below @var{min_addr} (this is w.r.t. to the target's load address + @var{address})
7575 @var{max_length} - maximum number of bytes to load.
7577 proc load_image_bin @{fname foffset address length @} @{
7578 # Load data from fname filename at foffset offset to
7579 # target at address. Load at most length bytes.
7580 load_image $fname [expr $address - $foffset] bin \
7586 @deffn Command {test_image} filename [address [@option{bin}|@option{ihex}|@option{elf}]]
7587 Displays image section sizes and addresses
7588 as if @var{filename} were loaded into target memory
7589 starting at @var{address} (defaults to zero).
7590 The file format may optionally be specified
7591 (@option{bin}, @option{ihex}, or @option{elf})
7594 @deffn Command {verify_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
7595 Verify @var{filename} against target memory starting at @var{address}.
7596 The file format may optionally be specified
7597 (@option{bin}, @option{ihex}, or @option{elf})
7598 This will first attempt a comparison using a CRC checksum, if this fails it will try a binary compare.
7601 @deffn Command {verify_image_checksum} filename address [@option{bin}|@option{ihex}|@option{elf}]
7602 Verify @var{filename} against target memory starting at @var{address}.
7603 The file format may optionally be specified
7604 (@option{bin}, @option{ihex}, or @option{elf})
7605 This perform a comparison using a CRC checksum only
7609 @section Breakpoint and Watchpoint commands
7613 CPUs often make debug modules accessible through JTAG, with
7614 hardware support for a handful of code breakpoints and data
7616 In addition, CPUs almost always support software breakpoints.
7618 @deffn Command {bp} [address len [@option{hw}]]
7619 With no parameters, lists all active breakpoints.
7620 Else sets a breakpoint on code execution starting
7621 at @var{address} for @var{length} bytes.
7622 This is a software breakpoint, unless @option{hw} is specified
7623 in which case it will be a hardware breakpoint.
7625 (@xref{arm9vectorcatch,,arm9 vector_catch}, or @pxref{xscalevectorcatch,,xscale vector_catch},
7626 for similar mechanisms that do not consume hardware breakpoints.)
7629 @deffn Command {rbp} address
7630 Remove the breakpoint at @var{address}.
7633 @deffn Command {rwp} address
7634 Remove data watchpoint on @var{address}
7637 @deffn Command {wp} [address len [(@option{r}|@option{w}|@option{a}) [value [mask]]]]
7638 With no parameters, lists all active watchpoints.
7639 Else sets a data watchpoint on data from @var{address} for @var{length} bytes.
7640 The watch point is an "access" watchpoint unless
7641 the @option{r} or @option{w} parameter is provided,
7642 defining it as respectively a read or write watchpoint.
7643 If a @var{value} is provided, that value is used when determining if
7644 the watchpoint should trigger. The value may be first be masked
7645 using @var{mask} to mark ``don't care'' fields.
7648 @section Misc Commands
7651 @deffn Command {profile} seconds filename [start end]
7652 Profiling samples the CPU's program counter as quickly as possible,
7653 which is useful for non-intrusive stochastic profiling.
7654 Saves up to 10000 samples in @file{filename} using ``gmon.out''
7655 format. Optional @option{start} and @option{end} parameters allow to
7656 limit the address range.
7659 @deffn Command {version}
7660 Displays a string identifying the version of this OpenOCD server.
7663 @deffn Command {virt2phys} virtual_address
7664 Requests the current target to map the specified @var{virtual_address}
7665 to its corresponding physical address, and displays the result.
7668 @node Architecture and Core Commands
7669 @chapter Architecture and Core Commands
7670 @cindex Architecture Specific Commands
7671 @cindex Core Specific Commands
7673 Most CPUs have specialized JTAG operations to support debugging.
7674 OpenOCD packages most such operations in its standard command framework.
7675 Some of those operations don't fit well in that framework, so they are
7676 exposed here as architecture or implementation (core) specific commands.
7678 @anchor{armhardwaretracing}
7679 @section ARM Hardware Tracing
7684 CPUs based on ARM cores may include standard tracing interfaces,
7685 based on an ``Embedded Trace Module'' (ETM) which sends voluminous
7686 address and data bus trace records to a ``Trace Port''.
7690 Development-oriented boards will sometimes provide a high speed
7691 trace connector for collecting that data, when the particular CPU
7692 supports such an interface.
7693 (The standard connector is a 38-pin Mictor, with both JTAG
7694 and trace port support.)
7695 Those trace connectors are supported by higher end JTAG adapters
7696 and some logic analyzer modules; frequently those modules can
7697 buffer several megabytes of trace data.
7698 Configuring an ETM coupled to such an external trace port belongs
7699 in the board-specific configuration file.
7701 If the CPU doesn't provide an external interface, it probably
7702 has an ``Embedded Trace Buffer'' (ETB) on the chip, which is a
7703 dedicated SRAM. 4KBytes is one common ETB size.
7704 Configuring an ETM coupled only to an ETB belongs in the CPU-specific
7705 (target) configuration file, since it works the same on all boards.
7708 ETM support in OpenOCD doesn't seem to be widely used yet.
7711 ETM support may be buggy, and at least some @command{etm config}
7712 parameters should be detected by asking the ETM for them.
7714 ETM trigger events could also implement a kind of complex
7715 hardware breakpoint, much more powerful than the simple
7716 watchpoint hardware exported by EmbeddedICE modules.
7717 @emph{Such breakpoints can be triggered even when using the
7718 dummy trace port driver}.
7720 It seems like a GDB hookup should be possible,
7721 as well as tracing only during specific states
7722 (perhaps @emph{handling IRQ 23} or @emph{calls foo()}).
7724 There should be GUI tools to manipulate saved trace data and help
7725 analyse it in conjunction with the source code.
7726 It's unclear how much of a common interface is shared
7727 with the current XScale trace support, or should be
7728 shared with eventual Nexus-style trace module support.
7730 At this writing (November 2009) only ARM7, ARM9, and ARM11 support
7731 for ETM modules is available. The code should be able to
7732 work with some newer cores; but not all of them support
7733 this original style of JTAG access.
7736 @subsection ETM Configuration
7737 ETM setup is coupled with the trace port driver configuration.
7739 @deffn {Config Command} {etm config} target width mode clocking driver
7740 Declares the ETM associated with @var{target}, and associates it
7741 with a given trace port @var{driver}. @xref{traceportdrivers,,Trace Port Drivers}.
7743 Several of the parameters must reflect the trace port capabilities,
7744 which are a function of silicon capabilties (exposed later
7745 using @command{etm info}) and of what hardware is connected to
7746 that port (such as an external pod, or ETB).
7747 The @var{width} must be either 4, 8, or 16,
7748 except with ETMv3.0 and newer modules which may also
7749 support 1, 2, 24, 32, 48, and 64 bit widths.
7750 (With those versions, @command{etm info} also shows whether
7751 the selected port width and mode are supported.)
7753 The @var{mode} must be @option{normal}, @option{multiplexed},
7754 or @option{demultiplexed}.
7755 The @var{clocking} must be @option{half} or @option{full}.
7758 With ETMv3.0 and newer, the bits set with the @var{mode} and
7759 @var{clocking} parameters both control the mode.
7760 This modified mode does not map to the values supported by
7761 previous ETM modules, so this syntax is subject to change.
7765 You can see the ETM registers using the @command{reg} command.
7766 Not all possible registers are present in every ETM.
7767 Most of the registers are write-only, and are used to configure
7768 what CPU activities are traced.
7772 @deffn Command {etm info}
7773 Displays information about the current target's ETM.
7774 This includes resource counts from the @code{ETM_CONFIG} register,
7775 as well as silicon capabilities (except on rather old modules).
7776 from the @code{ETM_SYS_CONFIG} register.
7779 @deffn Command {etm status}
7780 Displays status of the current target's ETM and trace port driver:
7781 is the ETM idle, or is it collecting data?
7782 Did trace data overflow?
7786 @deffn Command {etm tracemode} [type context_id_bits cycle_accurate branch_output]
7787 Displays what data that ETM will collect.
7788 If arguments are provided, first configures that data.
7789 When the configuration changes, tracing is stopped
7790 and any buffered trace data is invalidated.
7793 @item @var{type} ... describing how data accesses are traced,
7794 when they pass any ViewData filtering that that was set up.
7796 @option{none} (save nothing),
7797 @option{data} (save data),
7798 @option{address} (save addresses),
7799 @option{all} (save data and addresses)
7800 @item @var{context_id_bits} ... 0, 8, 16, or 32
7801 @item @var{cycle_accurate} ... @option{enable} or @option{disable}
7802 cycle-accurate instruction tracing.
7803 Before ETMv3, enabling this causes much extra data to be recorded.
7804 @item @var{branch_output} ... @option{enable} or @option{disable}.
7805 Disable this unless you need to try reconstructing the instruction
7806 trace stream without an image of the code.
7810 @deffn Command {etm trigger_debug} (@option{enable}|@option{disable})
7811 Displays whether ETM triggering debug entry (like a breakpoint) is
7812 enabled or disabled, after optionally modifying that configuration.
7813 The default behaviour is @option{disable}.
7814 Any change takes effect after the next @command{etm start}.
7816 By using script commands to configure ETM registers, you can make the
7817 processor enter debug state automatically when certain conditions,
7818 more complex than supported by the breakpoint hardware, happen.
7821 @subsection ETM Trace Operation
7823 After setting up the ETM, you can use it to collect data.
7824 That data can be exported to files for later analysis.
7825 It can also be parsed with OpenOCD, for basic sanity checking.
7827 To configure what is being traced, you will need to write
7828 various trace registers using @command{reg ETM_*} commands.
7829 For the definitions of these registers, read ARM publication
7830 @emph{IHI 0014, ``Embedded Trace Macrocell, Architecture Specification''}.
7831 Be aware that most of the relevant registers are write-only,
7832 and that ETM resources are limited. There are only a handful
7833 of address comparators, data comparators, counters, and so on.
7835 Examples of scenarios you might arrange to trace include:
7838 @item Code flow within a function, @emph{excluding} subroutines
7839 it calls. Use address range comparators to enable tracing
7840 for instruction access within that function's body.
7841 @item Code flow within a function, @emph{including} subroutines
7842 it calls. Use the sequencer and address comparators to activate
7843 tracing on an ``entered function'' state, then deactivate it by
7844 exiting that state when the function's exit code is invoked.
7845 @item Code flow starting at the fifth invocation of a function,
7846 combining one of the above models with a counter.
7847 @item CPU data accesses to the registers for a particular device,
7848 using address range comparators and the ViewData logic.
7849 @item Such data accesses only during IRQ handling, combining the above
7850 model with sequencer triggers which on entry and exit to the IRQ handler.
7851 @item @emph{... more}
7854 At this writing, September 2009, there are no Tcl utility
7855 procedures to help set up any common tracing scenarios.
7857 @deffn Command {etm analyze}
7858 Reads trace data into memory, if it wasn't already present.
7859 Decodes and prints the data that was collected.
7862 @deffn Command {etm dump} filename
7863 Stores the captured trace data in @file{filename}.
7866 @deffn Command {etm image} filename [base_address] [type]
7867 Opens an image file.
7870 @deffn Command {etm load} filename
7871 Loads captured trace data from @file{filename}.
7874 @deffn Command {etm start}
7875 Starts trace data collection.
7878 @deffn Command {etm stop}
7879 Stops trace data collection.
7882 @anchor{traceportdrivers}
7883 @subsection Trace Port Drivers
7885 To use an ETM trace port it must be associated with a driver.
7887 @deffn {Trace Port Driver} dummy
7888 Use the @option{dummy} driver if you are configuring an ETM that's
7889 not connected to anything (on-chip ETB or off-chip trace connector).
7890 @emph{This driver lets OpenOCD talk to the ETM, but it does not expose
7891 any trace data collection.}
7892 @deffn {Config Command} {etm_dummy config} target
7893 Associates the ETM for @var{target} with a dummy driver.
7897 @deffn {Trace Port Driver} etb
7898 Use the @option{etb} driver if you are configuring an ETM
7899 to use on-chip ETB memory.
7900 @deffn {Config Command} {etb config} target etb_tap
7901 Associates the ETM for @var{target} with the ETB at @var{etb_tap}.
7902 You can see the ETB registers using the @command{reg} command.
7904 @deffn Command {etb trigger_percent} [percent]
7905 This displays, or optionally changes, ETB behavior after the
7906 ETM's configured @emph{trigger} event fires.
7907 It controls how much more trace data is saved after the (single)
7908 trace trigger becomes active.
7911 @item The default corresponds to @emph{trace around} usage,
7912 recording 50 percent data before the event and the rest
7914 @item The minimum value of @var{percent} is 2 percent,
7915 recording almost exclusively data before the trigger.
7916 Such extreme @emph{trace before} usage can help figure out
7917 what caused that event to happen.
7918 @item The maximum value of @var{percent} is 100 percent,
7919 recording data almost exclusively after the event.
7920 This extreme @emph{trace after} usage might help sort out
7921 how the event caused trouble.
7923 @c REVISIT allow "break" too -- enter debug mode.
7928 @deffn {Trace Port Driver} oocd_trace
7929 This driver isn't available unless OpenOCD was explicitly configured
7930 with the @option{--enable-oocd_trace} option. You probably don't want
7931 to configure it unless you've built the appropriate prototype hardware;
7932 it's @emph{proof-of-concept} software.
7934 Use the @option{oocd_trace} driver if you are configuring an ETM that's
7935 connected to an off-chip trace connector.
7937 @deffn {Config Command} {oocd_trace config} target tty
7938 Associates the ETM for @var{target} with a trace driver which
7939 collects data through the serial port @var{tty}.
7942 @deffn Command {oocd_trace resync}
7943 Re-synchronizes with the capture clock.
7946 @deffn Command {oocd_trace status}
7947 Reports whether the capture clock is locked or not.
7951 @anchor{armcrosstrigger}
7952 @section ARM Cross-Trigger Interface
7955 The ARM Cross-Trigger Interface (CTI) is a generic CoreSight component
7956 that connects event sources like tracing components or CPU cores with each
7957 other through a common trigger matrix (CTM). For ARMv8 architecture, a
7958 CTI is mandatory for core run control and each core has an individual
7959 CTI instance attached to it. OpenOCD has limited support for CTI using
7960 the @emph{cti} group of commands.
7962 @deffn Command {cti create} cti_name @option{-dap} dap_name @option{-ap-num} apn @option{-ctibase} base_address
7963 Creates a CTI instance @var{cti_name} on the DAP instance @var{dap_name} on MEM-AP
7964 @var{apn}. The @var{base_address} must match the base address of the CTI
7965 on the respective MEM-AP. All arguments are mandatory. This creates a
7966 new command @command{$cti_name} which is used for various purposes
7967 including additional configuration.
7970 @deffn Command {$cti_name enable} @option{on|off}
7971 Enable (@option{on}) or disable (@option{off}) the CTI.
7974 @deffn Command {$cti_name dump}
7975 Displays a register dump of the CTI.
7978 @deffn Command {$cti_name write } @var{reg_name} @var{value}
7979 Write @var{value} to the CTI register with the symbolic name @var{reg_name}.
7982 @deffn Command {$cti_name read} @var{reg_name}
7983 Print the value read from the CTI register with the symbolic name @var{reg_name}.
7986 @deffn Command {$cti_name testmode} @option{on|off}
7987 Enable (@option{on}) or disable (@option{off}) the integration test mode
7991 @deffn Command {cti names}
7992 Prints a list of names of all CTI objects created. This command is mainly
7993 useful in TCL scripting.
7996 @section Generic ARM
7999 These commands should be available on all ARM processors.
8000 They are available in addition to other core-specific
8001 commands that may be available.
8003 @deffn Command {arm core_state} [@option{arm}|@option{thumb}]
8004 Displays the core_state, optionally changing it to process
8005 either @option{arm} or @option{thumb} instructions.
8006 The target may later be resumed in the currently set core_state.
8007 (Processors may also support the Jazelle state, but
8008 that is not currently supported in OpenOCD.)
8011 @deffn Command {arm disassemble} address [count [@option{thumb}]]
8013 Disassembles @var{count} instructions starting at @var{address}.
8014 If @var{count} is not specified, a single instruction is disassembled.
8015 If @option{thumb} is specified, or the low bit of the address is set,
8016 Thumb2 (mixed 16/32-bit) instructions are used;
8017 else ARM (32-bit) instructions are used.
8018 (Processors may also support the Jazelle state, but
8019 those instructions are not currently understood by OpenOCD.)
8021 Note that all Thumb instructions are Thumb2 instructions,
8022 so older processors (without Thumb2 support) will still
8023 see correct disassembly of Thumb code.
8024 Also, ThumbEE opcodes are the same as Thumb2,
8025 with a handful of exceptions.
8026 ThumbEE disassembly currently has no explicit support.
8029 @deffn Command {arm mcr} pX op1 CRn CRm op2 value
8030 Write @var{value} to a coprocessor @var{pX} register
8031 passing parameters @var{CRn},
8032 @var{CRm}, opcodes @var{opc1} and @var{opc2},
8033 and using the MCR instruction.
8034 (Parameter sequence matches the ARM instruction, but omits
8038 @deffn Command {arm mrc} pX coproc op1 CRn CRm op2
8039 Read a coprocessor @var{pX} register passing parameters @var{CRn},
8040 @var{CRm}, opcodes @var{opc1} and @var{opc2},
8041 and the MRC instruction.
8042 Returns the result so it can be manipulated by Jim scripts.
8043 (Parameter sequence matches the ARM instruction, but omits
8047 @deffn Command {arm reg}
8048 Display a table of all banked core registers, fetching the current value from every
8049 core mode if necessary.
8052 @deffn Command {arm semihosting} [@option{enable}|@option{disable}]
8053 @cindex ARM semihosting
8054 Display status of semihosting, after optionally changing that status.
8056 Semihosting allows for code executing on an ARM target to use the
8057 I/O facilities on the host computer i.e. the system where OpenOCD
8058 is running. The target application must be linked against a library
8059 implementing the ARM semihosting convention that forwards operation
8060 requests by using a special SVC instruction that is trapped at the
8061 Supervisor Call vector by OpenOCD.
8064 @deffn Command {arm semihosting_cmdline} [@option{enable}|@option{disable}]
8065 @cindex ARM semihosting
8066 Set the command line to be passed to the debuggee.
8069 arm semihosting_cmdline argv0 argv1 argv2 ...
8072 This option lets one set the command line arguments to be passed to
8073 the program. The first argument (argv0) is the program name in a
8074 standard C environment (argv[0]). Depending on the program (not much
8075 programs look at argv[0]), argv0 is ignored and can be any string.
8078 @deffn Command {arm semihosting_fileio} [@option{enable}|@option{disable}]
8079 @cindex ARM semihosting
8080 Display status of semihosting fileio, after optionally changing that
8083 Enabling this option forwards semihosting I/O to GDB process using the
8084 File-I/O remote protocol extension. This is especially useful for
8085 interacting with remote files or displaying console messages in the
8089 @section ARMv4 and ARMv5 Architecture
8093 The ARMv4 and ARMv5 architectures are widely used in embedded systems,
8094 and introduced core parts of the instruction set in use today.
8095 That includes the Thumb instruction set, introduced in the ARMv4T
8098 @subsection ARM7 and ARM9 specific commands
8102 These commands are specific to ARM7 and ARM9 cores, like ARM7TDMI, ARM720T,
8103 ARM9TDMI, ARM920T or ARM926EJ-S.
8104 They are available in addition to the ARM commands,
8105 and any other core-specific commands that may be available.
8107 @deffn Command {arm7_9 dbgrq} [@option{enable}|@option{disable}]
8108 Displays the value of the flag controlling use of the
8109 the EmbeddedIce DBGRQ signal to force entry into debug mode,
8110 instead of breakpoints.
8111 If a boolean parameter is provided, first assigns that flag.
8114 safe for all but ARM7TDMI-S cores (like NXP LPC).
8115 This feature is enabled by default on most ARM9 cores,
8116 including ARM9TDMI, ARM920T, and ARM926EJ-S.
8119 @deffn Command {arm7_9 dcc_downloads} [@option{enable}|@option{disable}]
8121 Displays the value of the flag controlling use of the debug communications
8122 channel (DCC) to write larger (>128 byte) amounts of memory.
8123 If a boolean parameter is provided, first assigns that flag.
8125 DCC downloads offer a huge speed increase, but might be
8126 unsafe, especially with targets running at very low speeds. This command was introduced
8127 with OpenOCD rev. 60, and requires a few bytes of working area.
8130 @deffn Command {arm7_9 fast_memory_access} [@option{enable}|@option{disable}]
8131 Displays the value of the flag controlling use of memory writes and reads
8132 that don't check completion of the operation.
8133 If a boolean parameter is provided, first assigns that flag.
8135 This provides a huge speed increase, especially with USB JTAG
8136 cables (FT2232), but might be unsafe if used with targets running at very low
8137 speeds, like the 32kHz startup clock of an AT91RM9200.
8140 @subsection ARM720T specific commands
8143 These commands are available to ARM720T based CPUs,
8144 which are implementations of the ARMv4T architecture
8145 based on the ARM7TDMI-S integer core.
8146 They are available in addition to the ARM and ARM7/ARM9 commands.
8148 @deffn Command {arm720t cp15} opcode [value]
8149 @emph{DEPRECATED -- avoid using this.
8150 Use the @command{arm mrc} or @command{arm mcr} commands instead.}
8152 Display cp15 register returned by the ARM instruction @var{opcode};
8153 else if a @var{value} is provided, that value is written to that register.
8154 The @var{opcode} should be the value of either an MRC or MCR instruction.
8157 @subsection ARM9 specific commands
8160 ARM9-family cores are built around ARM9TDMI or ARM9E (including ARM9EJS)
8162 Such cores include the ARM920T, ARM926EJ-S, and ARM966.
8164 @c 9-june-2009: tried this on arm920t, it didn't work.
8165 @c no-params always lists nothing caught, and that's how it acts.
8166 @c 23-oct-2009: doesn't work _consistently_ ... as if the ICE
8167 @c versions have different rules about when they commit writes.
8169 @anchor{arm9vectorcatch}
8170 @deffn Command {arm9 vector_catch} [@option{all}|@option{none}|list]
8171 @cindex vector_catch
8172 Vector Catch hardware provides a sort of dedicated breakpoint
8173 for hardware events such as reset, interrupt, and abort.
8174 You can use this to conserve normal breakpoint resources,
8175 so long as you're not concerned with code that branches directly
8176 to those hardware vectors.
8178 This always finishes by listing the current configuration.
8179 If parameters are provided, it first reconfigures the
8180 vector catch hardware to intercept
8181 @option{all} of the hardware vectors,
8182 @option{none} of them,
8183 or a list with one or more of the following:
8184 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt}
8185 @option{irq} @option{fiq}.
8188 @subsection ARM920T specific commands
8191 These commands are available to ARM920T based CPUs,
8192 which are implementations of the ARMv4T architecture
8193 built using the ARM9TDMI integer core.
8194 They are available in addition to the ARM, ARM7/ARM9,
8197 @deffn Command {arm920t cache_info}
8198 Print information about the caches found. This allows to see whether your target
8199 is an ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
8202 @deffn Command {arm920t cp15} regnum [value]
8203 Display cp15 register @var{regnum};
8204 else if a @var{value} is provided, that value is written to that register.
8205 This uses "physical access" and the register number is as
8206 shown in bits 38..33 of table 9-9 in the ARM920T TRM.
8207 (Not all registers can be written.)
8210 @deffn Command {arm920t cp15i} opcode [value [address]]
8211 @emph{DEPRECATED -- avoid using this.
8212 Use the @command{arm mrc} or @command{arm mcr} commands instead.}
8214 Interpreted access using ARM instruction @var{opcode}, which should
8215 be the value of either an MRC or MCR instruction
8216 (as shown tables 9-11, 9-12, and 9-13 in the ARM920T TRM).
8217 If no @var{value} is provided, the result is displayed.
8218 Else if that value is written using the specified @var{address},
8219 or using zero if no other address is provided.
8222 @deffn Command {arm920t read_cache} filename
8223 Dump the content of ICache and DCache to a file named @file{filename}.
8226 @deffn Command {arm920t read_mmu} filename
8227 Dump the content of the ITLB and DTLB to a file named @file{filename}.
8230 @subsection ARM926ej-s specific commands
8233 These commands are available to ARM926ej-s based CPUs,
8234 which are implementations of the ARMv5TEJ architecture
8235 based on the ARM9EJ-S integer core.
8236 They are available in addition to the ARM, ARM7/ARM9,
8239 The Feroceon cores also support these commands, although
8240 they are not built from ARM926ej-s designs.
8242 @deffn Command {arm926ejs cache_info}
8243 Print information about the caches found.
8246 @subsection ARM966E specific commands
8249 These commands are available to ARM966 based CPUs,
8250 which are implementations of the ARMv5TE architecture.
8251 They are available in addition to the ARM, ARM7/ARM9,
8254 @deffn Command {arm966e cp15} regnum [value]
8255 Display cp15 register @var{regnum};
8256 else if a @var{value} is provided, that value is written to that register.
8257 The six bit @var{regnum} values are bits 37..32 from table 7-2 of the
8259 There is no current control over bits 31..30 from that table,
8260 as required for BIST support.
8263 @subsection XScale specific commands
8266 Some notes about the debug implementation on the XScale CPUs:
8268 The XScale CPU provides a special debug-only mini-instruction cache
8269 (mini-IC) in which exception vectors and target-resident debug handler
8270 code are placed by OpenOCD. In order to get access to the CPU, OpenOCD
8271 must point vector 0 (the reset vector) to the entry of the debug
8272 handler. However, this means that the complete first cacheline in the
8273 mini-IC is marked valid, which makes the CPU fetch all exception
8274 handlers from the mini-IC, ignoring the code in RAM.
8276 To address this situation, OpenOCD provides the @code{xscale
8277 vector_table} command, which allows the user to explicity write
8278 individual entries to either the high or low vector table stored in
8281 It is recommended to place a pc-relative indirect branch in the vector
8282 table, and put the branch destination somewhere in memory. Doing so
8283 makes sure the code in the vector table stays constant regardless of
8284 code layout in memory:
8287 ldr pc,[pc,#0x100-8]
8288 ldr pc,[pc,#0x100-8]
8289 ldr pc,[pc,#0x100-8]
8290 ldr pc,[pc,#0x100-8]
8291 ldr pc,[pc,#0x100-8]
8292 ldr pc,[pc,#0x100-8]
8293 ldr pc,[pc,#0x100-8]
8294 ldr pc,[pc,#0x100-8]
8296 .long real_reset_vector
8297 .long real_ui_handler
8298 .long real_swi_handler
8300 .long real_data_abort
8301 .long 0 /* unused */
8302 .long real_irq_handler
8303 .long real_fiq_handler
8306 Alternatively, you may choose to keep some or all of the mini-IC
8307 vector table entries synced with those written to memory by your
8308 system software. The mini-IC can not be modified while the processor
8309 is executing, but for each vector table entry not previously defined
8310 using the @code{xscale vector_table} command, OpenOCD will copy the
8311 value from memory to the mini-IC every time execution resumes from a
8312 halt. This is done for both high and low vector tables (although the
8313 table not in use may not be mapped to valid memory, and in this case
8314 that copy operation will silently fail). This means that you will
8315 need to briefly halt execution at some strategic point during system
8316 start-up; e.g., after the software has initialized the vector table,
8317 but before exceptions are enabled. A breakpoint can be used to
8318 accomplish this once the appropriate location in the start-up code has
8319 been identified. A watchpoint over the vector table region is helpful
8320 in finding the location if you're not sure. Note that the same
8321 situation exists any time the vector table is modified by the system
8324 The debug handler must be placed somewhere in the address space using
8325 the @code{xscale debug_handler} command. The allowed locations for the
8326 debug handler are either (0x800 - 0x1fef800) or (0xfe000800 -
8327 0xfffff800). The default value is 0xfe000800.
8329 XScale has resources to support two hardware breakpoints and two
8330 watchpoints. However, the following restrictions on watchpoint
8331 functionality apply: (1) the value and mask arguments to the @code{wp}
8332 command are not supported, (2) the watchpoint length must be a
8333 power of two and not less than four, and can not be greater than the
8334 watchpoint address, and (3) a watchpoint with a length greater than
8335 four consumes all the watchpoint hardware resources. This means that
8336 at any one time, you can have enabled either two watchpoints with a
8337 length of four, or one watchpoint with a length greater than four.
8339 These commands are available to XScale based CPUs,
8340 which are implementations of the ARMv5TE architecture.
8342 @deffn Command {xscale analyze_trace}
8343 Displays the contents of the trace buffer.
8346 @deffn Command {xscale cache_clean_address} address
8347 Changes the address used when cleaning the data cache.
8350 @deffn Command {xscale cache_info}
8351 Displays information about the CPU caches.
8354 @deffn Command {xscale cp15} regnum [value]
8355 Display cp15 register @var{regnum};
8356 else if a @var{value} is provided, that value is written to that register.
8359 @deffn Command {xscale debug_handler} target address
8360 Changes the address used for the specified target's debug handler.
8363 @deffn Command {xscale dcache} [@option{enable}|@option{disable}]
8364 Enables or disable the CPU's data cache.
8367 @deffn Command {xscale dump_trace} filename
8368 Dumps the raw contents of the trace buffer to @file{filename}.
8371 @deffn Command {xscale icache} [@option{enable}|@option{disable}]
8372 Enables or disable the CPU's instruction cache.
8375 @deffn Command {xscale mmu} [@option{enable}|@option{disable}]
8376 Enables or disable the CPU's memory management unit.
8379 @deffn Command {xscale trace_buffer} [@option{enable}|@option{disable} [@option{fill} [n] | @option{wrap}]]
8380 Displays the trace buffer status, after optionally
8381 enabling or disabling the trace buffer
8382 and modifying how it is emptied.
8385 @deffn Command {xscale trace_image} filename [offset [type]]
8386 Opens a trace image from @file{filename}, optionally rebasing
8387 its segment addresses by @var{offset}.
8388 The image @var{type} may be one of
8389 @option{bin} (binary), @option{ihex} (Intel hex),
8390 @option{elf} (ELF file), @option{s19} (Motorola s19),
8391 @option{mem}, or @option{builder}.
8394 @anchor{xscalevectorcatch}
8395 @deffn Command {xscale vector_catch} [mask]
8396 @cindex vector_catch
8397 Display a bitmask showing the hardware vectors to catch.
8398 If the optional parameter is provided, first set the bitmask to that value.
8400 The mask bits correspond with bit 16..23 in the DCSR:
8403 0x02 Trap Undefined Instructions
8404 0x04 Trap Software Interrupt
8405 0x08 Trap Prefetch Abort
8406 0x10 Trap Data Abort
8413 @deffn Command {xscale vector_table} [(@option{low}|@option{high}) index value]
8414 @cindex vector_table
8416 Set an entry in the mini-IC vector table. There are two tables: one for
8417 low vectors (at 0x00000000), and one for high vectors (0xFFFF0000), each
8418 holding the 8 exception vectors. @var{index} can be 1-7, because vector 0
8419 points to the debug handler entry and can not be overwritten.
8420 @var{value} holds the 32-bit opcode that is placed in the mini-IC.
8422 Without arguments, the current settings are displayed.
8426 @section ARMv6 Architecture
8429 @subsection ARM11 specific commands
8432 @deffn Command {arm11 memwrite burst} [@option{enable}|@option{disable}]
8433 Displays the value of the memwrite burst-enable flag,
8434 which is enabled by default.
8435 If a boolean parameter is provided, first assigns that flag.
8436 Burst writes are only used for memory writes larger than 1 word.
8437 They improve performance by assuming that the CPU has read each data
8438 word over JTAG and completed its write before the next word arrives,
8439 instead of polling for a status flag to verify that completion.
8440 This is usually safe, because JTAG runs much slower than the CPU.
8443 @deffn Command {arm11 memwrite error_fatal} [@option{enable}|@option{disable}]
8444 Displays the value of the memwrite error_fatal flag,
8445 which is enabled by default.
8446 If a boolean parameter is provided, first assigns that flag.
8447 When set, certain memory write errors cause earlier transfer termination.
8450 @deffn Command {arm11 step_irq_enable} [@option{enable}|@option{disable}]
8451 Displays the value of the flag controlling whether
8452 IRQs are enabled during single stepping;
8453 they are disabled by default.
8454 If a boolean parameter is provided, first assigns that.
8457 @deffn Command {arm11 vcr} [value]
8458 @cindex vector_catch
8459 Displays the value of the @emph{Vector Catch Register (VCR)},
8460 coprocessor 14 register 7.
8461 If @var{value} is defined, first assigns that.
8463 Vector Catch hardware provides dedicated breakpoints
8464 for certain hardware events.
8465 The specific bit values are core-specific (as in fact is using
8466 coprocessor 14 register 7 itself) but all current ARM11
8467 cores @emph{except the ARM1176} use the same six bits.
8470 @section ARMv7 and ARMv8 Architecture
8474 @subsection ARMv7-A specific commands
8477 @deffn Command {cortex_a cache_info}
8478 display information about target caches
8481 @deffn Command {cortex_a dacrfixup [@option{on}|@option{off}]}
8482 Work around issues with software breakpoints when the program text is
8483 mapped read-only by the operating system. This option sets the CP15 DACR
8484 to "all-manager" to bypass MMU permission checks on memory access.
8488 @deffn Command {cortex_a dbginit}
8489 Initialize core debug
8490 Enables debug by unlocking the Software Lock and clearing sticky powerdown indications
8493 @deffn Command {cortex_a smp_off}
8497 @deffn Command {cortex_a smp_on}
8501 @deffn Command {cortex_a smp_gdb} [core_id]
8502 Display/set the current core displayed in GDB
8505 @deffn Command {cortex_a maskisr} [@option{on}|@option{off}]
8506 Selects whether interrupts will be processed when single stepping
8509 @deffn Command {cache_config l2x} [base way]
8514 @subsection ARMv7-R specific commands
8517 @deffn Command {cortex_r dbginit}
8518 Initialize core debug
8519 Enables debug by unlocking the Software Lock and clearing sticky powerdown indications
8522 @deffn Command {cortex_r maskisr} [@option{on}|@option{off}]
8523 Selects whether interrupts will be processed when single stepping
8527 @subsection ARMv7-M specific commands
8535 @deffn Command {tpiu config} (@option{disable} | ((@option{external} | @option{internal (@var{filename} | -)}) @
8536 (@option{sync @var{port_width}} | ((@option{manchester} | @option{uart}) @var{formatter_enable})) @
8537 @var{TRACECLKIN_freq} [@var{trace_freq}]))
8539 ARMv7-M architecture provides several modules to generate debugging
8540 information internally (ITM, DWT and ETM). Their output is directed
8541 through TPIU to be captured externally either on an SWO pin (this
8542 configuration is called SWV) or on a synchronous parallel trace port.
8544 This command configures the TPIU module of the target and, if internal
8545 capture mode is selected, starts to capture trace output by using the
8546 debugger adapter features.
8548 Some targets require additional actions to be performed in the
8549 @b{trace-config} handler for trace port to be activated.
8553 @item @option{disable} disable TPIU handling;
8554 @item @option{external} configure TPIU to let user capture trace
8555 output externally (with an additional UART or logic analyzer hardware);
8556 @item @option{internal @var{filename}} configure TPIU and debug adapter to
8557 gather trace data and append it to @var{filename} (which can be
8558 either a regular file or a named pipe);
8559 @item @option{internal -} configure TPIU and debug adapter to
8560 gather trace data, but not write to any file. Useful in conjunction with the @command{tcl_trace} command;
8561 @item @option{sync @var{port_width}} use synchronous parallel trace output
8562 mode, and set port width to @var{port_width};
8563 @item @option{manchester} use asynchronous SWO mode with Manchester
8565 @item @option{uart} use asynchronous SWO mode with NRZ (same as
8566 regular UART 8N1) coding;
8567 @item @var{formatter_enable} is @option{on} or @option{off} to enable
8568 or disable TPIU formatter which needs to be used when both ITM and ETM
8569 data is to be output via SWO;
8570 @item @var{TRACECLKIN_freq} this should be specified to match target's
8571 current TRACECLKIN frequency (usually the same as HCLK);
8572 @item @var{trace_freq} trace port frequency. Can be omitted in
8573 internal mode to let the adapter driver select the maximum supported
8579 @item STM32L152 board is programmed with an application that configures
8580 PLL to provide core clock with 24MHz frequency; to use ITM output it's
8583 #include <libopencm3/cm3/itm.h>
8588 (the most obvious way is to use the first stimulus port for printf,
8589 for that this ITM_STIM8 assignment can be used inside _write(); to make it
8590 blocking to avoid data loss, add @code{while (!(ITM_STIM8(0) &
8591 ITM_STIM_FIFOREADY));});
8592 @item An FT2232H UART is connected to the SWO pin of the board;
8593 @item Commands to configure UART for 12MHz baud rate:
8595 $ setserial /dev/ttyUSB1 spd_cust divisor 5
8596 $ stty -F /dev/ttyUSB1 38400
8598 (FT2232H's base frequency is 60MHz, spd_cust allows to alias 38400
8599 baud with our custom divisor to get 12MHz)
8600 @item @code{itmdump -f /dev/ttyUSB1 -d1}
8601 @item OpenOCD invocation line:
8603 openocd -f interface/stlink-v2-1.cfg \
8604 -c "transport select hla_swd" \
8605 -f target/stm32l1.cfg \
8606 -c "tpiu config external uart off 24000000 12000000"
8611 @deffn Command {itm port} @var{port} (@option{0}|@option{1}|@option{on}|@option{off})
8612 Enable or disable trace output for ITM stimulus @var{port} (counting
8613 from 0). Port 0 is enabled on target creation automatically.
8616 @deffn Command {itm ports} (@option{0}|@option{1}|@option{on}|@option{off})
8617 Enable or disable trace output for all ITM stimulus ports.
8620 @subsection Cortex-M specific commands
8623 @deffn Command {cortex_m maskisr} (@option{auto}|@option{on}|@option{off})
8624 Control masking (disabling) interrupts during target step/resume.
8626 The @option{auto} option handles interrupts during stepping a way they get
8627 served but don't disturb the program flow. The step command first allows
8628 pending interrupt handlers to execute, then disables interrupts and steps over
8629 the next instruction where the core was halted. After the step interrupts
8630 are enabled again. If the interrupt handlers don't complete within 500ms,
8631 the step command leaves with the core running.
8633 Note that a free breakpoint is required for the @option{auto} option. If no
8634 breakpoint is available at the time of the step, then the step is taken
8635 with interrupts enabled, i.e. the same way the @option{off} option does.
8637 Default is @option{auto}.
8640 @deffn Command {cortex_m vector_catch} [@option{all}|@option{none}|list]
8641 @cindex vector_catch
8642 Vector Catch hardware provides dedicated breakpoints
8643 for certain hardware events.
8645 Parameters request interception of
8646 @option{all} of these hardware event vectors,
8647 @option{none} of them,
8648 or one or more of the following:
8649 @option{hard_err} for a HardFault exception;
8650 @option{mm_err} for a MemManage exception;
8651 @option{bus_err} for a BusFault exception;
8654 @option{chk_err}, or
8655 @option{nocp_err} for various UsageFault exceptions; or
8657 If NVIC setup code does not enable them,
8658 MemManage, BusFault, and UsageFault exceptions
8659 are mapped to HardFault.
8660 UsageFault checks for
8661 divide-by-zero and unaligned access
8662 must also be explicitly enabled.
8664 This finishes by listing the current vector catch configuration.
8667 @deffn Command {cortex_m reset_config} (@option{srst}|@option{sysresetreq}|@option{vectreset})
8668 Control reset handling. The default @option{srst} is to use srst if fitted,
8669 otherwise fallback to @option{vectreset}.
8671 @item @option{srst} use hardware srst if fitted otherwise fallback to @option{vectreset}.
8672 @item @option{sysresetreq} use NVIC SYSRESETREQ to reset system.
8673 @item @option{vectreset} use NVIC VECTRESET to reset system.
8675 Using @option{vectreset} is a safe option for all current Cortex-M cores.
8676 This however has the disadvantage of only resetting the core, all peripherals
8677 are uneffected. A solution would be to use a @code{reset-init} event handler to manually reset
8679 @xref{targetevents,,Target Events}.
8682 @subsection ARMv8-A specific commands
8686 @deffn Command {aarch64 cache_info}
8687 Display information about target caches
8690 @deffn Command {aarch64 dbginit}
8691 This command enables debugging by clearing the OS Lock and sticky power-down and reset
8692 indications. It also establishes the expected, basic cross-trigger configuration the aarch64
8693 target code relies on. In a configuration file, the command would typically be called from a
8694 @code{reset-end} or @code{reset-deassert-post} handler, to re-enable debugging after a system reset.
8695 However, normally it is not necessary to use the command at all.
8698 @deffn Command {aarch64 smp_on|smp_off}
8699 Enable and disable SMP handling. The state of SMP handling influences the way targets in an SMP group
8700 are handled by the run control. With SMP handling enabled, issuing halt or resume to one core will trigger
8701 halting or resuming of all cores in the group. The command @code{target smp} defines which targets are in the SMP
8702 group. With SMP handling disabled, all targets need to be treated individually.
8705 @deffn Command {aarch64 maskisr} [@option{on}|@option{off}]
8706 Selects whether interrupts will be processed when single stepping. The default configuration is
8710 @section Intel Architecture
8712 Intel Quark X10xx is the first product in the Quark family of SoCs. It is an IA-32
8713 (Pentium x86 ISA) compatible SoC. The core CPU in the X10xx is codenamed Lakemont.
8714 Lakemont version 1 (LMT1) is used in X10xx. The CPU TAP (Lakemont TAP) is used for
8715 software debug and the CLTAP is used for SoC level operations.
8716 Useful docs are here: https://communities.intel.com/community/makers/documentation
8718 @item Intel Quark SoC X1000 OpenOCD/GDB/Eclipse App Note (web search for doc num 330015)
8719 @item Intel Quark SoC X1000 Debug Operations User Guide (web search for doc num 329866)
8720 @item Intel Quark SoC X1000 Datasheet (web search for doc num 329676)
8723 @subsection x86 32-bit specific commands
8724 The three main address spaces for x86 are memory, I/O and configuration space.
8725 These commands allow a user to read and write to the 64Kbyte I/O address space.
8727 @deffn Command {x86_32 idw} address
8728 Display the contents of a 32-bit I/O port from address range 0x0000 - 0xffff.
8731 @deffn Command {x86_32 idh} address
8732 Display the contents of a 16-bit I/O port from address range 0x0000 - 0xffff.
8735 @deffn Command {x86_32 idb} address
8736 Display the contents of a 8-bit I/O port from address range 0x0000 - 0xffff.
8739 @deffn Command {x86_32 iww} address
8740 Write the contents of a 32-bit I/O port to address range 0x0000 - 0xffff.
8743 @deffn Command {x86_32 iwh} address
8744 Write the contents of a 16-bit I/O port to address range 0x0000 - 0xffff.
8747 @deffn Command {x86_32 iwb} address
8748 Write the contents of a 8-bit I/O port to address range 0x0000 - 0xffff.
8751 @section OpenRISC Architecture
8753 The OpenRISC CPU is a soft core. It is used in a programmable SoC which can be
8754 configured with any of the TAP / Debug Unit available.
8756 @subsection TAP and Debug Unit selection commands
8757 @deffn Command {tap_select} (@option{vjtag}|@option{mohor}|@option{xilinx_bscan})
8758 Select between the Altera Virtual JTAG , Xilinx Virtual JTAG and Mohor TAP.
8760 @deffn Command {du_select} (@option{adv}|@option{mohor}) [option]
8761 Select between the Advanced Debug Interface and the classic one.
8763 An option can be passed as a second argument to the debug unit.
8765 When using the Advanced Debug Interface, option = 1 means the RTL core is
8766 configured with ADBG_USE_HISPEED = 1. This configuration skips status checking
8767 between bytes while doing read or write bursts.
8770 @subsection Registers commands
8771 @deffn Command {addreg} [name] [address] [feature] [reg_group]
8772 Add a new register in the cpu register list. This register will be
8773 included in the generated target descriptor file.
8775 @strong{[feature]} must be "org.gnu.gdb.or1k.group[0..10]".
8777 @strong{[reg_group]} can be anything. The default register list defines "system",
8778 "dmmu", "immu", "dcache", "icache", "mac", "debug", "perf", "power", "pic"
8783 addreg rtest 0x1234 org.gnu.gdb.or1k.group0 system
8788 @deffn Command {readgroup} (@option{group})
8789 Display all registers in @emph{group}.
8791 @emph{group} can be "system",
8792 "dmmu", "immu", "dcache", "icache", "mac", "debug", "perf", "power", "pic",
8793 "timer" or any new group created with addreg command.
8796 @anchor{softwaredebugmessagesandtracing}
8797 @section Software Debug Messages and Tracing
8798 @cindex Linux-ARM DCC support
8802 OpenOCD can process certain requests from target software, when
8803 the target uses appropriate libraries.
8804 The most powerful mechanism is semihosting, but there is also
8805 a lighter weight mechanism using only the DCC channel.
8807 Currently @command{target_request debugmsgs}
8808 is supported only for @option{arm7_9} and @option{cortex_m} cores.
8809 These messages are received as part of target polling, so
8810 you need to have @command{poll on} active to receive them.
8811 They are intrusive in that they will affect program execution
8812 times. If that is a problem, @pxref{armhardwaretracing,,ARM Hardware Tracing}.
8814 See @file{libdcc} in the contrib dir for more details.
8815 In addition to sending strings, characters, and
8816 arrays of various size integers from the target,
8817 @file{libdcc} also exports a software trace point mechanism.
8818 The target being debugged may
8819 issue trace messages which include a 24-bit @dfn{trace point} number.
8820 Trace point support includes two distinct mechanisms,
8821 each supported by a command:
8824 @item @emph{History} ... A circular buffer of trace points
8825 can be set up, and then displayed at any time.
8826 This tracks where code has been, which can be invaluable in
8827 finding out how some fault was triggered.
8829 The buffer may overflow, since it collects records continuously.
8830 It may be useful to use some of the 24 bits to represent a
8831 particular event, and other bits to hold data.
8833 @item @emph{Counting} ... An array of counters can be set up,
8834 and then displayed at any time.
8835 This can help establish code coverage and identify hot spots.
8837 The array of counters is directly indexed by the trace point
8838 number, so trace points with higher numbers are not counted.
8841 Linux-ARM kernels have a ``Kernel low-level debugging
8842 via EmbeddedICE DCC channel'' option (CONFIG_DEBUG_ICEDCC,
8843 depends on CONFIG_DEBUG_LL) which uses this mechanism to
8844 deliver messages before a serial console can be activated.
8845 This is not the same format used by @file{libdcc}.
8846 Other software, such as the U-Boot boot loader, sometimes
8847 does the same thing.
8849 @deffn Command {target_request debugmsgs} [@option{enable}|@option{disable}|@option{charmsg}]
8850 Displays current handling of target DCC message requests.
8851 These messages may be sent to the debugger while the target is running.
8852 The optional @option{enable} and @option{charmsg} parameters
8853 both enable the messages, while @option{disable} disables them.
8855 With @option{charmsg} the DCC words each contain one character,
8856 as used by Linux with CONFIG_DEBUG_ICEDCC;
8857 otherwise the libdcc format is used.
8860 @deffn Command {trace history} [@option{clear}|count]
8861 With no parameter, displays all the trace points that have triggered
8862 in the order they triggered.
8863 With the parameter @option{clear}, erases all current trace history records.
8864 With a @var{count} parameter, allocates space for that many
8868 @deffn Command {trace point} [@option{clear}|identifier]
8869 With no parameter, displays all trace point identifiers and how many times
8870 they have been triggered.
8871 With the parameter @option{clear}, erases all current trace point counters.
8872 With a numeric @var{identifier} parameter, creates a new a trace point counter
8873 and associates it with that identifier.
8875 @emph{Important:} The identifier and the trace point number
8876 are not related except by this command.
8877 These trace point numbers always start at zero (from server startup,
8878 or after @command{trace point clear}) and count up from there.
8883 @chapter JTAG Commands
8884 @cindex JTAG Commands
8885 Most general purpose JTAG commands have been presented earlier.
8886 (@xref{jtagspeed,,JTAG Speed}, @ref{Reset Configuration}, and @ref{TAP Declaration}.)
8887 Lower level JTAG commands, as presented here,
8888 may be needed to work with targets which require special
8889 attention during operations such as reset or initialization.
8891 To use these commands you will need to understand some
8892 of the basics of JTAG, including:
8895 @item A JTAG scan chain consists of a sequence of individual TAP
8896 devices such as a CPUs.
8897 @item Control operations involve moving each TAP through the same
8898 standard state machine (in parallel)
8899 using their shared TMS and clock signals.
8900 @item Data transfer involves shifting data through the chain of
8901 instruction or data registers of each TAP, writing new register values
8902 while the reading previous ones.
8903 @item Data register sizes are a function of the instruction active in
8904 a given TAP, while instruction register sizes are fixed for each TAP.
8905 All TAPs support a BYPASS instruction with a single bit data register.
8906 @item The way OpenOCD differentiates between TAP devices is by
8907 shifting different instructions into (and out of) their instruction
8911 @section Low Level JTAG Commands
8913 These commands are used by developers who need to access
8914 JTAG instruction or data registers, possibly controlling
8915 the order of TAP state transitions.
8916 If you're not debugging OpenOCD internals, or bringing up a
8917 new JTAG adapter or a new type of TAP device (like a CPU or
8918 JTAG router), you probably won't need to use these commands.
8919 In a debug session that doesn't use JTAG for its transport protocol,
8920 these commands are not available.
8922 @deffn Command {drscan} tap [numbits value]+ [@option{-endstate} tap_state]
8923 Loads the data register of @var{tap} with a series of bit fields
8924 that specify the entire register.
8925 Each field is @var{numbits} bits long with
8926 a numeric @var{value} (hexadecimal encouraged).
8927 The return value holds the original value of each
8930 For example, a 38 bit number might be specified as one
8931 field of 32 bits then one of 6 bits.
8932 @emph{For portability, never pass fields which are more
8933 than 32 bits long. Many OpenOCD implementations do not
8934 support 64-bit (or larger) integer values.}
8936 All TAPs other than @var{tap} must be in BYPASS mode.
8937 The single bit in their data registers does not matter.
8939 When @var{tap_state} is specified, the JTAG state machine is left
8941 For example @sc{drpause} might be specified, so that more
8942 instructions can be issued before re-entering the @sc{run/idle} state.
8943 If the end state is not specified, the @sc{run/idle} state is entered.
8946 OpenOCD does not record information about data register lengths,
8947 so @emph{it is important that you get the bit field lengths right}.
8948 Remember that different JTAG instructions refer to different
8949 data registers, which may have different lengths.
8950 Moreover, those lengths may not be fixed;
8951 the SCAN_N instruction can change the length of
8952 the register accessed by the INTEST instruction
8953 (by connecting a different scan chain).
8957 @deffn Command {flush_count}
8958 Returns the number of times the JTAG queue has been flushed.
8959 This may be used for performance tuning.
8961 For example, flushing a queue over USB involves a
8962 minimum latency, often several milliseconds, which does
8963 not change with the amount of data which is written.
8964 You may be able to identify performance problems by finding
8965 tasks which waste bandwidth by flushing small transfers too often,
8966 instead of batching them into larger operations.
8969 @deffn Command {irscan} [tap instruction]+ [@option{-endstate} tap_state]
8970 For each @var{tap} listed, loads the instruction register
8971 with its associated numeric @var{instruction}.
8972 (The number of bits in that instruction may be displayed
8973 using the @command{scan_chain} command.)
8974 For other TAPs, a BYPASS instruction is loaded.
8976 When @var{tap_state} is specified, the JTAG state machine is left
8978 For example @sc{irpause} might be specified, so the data register
8979 can be loaded before re-entering the @sc{run/idle} state.
8980 If the end state is not specified, the @sc{run/idle} state is entered.
8983 OpenOCD currently supports only a single field for instruction
8984 register values, unlike data register values.
8985 For TAPs where the instruction register length is more than 32 bits,
8986 portable scripts currently must issue only BYPASS instructions.
8990 @deffn Command {jtag_reset} trst srst
8991 Set values of reset signals.
8992 The @var{trst} and @var{srst} parameter values may be
8993 @option{0}, indicating that reset is inactive (pulled or driven high),
8994 or @option{1}, indicating it is active (pulled or driven low).
8995 The @command{reset_config} command should already have been used
8996 to configure how the board and JTAG adapter treat these two
8997 signals, and to say if either signal is even present.
8998 @xref{Reset Configuration}.
9000 Note that TRST is specially handled.
9001 It actually signifies JTAG's @sc{reset} state.
9002 So if the board doesn't support the optional TRST signal,
9003 or it doesn't support it along with the specified SRST value,
9004 JTAG reset is triggered with TMS and TCK signals
9005 instead of the TRST signal.
9006 And no matter how that JTAG reset is triggered, once
9007 the scan chain enters @sc{reset} with TRST inactive,
9008 TAP @code{post-reset} events are delivered to all TAPs
9009 with handlers for that event.
9012 @deffn Command {pathmove} start_state [next_state ...]
9013 Start by moving to @var{start_state}, which
9014 must be one of the @emph{stable} states.
9015 Unless it is the only state given, this will often be the
9016 current state, so that no TCK transitions are needed.
9017 Then, in a series of single state transitions
9018 (conforming to the JTAG state machine) shift to
9019 each @var{next_state} in sequence, one per TCK cycle.
9020 The final state must also be stable.
9023 @deffn Command {runtest} @var{num_cycles}
9024 Move to the @sc{run/idle} state, and execute at least
9025 @var{num_cycles} of the JTAG clock (TCK).
9026 Instructions often need some time
9027 to execute before they take effect.
9030 @c tms_sequence (short|long)
9031 @c ... temporary, debug-only, other than USBprog bug workaround...
9033 @deffn Command {verify_ircapture} (@option{enable}|@option{disable})
9034 Verify values captured during @sc{ircapture} and returned
9035 during IR scans. Default is enabled, but this can be
9036 overridden by @command{verify_jtag}.
9037 This flag is ignored when validating JTAG chain configuration.
9040 @deffn Command {verify_jtag} (@option{enable}|@option{disable})
9041 Enables verification of DR and IR scans, to help detect
9042 programming errors. For IR scans, @command{verify_ircapture}
9043 must also be enabled.
9047 @section TAP state names
9048 @cindex TAP state names
9050 The @var{tap_state} names used by OpenOCD in the @command{drscan},
9051 @command{irscan}, and @command{pathmove} commands are the same
9052 as those used in SVF boundary scan documents, except that
9053 SVF uses @sc{idle} instead of @sc{run/idle}.
9056 @item @b{RESET} ... @emph{stable} (with TMS high);
9057 acts as if TRST were pulsed
9058 @item @b{RUN/IDLE} ... @emph{stable}; don't assume this always means IDLE
9061 @item @b{DRSHIFT} ... @emph{stable}; TDI/TDO shifting
9062 through the data register
9064 @item @b{DRPAUSE} ... @emph{stable}; data register ready
9065 for update or more shifting
9070 @item @b{IRSHIFT} ... @emph{stable}; TDI/TDO shifting
9071 through the instruction register
9073 @item @b{IRPAUSE} ... @emph{stable}; instruction register ready
9074 for update or more shifting
9079 Note that only six of those states are fully ``stable'' in the
9080 face of TMS fixed (low except for @sc{reset})
9081 and a free-running JTAG clock. For all the
9082 others, the next TCK transition changes to a new state.
9085 @item From @sc{drshift} and @sc{irshift}, clock transitions will
9086 produce side effects by changing register contents. The values
9087 to be latched in upcoming @sc{drupdate} or @sc{irupdate} states
9088 may not be as expected.
9089 @item @sc{run/idle}, @sc{drpause}, and @sc{irpause} are reasonable
9090 choices after @command{drscan} or @command{irscan} commands,
9091 since they are free of JTAG side effects.
9092 @item @sc{run/idle} may have side effects that appear at non-JTAG
9093 levels, such as advancing the ARM9E-S instruction pipeline.
9094 Consult the documentation for the TAP(s) you are working with.
9097 @node Boundary Scan Commands
9098 @chapter Boundary Scan Commands
9100 One of the original purposes of JTAG was to support
9101 boundary scan based hardware testing.
9102 Although its primary focus is to support On-Chip Debugging,
9103 OpenOCD also includes some boundary scan commands.
9105 @section SVF: Serial Vector Format
9106 @cindex Serial Vector Format
9109 The Serial Vector Format, better known as @dfn{SVF}, is a
9110 way to represent JTAG test patterns in text files.
9111 In a debug session using JTAG for its transport protocol,
9112 OpenOCD supports running such test files.
9114 @deffn Command {svf} @file{filename} [@option{-tap @var{tapname}}] [@option{[-]quiet}] @
9115 [@option{[-]nil}] [@option{[-]progress}] [@option{[-]ignore_error}]
9116 This issues a JTAG reset (Test-Logic-Reset) and then
9117 runs the SVF script from @file{filename}.
9119 Arguments can be specified in any order; the optional dash doesn't
9120 affect their semantics.
9124 @item @option{-tap @var{tapname}} ignore IR and DR headers and footers
9125 specified by the SVF file with HIR, TIR, HDR and TDR commands;
9126 instead, calculate them automatically according to the current JTAG
9127 chain configuration, targetting @var{tapname};
9128 @item @option{[-]quiet} do not log every command before execution;
9129 @item @option{[-]nil} ``dry run'', i.e., do not perform any operations
9130 on the real interface;
9131 @item @option{[-]progress} enable progress indication;
9132 @item @option{[-]ignore_error} continue execution despite TDO check
9137 @section XSVF: Xilinx Serial Vector Format
9138 @cindex Xilinx Serial Vector Format
9141 The Xilinx Serial Vector Format, better known as @dfn{XSVF}, is a
9142 binary representation of SVF which is optimized for use with
9144 In a debug session using JTAG for its transport protocol,
9145 OpenOCD supports running such test files.
9147 @quotation Important
9148 Not all XSVF commands are supported.
9151 @deffn Command {xsvf} (tapname|@option{plain}) filename [@option{virt2}] [@option{quiet}]
9152 This issues a JTAG reset (Test-Logic-Reset) and then
9153 runs the XSVF script from @file{filename}.
9154 When a @var{tapname} is specified, the commands are directed at
9156 When @option{virt2} is specified, the @sc{xruntest} command counts
9157 are interpreted as TCK cycles instead of microseconds.
9158 Unless the @option{quiet} option is specified,
9159 messages are logged for comments and some retries.
9162 The OpenOCD sources also include two utility scripts
9163 for working with XSVF; they are not currently installed
9164 after building the software.
9165 You may find them useful:
9168 @item @emph{svf2xsvf} ... converts SVF files into the extended XSVF
9169 syntax understood by the @command{xsvf} command; see notes below.
9170 @item @emph{xsvfdump} ... converts XSVF files into a text output format;
9171 understands the OpenOCD extensions.
9174 The input format accepts a handful of non-standard extensions.
9175 These include three opcodes corresponding to SVF extensions
9176 from Lattice Semiconductor (LCOUNT, LDELAY, LDSR), and
9177 two opcodes supporting a more accurate translation of SVF
9178 (XTRST, XWAITSTATE).
9179 If @emph{xsvfdump} shows a file is using those opcodes, it
9180 probably will not be usable with other XSVF tools.
9183 @node Utility Commands
9184 @chapter Utility Commands
9185 @cindex Utility Commands
9187 @section RAM testing
9190 There is often a need to stress-test random access memory (RAM) for
9191 errors. OpenOCD comes with a Tcl implementation of well-known memory
9192 testing procedures allowing the detection of all sorts of issues with
9193 electrical wiring, defective chips, PCB layout and other common
9196 To use them, you usually need to initialise your RAM controller first;
9197 consult your SoC's documentation to get the recommended list of
9198 register operations and translate them to the corresponding
9199 @command{mww}/@command{mwb} commands.
9201 Load the memory testing functions with
9204 source [find tools/memtest.tcl]
9207 to get access to the following facilities:
9209 @deffn Command {memTestDataBus} address
9210 Test the data bus wiring in a memory region by performing a walking
9211 1's test at a fixed address within that region.
9214 @deffn Command {memTestAddressBus} baseaddress size
9215 Perform a walking 1's test on the relevant bits of the address and
9216 check for aliasing. This test will find single-bit address failures
9217 such as stuck-high, stuck-low, and shorted pins.
9220 @deffn Command {memTestDevice} baseaddress size
9221 Test the integrity of a physical memory device by performing an
9222 increment/decrement test over the entire region. In the process every
9223 storage bit in the device is tested as zero and as one.
9226 @deffn Command {runAllMemTests} baseaddress size
9227 Run all of the above tests over a specified memory region.
9230 @section Firmware recovery helpers
9231 @cindex Firmware recovery
9233 OpenOCD includes an easy-to-use script to facilitate mass-market
9234 devices recovery with JTAG.
9236 For quickstart instructions run:
9238 openocd -f tools/firmware-recovery.tcl -c firmware_help
9244 If OpenOCD runs on an embedded host (as ZY1000 does), then TFTP can
9245 be used to access files on PCs (either the developer's PC or some other PC).
9247 The way this works on the ZY1000 is to prefix a filename by
9248 "/tftp/ip/" and append the TFTP path on the TFTP
9249 server (tftpd). For example,
9252 load_image /tftp/10.0.0.96/c:\temp\abc.elf
9255 will load c:\temp\abc.elf from the developer pc (10.0.0.96) into memory as
9256 if the file was hosted on the embedded host.
9258 In order to achieve decent performance, you must choose a TFTP server
9259 that supports a packet size bigger than the default packet size (512 bytes). There
9260 are numerous TFTP servers out there (free and commercial) and you will have to do
9261 a bit of googling to find something that fits your requirements.
9263 @node GDB and OpenOCD
9264 @chapter GDB and OpenOCD
9266 OpenOCD complies with the remote gdbserver protocol and, as such, can be used
9267 to debug remote targets.
9268 Setting up GDB to work with OpenOCD can involve several components:
9271 @item The OpenOCD server support for GDB may need to be configured.
9272 @xref{gdbconfiguration,,GDB Configuration}.
9273 @item GDB's support for OpenOCD may need configuration,
9274 as shown in this chapter.
9275 @item If you have a GUI environment like Eclipse,
9276 that also will probably need to be configured.
9279 Of course, the version of GDB you use will need to be one which has
9280 been built to know about the target CPU you're using. It's probably
9281 part of the tool chain you're using. For example, if you are doing
9282 cross-development for ARM on an x86 PC, instead of using the native
9283 x86 @command{gdb} command you might use @command{arm-none-eabi-gdb}
9284 if that's the tool chain used to compile your code.
9286 @section Connecting to GDB
9287 @cindex Connecting to GDB
9288 Use GDB 6.7 or newer with OpenOCD if you run into trouble. For
9289 instance GDB 6.3 has a known bug that produces bogus memory access
9290 errors, which has since been fixed; see
9291 @url{http://osdir.com/ml/gdb.bugs.discuss/2004-12/msg00018.html}
9293 OpenOCD can communicate with GDB in two ways:
9297 A socket (TCP/IP) connection is typically started as follows:
9299 target remote localhost:3333
9301 This would cause GDB to connect to the gdbserver on the local pc using port 3333.
9303 It is also possible to use the GDB extended remote protocol as follows:
9305 target extended-remote localhost:3333
9308 A pipe connection is typically started as follows:
9310 target remote | openocd -c "gdb_port pipe; log_output openocd.log"
9312 This would cause GDB to run OpenOCD and communicate using pipes (stdin/stdout).
9313 Using this method has the advantage of GDB starting/stopping OpenOCD for the debug
9314 session. log_output sends the log output to a file to ensure that the pipe is
9315 not saturated when using higher debug level outputs.
9318 To list the available OpenOCD commands type @command{monitor help} on the
9321 @section Sample GDB session startup
9323 With the remote protocol, GDB sessions start a little differently
9324 than they do when you're debugging locally.
9325 Here's an example showing how to start a debug session with a
9327 In this case the program was linked to be loaded into SRAM on a Cortex-M3.
9328 Most programs would be written into flash (address 0) and run from there.
9331 $ arm-none-eabi-gdb example.elf
9332 (gdb) target remote localhost:3333
9333 Remote debugging using localhost:3333
9335 (gdb) monitor reset halt
9338 Loading section .vectors, size 0x100 lma 0x20000000
9339 Loading section .text, size 0x5a0 lma 0x20000100
9340 Loading section .data, size 0x18 lma 0x200006a0
9341 Start address 0x2000061c, load size 1720
9342 Transfer rate: 22 KB/sec, 573 bytes/write.
9348 You could then interrupt the GDB session to make the program break,
9349 type @command{where} to show the stack, @command{list} to show the
9350 code around the program counter, @command{step} through code,
9351 set breakpoints or watchpoints, and so on.
9353 @section Configuring GDB for OpenOCD
9355 OpenOCD supports the gdb @option{qSupported} packet, this enables information
9356 to be sent by the GDB remote server (i.e. OpenOCD) to GDB. Typical information includes
9357 packet size and the device's memory map.
9358 You do not need to configure the packet size by hand,
9359 and the relevant parts of the memory map should be automatically
9360 set up when you declare (NOR) flash banks.
9362 However, there are other things which GDB can't currently query.
9363 You may need to set those up by hand.
9364 As OpenOCD starts up, you will often see a line reporting
9368 Info : lm3s.cpu: hardware has 6 breakpoints, 4 watchpoints
9371 You can pass that information to GDB with these commands:
9374 set remote hardware-breakpoint-limit 6
9375 set remote hardware-watchpoint-limit 4
9378 With that particular hardware (Cortex-M3) the hardware breakpoints
9379 only work for code running from flash memory. Most other ARM systems
9380 do not have such restrictions.
9382 Rather than typing such commands interactively, you may prefer to
9383 save them in a file and have GDB execute them as it starts, perhaps
9384 using a @file{.gdbinit} in your project directory or starting GDB
9385 using @command{gdb -x filename}.
9387 @section Programming using GDB
9388 @cindex Programming using GDB
9389 @anchor{programmingusinggdb}
9391 By default the target memory map is sent to GDB. This can be disabled by
9392 the following OpenOCD configuration option:
9394 gdb_memory_map disable
9396 For this to function correctly a valid flash configuration must also be set
9397 in OpenOCD. For faster performance you should also configure a valid
9400 Informing GDB of the memory map of the target will enable GDB to protect any
9401 flash areas of the target and use hardware breakpoints by default. This means
9402 that the OpenOCD option @command{gdb_breakpoint_override} is not required when
9403 using a memory map. @xref{gdbbreakpointoverride,,gdb_breakpoint_override}.
9405 To view the configured memory map in GDB, use the GDB command @option{info mem}.
9406 All other unassigned addresses within GDB are treated as RAM.
9408 GDB 6.8 and higher set any memory area not in the memory map as inaccessible.
9409 This can be changed to the old behaviour by using the following GDB command
9411 set mem inaccessible-by-default off
9414 If @command{gdb_flash_program enable} is also used, GDB will be able to
9415 program any flash memory using the vFlash interface.
9417 GDB will look at the target memory map when a load command is given, if any
9418 areas to be programmed lie within the target flash area the vFlash packets
9421 If the target needs configuring before GDB programming, set target
9422 event gdb-flash-erase-start:
9424 $_TARGETNAME configure -event gdb-flash-erase-start BODY
9426 @xref{targetevents,,Target Events}, for other GDB programming related events.
9428 To verify any flash programming the GDB command @option{compare-sections}
9431 @section Using GDB as a non-intrusive memory inspector
9432 @cindex Using GDB as a non-intrusive memory inspector
9433 @anchor{gdbmeminspect}
9435 If your project controls more than a blinking LED, let's say a heavy industrial
9436 robot or an experimental nuclear reactor, stopping the controlling process
9437 just because you want to attach GDB is not a good option.
9439 OpenOCD does not support GDB non-stop mode (might be implemented in the future).
9440 Though there is a possible setup where the target does not get stopped
9441 and GDB treats it as it were running.
9442 If the target supports background access to memory while it is running,
9443 you can use GDB in this mode to inspect memory (mainly global variables)
9444 without any intrusion of the target process.
9446 Remove default setting of gdb-attach event. @xref{targetevents,,Target Events}.
9447 Place following command after target configuration:
9449 $_TARGETNAME configure -event gdb-attach @{@}
9452 If any of installed flash banks does not support probe on running target,
9453 switch off gdb_memory_map:
9455 gdb_memory_map disable
9458 Ensure GDB is configured without interrupt-on-connect.
9459 Some GDB versions set it by default, some does not.
9461 set remote interrupt-on-connect off
9464 If you switched gdb_memory_map off, you may want to setup GDB memory map
9465 manually or issue @command{set mem inaccessible-by-default off}
9467 Now you can issue GDB command @command{target remote ...} and inspect memory
9468 of a running target. Do not use GDB commands @command{continue},
9469 @command{step} or @command{next} as they synchronize GDB with your target
9470 and GDB would require stopping the target to get the prompt back.
9472 Do not use this mode under an IDE like Eclipse as it caches values of
9473 previously shown varibles.
9475 @anchor{usingopenocdsmpwithgdb}
9476 @section Using OpenOCD SMP with GDB
9478 For SMP support following GDB serial protocol packet have been defined :
9480 @item j - smp status request
9481 @item J - smp set request
9484 OpenOCD implements :
9486 @item @option{jc} packet for reading core id displayed by
9487 GDB connection. Reply is @option{XXXXXXXX} (8 hex digits giving core id) or
9488 @option{E01} for target not smp.
9489 @item @option{JcXXXXXXXX} (8 hex digits) packet for setting core id displayed at next GDB continue
9490 (core id -1 is reserved for returning to normal resume mode). Reply @option{E01}
9491 for target not smp or @option{OK} on success.
9494 Handling of this packet within GDB can be done :
9496 @item by the creation of an internal variable (i.e @option{_core}) by mean
9497 of function allocate_computed_value allowing following GDB command.
9500 #Jc01 packet is sent
9502 #jc packet is sent and result is affected in $
9505 @item by the usage of GDB maintenance command as described in following example (2 cpus in SMP with
9506 core id 0 and 1 @pxref{definecputargetsworkinginsmp,,Define CPU targets working in SMP}).
9509 # toggle0 : force display of coreid 0
9515 # toggle1 : force display of coreid 1
9524 @section RTOS Support
9525 @cindex RTOS Support
9526 @anchor{gdbrtossupport}
9528 OpenOCD includes RTOS support, this will however need enabling as it defaults to disabled.
9529 It can be enabled by passing @option{-rtos} arg to the target. @xref{rtostype,,RTOS Type}.
9531 @xref{Threads, Debugging Programs with Multiple Threads,
9532 Debugging Programs with Multiple Threads, gdb, GDB manual}, for details about relevant
9535 @* An example setup is below:
9538 $_TARGETNAME configure -rtos auto
9541 This will attempt to auto detect the RTOS within your application.
9543 Currently supported rtos's include:
9546 @item @option{ThreadX}
9547 @item @option{FreeRTOS}
9548 @item @option{linux}
9549 @item @option{ChibiOS}
9550 @item @option{embKernel}
9552 @item @option{uCOS-III}
9556 Before an RTOS can be detected, it must export certain symbols; otherwise, it cannot
9557 be used by OpenOCD. Below is a list of the required symbols for each supported RTOS.
9562 Cyg_Thread::thread_list, Cyg_Scheduler_Base::current_thread.
9563 @item ThreadX symbols
9564 _tx_thread_current_ptr, _tx_thread_created_ptr, _tx_thread_created_count.
9565 @item FreeRTOS symbols
9566 @c The following is taken from recent texinfo to provide compatibility
9567 @c with ancient versions that do not support @raggedright
9570 \rightskip0pt plus2em \spaceskip.3333em \xspaceskip.5em\relax
9571 pxCurrentTCB, pxReadyTasksLists, xDelayedTaskList1, xDelayedTaskList2,
9572 pxDelayedTaskList, pxOverflowDelayedTaskList, xPendingReadyList,
9573 uxCurrentNumberOfTasks, uxTopUsedPriority.
9579 @item ChibiOS symbols
9580 rlist, ch_debug, chSysInit.
9581 @item embKernel symbols
9582 Rtos::sCurrentTask, Rtos::sListReady, Rtos::sListSleep,
9583 Rtos::sListSuspended, Rtos::sMaxPriorities, Rtos::sCurrentTaskCount.
9585 _mqx_kernel_data, MQX_init_struct.
9586 @item uC/OS-III symbols
9587 OSRunning, OSTCBCurPtr, OSTaskDbgListPtr, OSTaskQty
9590 For most RTOS supported the above symbols will be exported by default. However for
9591 some, eg. FreeRTOS and uC/OS-III, extra steps must be taken.
9593 These RTOSes may require additional OpenOCD-specific file to be linked
9594 along with the project:
9598 contrib/rtos-helpers/FreeRTOS-openocd.c
9600 contrib/rtos-helpers/uCOS-III-openocd.c
9603 @node Tcl Scripting API
9604 @chapter Tcl Scripting API
9605 @cindex Tcl Scripting API
9609 Tcl commands are stateless; e.g. the @command{telnet} command has
9610 a concept of currently active target, the Tcl API proc's take this sort
9611 of state information as an argument to each proc.
9613 There are three main types of return values: single value, name value
9614 pair list and lists.
9616 Name value pair. The proc 'foo' below returns a name/value pair
9621 > set foo(you) Oyvind
9622 > set foo(mouse) Micky
9623 > set foo(duck) Donald
9635 me Duane you Oyvind mouse Micky duck Donald
9638 Thus, to get the names of the associative array is easy:
9641 foreach { name value } [set foo] {
9642 puts "Name: $name, Value: $value"
9646 Lists returned should be relatively small. Otherwise, a range
9647 should be passed in to the proc in question.
9649 @section Internal low-level Commands
9651 By "low-level," we mean commands that a human would typically not
9654 Some low-level commands need to be prefixed with "ocd_"; e.g.
9655 @command{ocd_flash_banks}
9656 is the low-level API upon which @command{flash banks} is implemented.
9659 @item @b{mem2array} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
9661 Read memory and return as a Tcl array for script processing
9662 @item @b{array2mem} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
9664 Convert a Tcl array to memory locations and write the values
9665 @item @b{ocd_flash_banks} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}> <@var{target}> [@option{driver options} ...]
9667 Return information about the flash banks
9669 @item @b{capture} <@var{command}>
9671 Run <@var{command}> and return full log output that was produced during
9672 its execution. Example:
9675 > capture "reset init"
9680 OpenOCD commands can consist of two words, e.g. "flash banks". The
9681 @file{startup.tcl} "unknown" proc will translate this into a Tcl proc
9682 called "flash_banks".
9684 @section OpenOCD specific Global Variables
9686 Real Tcl has ::tcl_platform(), and platform::identify, and many other
9687 variables. JimTCL, as implemented in OpenOCD creates $ocd_HOSTOS which
9688 holds one of the following values:
9691 @item @b{cygwin} Running under Cygwin
9692 @item @b{darwin} Darwin (Mac-OS) is the underlying operating sytem.
9693 @item @b{freebsd} Running under FreeBSD
9694 @item @b{openbsd} Running under OpenBSD
9695 @item @b{netbsd} Running under NetBSD
9696 @item @b{linux} Linux is the underlying operating sytem
9697 @item @b{mingw32} Running under MingW32
9698 @item @b{winxx} Built using Microsoft Visual Studio
9699 @item @b{ecos} Running under eCos
9700 @item @b{other} Unknown, none of the above.
9703 Note: 'winxx' was choosen because today (March-2009) no distinction is made between Win32 and Win64.
9706 We should add support for a variable like Tcl variable
9707 @code{tcl_platform(platform)}, it should be called
9708 @code{jim_platform} (because it
9709 is jim, not real tcl).
9712 @section Tcl RPC server
9715 OpenOCD provides a simple RPC server that allows to run arbitrary Tcl
9716 commands and receive the results.
9718 To access it, your application needs to connect to a configured TCP port
9719 (see @command{tcl_port}). Then it can pass any string to the
9720 interpreter terminating it with @code{0x1a} and wait for the return
9721 value (it will be terminated with @code{0x1a} as well). This can be
9722 repeated as many times as desired without reopening the connection.
9724 Remember that most of the OpenOCD commands need to be prefixed with
9725 @code{ocd_} to get the results back. Sometimes you might also need the
9726 @command{capture} command.
9728 See @file{contrib/rpc_examples/} for specific client implementations.
9730 @section Tcl RPC server notifications
9731 @cindex RPC Notifications
9733 Notifications are sent asynchronously to other commands being executed over
9734 the RPC server, so the port must be polled continuously.
9736 Target event, state and reset notifications are emitted as Tcl associative arrays
9737 in the following format.
9740 type target_event event [event-name]
9741 type target_state state [state-name]
9742 type target_reset mode [reset-mode]
9745 @deffn {Command} tcl_notifications [on/off]
9746 Toggle output of target notifications to the current Tcl RPC server.
9747 Only available from the Tcl RPC server.
9752 @section Tcl RPC server trace output
9753 @cindex RPC trace output
9755 Trace data is sent asynchronously to other commands being executed over
9756 the RPC server, so the port must be polled continuously.
9758 Target trace data is emitted as a Tcl associative array in the following format.
9761 type target_trace data [trace-data-hex-encoded]
9764 @deffn {Command} tcl_trace [on/off]
9765 Toggle output of target trace data to the current Tcl RPC server.
9766 Only available from the Tcl RPC server.
9769 See an example application here:
9770 @url{https://github.com/apmorton/OpenOcdTraceUtil} [OpenOcdTraceUtil]
9779 @item @b{RTCK, also known as: Adaptive Clocking - What is it?}
9781 @cindex adaptive clocking
9784 In digital circuit design it is often refered to as ``clock
9785 synchronisation'' the JTAG interface uses one clock (TCK or TCLK)
9786 operating at some speed, your CPU target is operating at another.
9787 The two clocks are not synchronised, they are ``asynchronous''
9789 In order for the two to work together they must be synchronised
9790 well enough to work; JTAG can't go ten times faster than the CPU,
9791 for example. There are 2 basic options:
9794 Use a special "adaptive clocking" circuit to change the JTAG
9795 clock rate to match what the CPU currently supports.
9797 The JTAG clock must be fixed at some speed that's enough slower than
9798 the CPU clock that all TMS and TDI transitions can be detected.
9801 @b{Does this really matter?} For some chips and some situations, this
9802 is a non-issue, like a 500MHz ARM926 with a 5 MHz JTAG link;
9803 the CPU has no difficulty keeping up with JTAG.
9804 Startup sequences are often problematic though, as are other
9805 situations where the CPU clock rate changes (perhaps to save
9808 For example, Atmel AT91SAM chips start operation from reset with
9809 a 32kHz system clock. Boot firmware may activate the main oscillator
9810 and PLL before switching to a faster clock (perhaps that 500 MHz
9812 If you're using JTAG to debug that startup sequence, you must slow
9813 the JTAG clock to sometimes 1 to 4kHz. After startup completes,
9814 JTAG can use a faster clock.
9816 Consider also debugging a 500MHz ARM926 hand held battery powered
9817 device that enters a low power ``deep sleep'' mode, at 32kHz CPU
9818 clock, between keystrokes unless it has work to do. When would
9819 that 5 MHz JTAG clock be usable?
9821 @b{Solution #1 - A special circuit}
9823 In order to make use of this,
9824 your CPU, board, and JTAG adapter must all support the RTCK
9825 feature. Not all of them support this; keep reading!
9827 The RTCK ("Return TCK") signal in some ARM chips is used to help with
9828 this problem. ARM has a good description of the problem described at
9829 this link: @url{http://www.arm.com/support/faqdev/4170.html} [checked
9830 28/nov/2008]. Link title: ``How does the JTAG synchronisation logic
9831 work? / how does adaptive clocking work?''.
9833 The nice thing about adaptive clocking is that ``battery powered hand
9834 held device example'' - the adaptiveness works perfectly all the
9835 time. One can set a break point or halt the system in the deep power
9836 down code, slow step out until the system speeds up.
9838 Note that adaptive clocking may also need to work at the board level,
9839 when a board-level scan chain has multiple chips.
9840 Parallel clock voting schemes are good way to implement this,
9841 both within and between chips, and can easily be implemented
9843 It's not difficult to have logic fan a module's input TCK signal out
9844 to each TAP in the scan chain, and then wait until each TAP's RTCK comes
9845 back with the right polarity before changing the output RTCK signal.
9846 Texas Instruments makes some clock voting logic available
9847 for free (with no support) in VHDL form; see
9848 @url{http://tiexpressdsp.com/index.php/Adaptive_Clocking}
9850 @b{Solution #2 - Always works - but may be slower}
9852 Often this is a perfectly acceptable solution.
9854 In most simple terms: Often the JTAG clock must be 1/10 to 1/12 of
9855 the target clock speed. But what that ``magic division'' is varies
9856 depending on the chips on your board.
9857 @b{ARM rule of thumb} Most ARM based systems require an 6:1 division;
9858 ARM11 cores use an 8:1 division.
9859 @b{Xilinx rule of thumb} is 1/12 the clock speed.
9861 Note: most full speed FT2232 based JTAG adapters are limited to a
9862 maximum of 6MHz. The ones using USB high speed chips (FT2232H)
9863 often support faster clock rates (and adaptive clocking).
9865 You can still debug the 'low power' situations - you just need to
9866 either use a fixed and very slow JTAG clock rate ... or else
9867 manually adjust the clock speed at every step. (Adjusting is painful
9868 and tedious, and is not always practical.)
9870 It is however easy to ``code your way around it'' - i.e.: Cheat a little,
9871 have a special debug mode in your application that does a ``high power
9872 sleep''. If you are careful - 98% of your problems can be debugged
9875 Note that on ARM you may need to avoid using the @emph{wait for interrupt}
9876 operation in your idle loops even if you don't otherwise change the CPU
9878 That operation gates the CPU clock, and thus the JTAG clock; which
9879 prevents JTAG access. One consequence is not being able to @command{halt}
9880 cores which are executing that @emph{wait for interrupt} operation.
9882 To set the JTAG frequency use the command:
9890 @item @b{Win32 Pathnames} Why don't backslashes work in Windows paths?
9892 OpenOCD uses Tcl and a backslash is an escape char. Use @{ and @}
9893 around Windows filenames.
9906 @item @b{Missing: cygwin1.dll} OpenOCD complains about a missing cygwin1.dll.
9908 Make sure you have Cygwin installed, or at least a version of OpenOCD that
9909 claims to come with all the necessary DLLs. When using Cygwin, try launching
9910 OpenOCD from the Cygwin shell.
9912 @item @b{Breakpoint Issue} I'm trying to set a breakpoint using GDB (or a frontend like Insight or
9913 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
9914 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
9916 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
9917 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720T or ARM920T,
9918 software breakpoints consume one of the two available hardware breakpoints.
9920 @item @b{LPC2000 Flash} When erasing or writing LPC2000 on-chip flash, the operation fails at random.
9922 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
9923 clock at the time you're programming the flash. If you've specified the crystal's
9924 frequency, make sure the PLL is disabled. If you've specified the full core speed
9925 (e.g. 60MHz), make sure the PLL is enabled.
9927 @item @b{Amontec Chameleon} When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
9928 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
9929 out while waiting for end of scan, rtck was disabled".
9931 Make sure your PC's parallel port operates in EPP mode. You might have to try several
9932 settings in your PC BIOS (ECP, EPP, and different versions of those).
9934 @item @b{Data Aborts} When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
9935 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
9936 memory read caused data abort".
9938 The errors are non-fatal, and are the result of GDB trying to trace stack frames
9939 beyond the last valid frame. It might be possible to prevent this by setting up
9940 a proper "initial" stack frame, if you happen to know what exactly has to
9941 be done, feel free to add this here.
9943 @b{Simple:} In your startup code - push 8 registers of zeros onto the
9944 stack before calling main(). What GDB is doing is ``climbing'' the run
9945 time stack by reading various values on the stack using the standard
9946 call frame for the target. GDB keeps going - until one of 2 things
9947 happen @b{#1} an invalid frame is found, or @b{#2} some huge number of
9948 stackframes have been processed. By pushing zeros on the stack, GDB
9951 @b{Debugging Interrupt Service Routines} - In your ISR before you call
9952 your C code, do the same - artifically push some zeros onto the stack,
9953 remember to pop them off when the ISR is done.
9955 @b{Also note:} If you have a multi-threaded operating system, they
9956 often do not @b{in the intrest of saving memory} waste these few
9960 @item @b{JTAG Reset Config} I get the following message in the OpenOCD console (or log file):
9961 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
9963 This warning doesn't indicate any serious problem, as long as you don't want to
9964 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
9965 trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
9966 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
9967 independently. With this setup, it's not possible to halt the core right out of
9968 reset, everything else should work fine.
9970 @item @b{USB Power} When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
9971 toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
9972 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
9973 quit with an error message. Is there a stability issue with OpenOCD?
9975 No, this is not a stability issue concerning OpenOCD. Most users have solved
9976 this issue by simply using a self-powered USB hub, which they connect their
9977 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
9978 supply stable enough for the Amontec JTAGkey to be operated.
9980 @b{Laptops running on battery have this problem too...}
9982 @item @b{GDB Disconnects} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
9983 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
9984 What does that mean and what might be the reason for this?
9986 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
9987 has closed the connection to OpenOCD. This might be a GDB issue.
9989 @item @b{LPC2000 Flash} In the configuration file in the section where flash device configurations
9990 are described, there is a parameter for specifying the clock frequency
9991 for LPC2000 internal flash devices (e.g. @option{flash bank $_FLASHNAME lpc2000
9992 0x0 0x40000 0 0 $_TARGETNAME lpc2000_v1 14746 calc_checksum}), which must be
9993 specified in kilohertz. However, I do have a quartz crystal of a
9994 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz,
9995 i.e. 14,745.600 kHz). Is it possible to specify real numbers for the
9998 No. The clock frequency specified here must be given as an integral number.
9999 However, this clock frequency is used by the In-Application-Programming (IAP)
10000 routines of the LPC2000 family only, which seems to be very tolerant concerning
10001 the given clock frequency, so a slight difference between the specified clock
10002 frequency and the actual clock frequency will not cause any trouble.
10004 @item @b{Command Order} Do I have to keep a specific order for the commands in the configuration file?
10006 Well, yes and no. Commands can be given in arbitrary order, yet the
10007 devices listed for the JTAG scan chain must be given in the right
10008 order (jtag newdevice), with the device closest to the TDO-Pin being
10009 listed first. In general, whenever objects of the same type exist
10010 which require an index number, then these objects must be given in the
10011 right order (jtag newtap, targets and flash banks - a target
10012 references a jtag newtap and a flash bank references a target).
10014 You can use the ``scan_chain'' command to verify and display the tap order.
10016 Also, some commands can't execute until after @command{init} has been
10017 processed. Such commands include @command{nand probe} and everything
10018 else that needs to write to controller registers, perhaps for setting
10019 up DRAM and loading it with code.
10021 @anchor{faqtaporder}
10022 @item @b{JTAG TAP Order} Do I have to declare the TAPS in some
10025 Yes; whenever you have more than one, you must declare them in
10026 the same order used by the hardware.
10028 Many newer devices have multiple JTAG TAPs. For example: ST
10029 Microsystems STM32 chips have two TAPs, a ``boundary scan TAP'' and
10030 ``Cortex-M3'' TAP. Example: The STM32 reference manual, Document ID:
10031 RM0008, Section 26.5, Figure 259, page 651/681, the ``TDI'' pin is
10032 connected to the boundary scan TAP, which then connects to the
10033 Cortex-M3 TAP, which then connects to the TDO pin.
10035 Thus, the proper order for the STM32 chip is: (1) The Cortex-M3, then
10036 (2) The boundary scan TAP. If your board includes an additional JTAG
10037 chip in the scan chain (for example a Xilinx CPLD or FPGA) you could
10038 place it before or after the STM32 chip in the chain. For example:
10041 @item OpenOCD_TDI(output) -> STM32 TDI Pin (BS Input)
10042 @item STM32 BS TDO (output) -> STM32 Cortex-M3 TDI (input)
10043 @item STM32 Cortex-M3 TDO (output) -> SM32 TDO Pin
10044 @item STM32 TDO Pin (output) -> Xilinx TDI Pin (input)
10045 @item Xilinx TDO Pin -> OpenOCD TDO (input)
10048 The ``jtag device'' commands would thus be in the order shown below. Note:
10051 @item jtag newtap Xilinx tap -irlen ...
10052 @item jtag newtap stm32 cpu -irlen ...
10053 @item jtag newtap stm32 bs -irlen ...
10054 @item # Create the debug target and say where it is
10055 @item target create stm32.cpu -chain-position stm32.cpu ...
10059 @item @b{SYSCOMP} Sometimes my debugging session terminates with an error. When I look into the
10060 log file, I can see these error messages: Error: arm7_9_common.c:561
10061 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP
10067 @node Tcl Crash Course
10068 @chapter Tcl Crash Course
10071 Not everyone knows Tcl - this is not intended to be a replacement for
10072 learning Tcl, the intent of this chapter is to give you some idea of
10073 how the Tcl scripts work.
10075 This chapter is written with two audiences in mind. (1) OpenOCD users
10076 who need to understand a bit more of how Jim-Tcl works so they can do
10077 something useful, and (2) those that want to add a new command to
10080 @section Tcl Rule #1
10081 There is a famous joke, it goes like this:
10083 @item Rule #1: The wife is always correct
10084 @item Rule #2: If you think otherwise, See Rule #1
10087 The Tcl equal is this:
10090 @item Rule #1: Everything is a string
10091 @item Rule #2: If you think otherwise, See Rule #1
10094 As in the famous joke, the consequences of Rule #1 are profound. Once
10095 you understand Rule #1, you will understand Tcl.
10097 @section Tcl Rule #1b
10098 There is a second pair of rules.
10100 @item Rule #1: Control flow does not exist. Only commands
10101 @* For example: the classic FOR loop or IF statement is not a control
10102 flow item, they are commands, there is no such thing as control flow
10104 @item Rule #2: If you think otherwise, See Rule #1
10105 @* Actually what happens is this: There are commands that by
10106 convention, act like control flow key words in other languages. One of
10107 those commands is the word ``for'', another command is ``if''.
10110 @section Per Rule #1 - All Results are strings
10111 Every Tcl command results in a string. The word ``result'' is used
10112 deliberatly. No result is just an empty string. Remember: @i{Rule #1 -
10113 Everything is a string}
10115 @section Tcl Quoting Operators
10116 In life of a Tcl script, there are two important periods of time, the
10117 difference is subtle.
10120 @item Evaluation Time
10123 The two key items here are how ``quoted things'' work in Tcl. Tcl has
10124 three primary quoting constructs, the [square-brackets] the
10125 @{curly-braces@} and ``double-quotes''
10127 By now you should know $VARIABLES always start with a $DOLLAR
10128 sign. BTW: To set a variable, you actually use the command ``set'', as
10129 in ``set VARNAME VALUE'' much like the ancient BASIC langauge ``let x
10130 = 1'' statement, but without the equal sign.
10133 @item @b{[square-brackets]}
10134 @* @b{[square-brackets]} are command substitutions. It operates much
10135 like Unix Shell `back-ticks`. The result of a [square-bracket]
10136 operation is exactly 1 string. @i{Remember Rule #1 - Everything is a
10137 string}. These two statements are roughly identical:
10141 echo "The Date is: $X"
10144 puts "The Date is: $X"
10146 @item @b{``double-quoted-things''}
10147 @* @b{``double-quoted-things''} are just simply quoted
10148 text. $VARIABLES and [square-brackets] are expanded in place - the
10149 result however is exactly 1 string. @i{Remember Rule #1 - Everything
10153 puts "It is now \"[date]\", $x is in 1 hour"
10155 @item @b{@{Curly-Braces@}}
10156 @*@b{@{Curly-Braces@}} are magic: $VARIABLES and [square-brackets] are
10157 parsed, but are NOT expanded or executed. @{Curly-Braces@} are like
10158 'single-quote' operators in BASH shell scripts, with the added
10159 feature: @{curly-braces@} can be nested, single quotes can not. @{@{@{this is
10160 nested 3 times@}@}@} NOTE: [date] is a bad example;
10161 at this writing, Jim/OpenOCD does not have a date command.
10164 @section Consequences of Rule 1/2/3/4
10166 The consequences of Rule 1 are profound.
10168 @subsection Tokenisation & Execution.
10170 Of course, whitespace, blank lines and #comment lines are handled in
10173 As a script is parsed, each (multi) line in the script file is
10174 tokenised and according to the quoting rules. After tokenisation, that
10175 line is immedatly executed.
10177 Multi line statements end with one or more ``still-open''
10178 @{curly-braces@} which - eventually - closes a few lines later.
10180 @subsection Command Execution
10182 Remember earlier: There are no ``control flow''
10183 statements in Tcl. Instead there are COMMANDS that simply act like
10184 control flow operators.
10186 Commands are executed like this:
10189 @item Parse the next line into (argc) and (argv[]).
10190 @item Look up (argv[0]) in a table and call its function.
10191 @item Repeat until End Of File.
10194 It sort of works like this:
10197 ReadAndParse( &argc, &argv );
10199 cmdPtr = LookupCommand( argv[0] );
10201 (*cmdPtr->Execute)( argc, argv );
10205 When the command ``proc'' is parsed (which creates a procedure
10206 function) it gets 3 parameters on the command line. @b{1} the name of
10207 the proc (function), @b{2} the list of parameters, and @b{3} the body
10208 of the function. Not the choice of words: LIST and BODY. The PROC
10209 command stores these items in a table somewhere so it can be found by
10210 ``LookupCommand()''
10212 @subsection The FOR command
10214 The most interesting command to look at is the FOR command. In Tcl,
10215 the FOR command is normally implemented in C. Remember, FOR is a
10216 command just like any other command.
10218 When the ascii text containing the FOR command is parsed, the parser
10219 produces 5 parameter strings, @i{(If in doubt: Refer to Rule #1)} they
10223 @item The ascii text 'for'
10224 @item The start text
10225 @item The test expression
10226 @item The next text
10227 @item The body text
10230 Sort of reminds you of ``main( int argc, char **argv )'' does it not?
10231 Remember @i{Rule #1 - Everything is a string.} The key point is this:
10232 Often many of those parameters are in @{curly-braces@} - thus the
10233 variables inside are not expanded or replaced until later.
10235 Remember that every Tcl command looks like the classic ``main( argc,
10236 argv )'' function in C. In JimTCL - they actually look like this:
10240 MyCommand( Jim_Interp *interp,
10242 Jim_Obj * const *argvs );
10245 Real Tcl is nearly identical. Although the newer versions have
10246 introduced a byte-code parser and intepreter, but at the core, it
10247 still operates in the same basic way.
10249 @subsection FOR command implementation
10251 To understand Tcl it is perhaps most helpful to see the FOR
10252 command. Remember, it is a COMMAND not a control flow structure.
10254 In Tcl there are two underlying C helper functions.
10256 Remember Rule #1 - You are a string.
10258 The @b{first} helper parses and executes commands found in an ascii
10259 string. Commands can be seperated by semicolons, or newlines. While
10260 parsing, variables are expanded via the quoting rules.
10262 The @b{second} helper evaluates an ascii string as a numerical
10263 expression and returns a value.
10265 Here is an example of how the @b{FOR} command could be
10266 implemented. The pseudo code below does not show error handling.
10268 void Execute_AsciiString( void *interp, const char *string );
10270 int Evaluate_AsciiExpression( void *interp, const char *string );
10273 MyForCommand( void *interp,
10278 SetResult( interp, "WRONG number of parameters");
10282 // argv[0] = the ascii string just like C
10284 // Execute the start statement.
10285 Execute_AsciiString( interp, argv[1] );
10287 // Top of loop test
10289 i = Evaluate_AsciiExpression(interp, argv[2]);
10293 // Execute the body
10294 Execute_AsciiString( interp, argv[3] );
10296 // Execute the LOOP part
10297 Execute_AsciiString( interp, argv[4] );
10301 SetResult( interp, "" );
10306 Every other command IF, WHILE, FORMAT, PUTS, EXPR, everything works
10307 in the same basic way.
10309 @section OpenOCD Tcl Usage
10311 @subsection source and find commands
10312 @b{Where:} In many configuration files
10313 @* Example: @b{ source [find FILENAME] }
10314 @*Remember the parsing rules
10316 @item The @command{find} command is in square brackets,
10317 and is executed with the parameter FILENAME. It should find and return
10318 the full path to a file with that name; it uses an internal search path.
10319 The RESULT is a string, which is substituted into the command line in
10320 place of the bracketed @command{find} command.
10321 (Don't try to use a FILENAME which includes the "#" character.
10322 That character begins Tcl comments.)
10323 @item The @command{source} command is executed with the resulting filename;
10324 it reads a file and executes as a script.
10326 @subsection format command
10327 @b{Where:} Generally occurs in numerous places.
10328 @* Tcl has no command like @b{printf()}, instead it has @b{format}, which is really more like
10334 puts [format "The answer: %d" [expr $x * $y]]
10337 @item The SET command creates 2 variables, X and Y.
10338 @item The double [nested] EXPR command performs math
10339 @* The EXPR command produces numerical result as a string.
10340 @* Refer to Rule #1
10341 @item The format command is executed, producing a single string
10342 @* Refer to Rule #1.
10343 @item The PUTS command outputs the text.
10345 @subsection Body or Inlined Text
10346 @b{Where:} Various TARGET scripts.
10349 proc someproc @{@} @{
10350 ... multiple lines of stuff ...
10352 $_TARGETNAME configure -event FOO someproc
10353 #2 Good - no variables
10354 $_TARGETNAME confgure -event foo "this ; that;"
10355 #3 Good Curly Braces
10356 $_TARGETNAME configure -event FOO @{
10357 puts "Time: [date]"
10359 #4 DANGER DANGER DANGER
10360 $_TARGETNAME configure -event foo "puts \"Time: [date]\""
10363 @item The $_TARGETNAME is an OpenOCD variable convention.
10364 @*@b{$_TARGETNAME} represents the last target created, the value changes
10365 each time a new target is created. Remember the parsing rules. When
10366 the ascii text is parsed, the @b{$_TARGETNAME} becomes a simple string,
10367 the name of the target which happens to be a TARGET (object)
10369 @item The 2nd parameter to the @option{-event} parameter is a TCBODY
10370 @*There are 4 examples:
10372 @item The TCLBODY is a simple string that happens to be a proc name
10373 @item The TCLBODY is several simple commands seperated by semicolons
10374 @item The TCLBODY is a multi-line @{curly-brace@} quoted string
10375 @item The TCLBODY is a string with variables that get expanded.
10378 In the end, when the target event FOO occurs the TCLBODY is
10379 evaluated. Method @b{#1} and @b{#2} are functionally identical. For
10380 Method @b{#3} and @b{#4} it is more interesting. What is the TCLBODY?
10382 Remember the parsing rules. In case #3, @{curly-braces@} mean the
10383 $VARS and [square-brackets] are expanded later, when the EVENT occurs,
10384 and the text is evaluated. In case #4, they are replaced before the
10385 ``Target Object Command'' is executed. This occurs at the same time
10386 $_TARGETNAME is replaced. In case #4 the date will never
10387 change. @{BTW: [date] is a bad example; at this writing,
10388 Jim/OpenOCD does not have a date command@}
10390 @subsection Global Variables
10391 @b{Where:} You might discover this when writing your own procs @* In
10392 simple terms: Inside a PROC, if you need to access a global variable
10393 you must say so. See also ``upvar''. Example:
10395 proc myproc @{ @} @{
10396 set y 0 #Local variable Y
10397 global x #Global variable X
10398 puts [format "X=%d, Y=%d" $x $y]
10401 @section Other Tcl Hacks
10402 @b{Dynamic variable creation}
10404 # Dynamically create a bunch of variables.
10405 for @{ set x 0 @} @{ $x < 32 @} @{ set x [expr $x + 1]@} @{
10407 set vn [format "BIT%d" $x]
10411 set $vn [expr (1 << $x)]
10414 @b{Dynamic proc/command creation}
10416 # One "X" function - 5 uart functions.
10417 foreach who @{A B C D E@}
10418 proc [format "show_uart%c" $who] @{ @} "show_UARTx $who"
10424 @node OpenOCD Concept Index
10425 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
10426 @comment case issue with ``Index.html'' and ``index.html''
10427 @comment Occurs when creating ``--html --no-split'' output
10428 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
10429 @unnumbered OpenOCD Concept Index
10433 @node Command and Driver Index
10434 @unnumbered Command and Driver Index