1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle Open On-Chip Debugger (openocd)
10 @title Open On-Chip Debugger (openocd)
11 @subtitle Edition @value{EDITION} for openocd version @value{VERSION}
12 @subtitle @value{UPDATED}
14 @vskip 0pt plus 1filll
19 @node Top, About, , (dir)
22 This is edition @value{EDITION} of the openocd manual for version
23 @value{VERSION}, @value{UPDATED}
26 * About:: About Openocd.
28 * Building:: Building Openocd
29 * Running:: Running Openocd
30 * Configuration:: Openocd Configuration.
31 * Commands:: Openocd Commands
32 * Sample Scripts:: Sample Target Scripts
33 * GDB and Openocd:: Using GDB and Openocd
34 * FAQ:: Frequently Asked Questions
35 * License:: GNU Free Documentation License
43 The Open On-Chip Debugger (openocd) aims to provide debugging, in-system programming
44 and boundary-scan testing for embedded target devices. The targets are interfaced
45 using JTAG (IEEE 1149.1) compliant hardware, but this may be extended to other
46 connection types in the future.
48 Openocd currently supports Wiggler (clones), FTDI FT2232 based JTAG interfaces, the
49 Amontec JTAG Accelerator, and the Gateworks GW1602. It allows ARM7 (ARM7TDMI and ARM720t),
50 ARM9 (ARM920t, ARM922t, ARM926ej--s, ARM966e--s), XScale (PXA25x, IXP42x) and
51 Cortex-M3 (Luminary Stellaris LM3 and ST STM32) based cores to be debugged.
53 Flash writing is supported for external CFI compatible flashes (Intel and AMD/Spansion
54 command set) and several internal flashes (LPC2000, AT91SAM7, STR7x, STR9x, LM3
55 and STM32x). Preliminary support for using the LPC3180's NAND flash controller is included.
61 Openocd has been created by Dominic Rath as part of a diploma thesis written at the
62 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
63 Others interested in improving the state of free and open debug and testing technology
64 are welcome to participate.
66 Other developers have contributed support for additional targets and flashes as well
67 as numerous bugfixes and enhancements. See the AUTHORS file for regular contributors.
71 @cindex building openocd
73 You can download the current SVN version with SVN client of your choice from the
74 following repositories:
76 (@uref{svn://svn.berlios.de/openocd/trunk})
80 (@uref{http://svn.berlios.de/svnroot/repos/openocd/trunk})
82 Using the SVN command line client, you could use the following command to fetch the
83 latest version (make sure there is no (non-svn) directory called "openocd" in the
87 svn checkout svn://svn.berlios.de/openocd/trunk
90 Building the OpenOCD requires a recent version of the GNU autotools.
91 On my build system, I'm using autoconf 2.13 and automake 1.9. For building on Windows,
92 you have to use Cygwin. Make sure that your @env{PATH} environment variable contains no
93 other locations with Unix utils (like UnxUtils) - these can't handle the Cygwin
94 paths, resulting in obscure dependency errors (This is an observation I've gathered
95 from the logs of one user - correct me if I'm wrong).
97 You further need the appropriate driver files, if you want to build support for
98 a FTDI FT2232 based interface:
100 @item @b{ftdi2232} libftdi (@uref{http://www.intra2net.com/opensource/ftdi/})
101 @item @b{ftd2xx} libftd2xx (@uref{http://www.ftdichip.com/Drivers/D2XX.htm})
102 @item When using the Amontec JTAGkey, you have to get the drivers from the Amontec
103 homepage (@uref{www.amontec.com}), as the JTAGkey uses a non-standard VID/PID.
106 Please note that the ftdi2232 variant (using libftdi) isn't supported under Cygwin.
107 You have to use the ftd2xx variant (using FTDI's D2XX) on Cygwin.
109 In general, the D2XX driver provides superior performance (several times as fast),
110 but has the draw-back of being binary-only - though that isn't as worse, as it isn't
111 a kernel module, only a user space library.
113 To build OpenOCD (on both Linux and Cygwin), use the following commands:
117 Bootstrap generates the configure script, and prepares building on your system.
121 Configure generates the Makefiles used to build OpenOCD
125 Make builds the OpenOCD, and places the final executable in ./src/
127 The configure script takes several options, specifying which JTAG interfaces
134 --enable-parport_ppdev
136 --enable-amtjtagaccel
138 --enable-ft2232_ftd2xx
139 @footnote{Using the latest D2XX drivers from FTDI and following their installation
140 instructions, I had to use @option{--enable-ft2232_libftd2xx} for the OpenOCD to
143 --enable-ft2232_libftdi
145 --with-ftd2xx=/path/to/d2xx/
148 If you want to access the parallel port using the PPDEV interface you have to specify
149 both the @option{--enable-parport} AND the @option{--enable-parport_ppdev} option since
150 the @option{--enable-parport_ppdev} option actually is an option to the parport driver
151 (see @uref{http://forum.sparkfun.com/viewtopic.php?t=3795} for more info).
153 Cygwin users have to specify the location of the FTDI D2XX package. This should be an
154 absolute path containing no spaces.
156 Linux users should copy the various parts of the D2XX package to the appropriate
157 locations, i.e. /usr/include, /usr/lib.
161 @cindex running openocd
162 The OpenOCD runs as a daemon, waiting for connections from clients (Telnet or GDB).
163 Run with @option{--help} or @option{-h} to view the available command line arguments.
165 It reads its configuration by default from the file openocd.cfg located in the current
166 working directory. This may be overwritten with the @option{-f <configfile>} command line
169 To enable debug output (when reporting problems or working on OpenOCD itself), use
170 the @option{-d} command line switch. This sets the debug_level to "3", outputting
171 the most information, including debug messages. The default setting is "2", outputting
172 only informational messages, warnings and errors. You can also change this setting
173 from within a telnet or gdb session (@option{debug_level <n>}).
175 You can redirect all output from the daemon to a file using the @option{-l <logfile>} switch.
178 @chapter Configuration
179 @cindex configuration
180 The Open On-Chip Debugger (OpenOCD) runs as a daemon, and reads it current configuration
181 by default from the file openocd.cfg in the current directory. A different configuration
182 file can be specified with the @option{-f <conf.file>} given at the openocd command line.
184 The configuration file is used to specify on which ports the daemon listens for new
185 connections, the JTAG interface used to connect to the target, the layout of the JTAG
186 chain, the targets that should be debugged, and connected flashes.
188 @section Daemon configuration
191 @item @b{telnet_port} <@var{number}>
193 Port on which to listen for incoming telnet connections
194 @item @b{gdb_port} <@var{number}>
196 First port on which to listen for incoming GDB connections. The GDB port for the
197 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
198 @item @b{gdb_detach} <@var{resume|reset|halt|nothing}>
200 Configures what openocd will do when gdb detaches from the daeman.
201 Default behaviour is <@var{resume}>
202 @item @b{gdb_memory_map} <@var{enable|disable}>
203 @cindex gdb_memory_map
204 Set to <@var{enable}> so that openocd will send the memory configuration to gdb when
205 requested. gdb will then know when to set hardware breakpoints, and program flash
206 using the gdb load command. @option{gdb_flash_program enable} will also need enabling
207 for flash programming to work.
208 Default behaviour is <@var{disable}>
209 @item @b{gdb_flash_program} <@var{enable|disable}>
210 @cindex gdb_flash_program
211 Set to <@var{enable}> so that openocd will program the flash memory when a
212 vFlash packet is received.
213 Default behaviour is <@var{disable}>
214 @item @b{daemon_startup} <@var{mode}> either @samp{attach} or @samp{reset}
215 @cindex daemon_startup
216 Tells the OpenOCD whether it should reset the target when the daemon is launched, or
217 if it should just attach to the target.
220 @section JTAG interface configuration
223 @item @b{interface} <@var{name}>
225 Use the interface driver <@var{name}> to connect to the target. Currently supported
229 PC parallel port bit-banging (Wigglers, PLD download cable, ...)
233 Amontec Chameleon in its JTAG Accelerator configuration connected to a PC's EPP
238 FTDI FT2232 based devices using either the open-source libftdi or the binary only
239 FTD2XX driver. The FTD2XX is superior in performance, but not available on every
240 platform. The libftdi uses libusb, and should be portable to all systems that provide
245 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
250 @item @b{jtag_speed} <@var{number}>
252 Limit the maximum speed of the JTAG interface. Usually, a value of zero means maximum
253 speed. The actual effect of this option depends on the JTAG interface used.
255 @item @b{reset_config} <@var{signals}> [@var{combination}] [@var{trst_type}] [@var{srst_type}]
257 The configuration of the reset signals available on the JTAG interface AND the target.
258 If the JTAG interface provides SRST, but the target doesn't connect that signal properly,
259 then OpenOCD can't use it. <@var{signals}> can be @samp{none}, @samp{trst_only},
260 @samp{srst_only} or @samp{trst_and_srst}.
261 [@var{combination}] is an optional value specifying broken reset signal implementations.
262 @samp{srst_pulls_trst} states that the testlogic is reset together with the reset of
263 the system (e.g. Philips LPC2000, "broken" board layout), @samp{trst_pulls_srst} says
264 that the system is reset together with the test logic (only hypothetical, I haven't
265 seen hardware with such a bug, and can be worked around).
267 The [@var{trst_type}] and [@var{srst_type}] parameters allow the driver type of the
268 reset lines to be specified. Possible values are @samp{trst_push_pull} (default)
269 and @samp{trst_open_drain} for the test reset signal, and @samp{srst_open_drain}
270 (default) and @samp{srst_push_pull} for the system reset. These values only affect
271 JTAG interfaces with support for different drivers, like the Amontec JTAGkey and JTAGAccelerator.
273 @item @b{jtag_device} <@var{IR length}> <@var{IR capture}> <@var{IR mask}> <@var{IDCODE instruction}>
275 Describes the devices that form the JTAG daisy chain, with the first device being
276 the one closest to TDO. The parameters are the length of the instruction register
277 (4 for all ARM7/9s), the value captured during Capture-IR (0x1 for ARM7/9), and a mask
278 of bits that should be validated when doing IR scans (all four bits (0xf) for ARM7/9).
279 The IDCODE instruction will in future be used to query devices for their JTAG
280 identification code. This line is the same for all ARM7 and ARM9 devices.
281 Other devices, like CPLDs, require different parameters. An example configuration
282 line for a Xilinx XC9500 CPLD would look like this:
284 jtag_device 8 0x01 0x0e3 0xfe
286 The instruction register (IR) is 8 bits long, during Capture-IR 0x01 is loaded into
287 the IR, but only bits 0-1 and 5-7 should be checked, the others (2-4) might vary.
288 The IDCODE instruction is 0xfe.
290 @item @b{jtag_nsrst_delay} <@var{ms}>
291 @cindex jtag_nsrst_delay
292 How long (in miliseconds) the OpenOCD should wait after deasserting nSRST before
293 starting new JTAG operations.
294 @item @b{jtag_ntrst_delay} <@var{ms}>
295 @cindex jtag_ntrst_delay
296 How long (in miliseconds) the OpenOCD should wait after deasserting nTRST before
297 starting new JTAG operations.
299 The jtag_n[st]rst_delay options are useful if reset circuitry (like a reset supervisor,
300 or on-chip features) keep a reset line asserted for some time after the external reset
304 @section parport options
307 @item @b{parport_port} <@var{number}>
309 Either the address of the I/O port (default: 0x378 for LPT1) or the number of
310 the @file{/dev/parport} device
312 When using PPDEV to access the parallel port, use the number of the parallel port:
313 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
314 you may encounter a problem.
315 @item @b{parport_cable} <@var{name}>
316 @cindex parport_cable
317 The layout of the parallel port cable used to connect to the target.
318 Currently supported cables are
322 Original Wiggler layout, also supported by several clones, such
323 as the Olimex ARM-JTAG
324 @item old_amt_wiggler
325 @cindex old_amt_wiggler
326 The Wiggler configuration that comes with Amontec's Chameleon Programmer. The new
327 version available from the website uses the original Wiggler layout ('@var{wiggler}')
330 Describes the connection of the Amontec Chameleon's CPLD when operated in
331 configuration mode. This is only used to program the Chameleon itself, not
335 Xilinx Parallel cable III.
338 The parallel port adapter found on the 'Karo Triton 1 Development Board'.
339 This is also the layout used by the HollyGates design
340 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
345 @item @b{parport_write_on_exit} <@var{on|off}>
346 @cindex parport_write_on_exit
347 This will configure the parallel driver to write a known value to the parallel
348 interface on exiting openocd
351 @section amt_jtagaccel options
353 @item @b{parport_port} <@var{number}>
355 Either the address of the I/O port (default: 0x378 for LPT1) or the number of the
356 @file{/dev/parport} device
358 @section ft2232 options
361 @item @b{ft2232_device_desc} <@var{description}>
362 @cindex ft2232_device_desc
363 The USB device description of the FTDI FT2232 device. If not specified, the FTDI
364 default value is used. This setting is only valid if compiled with FTD2XX support.
365 @item @b{ft2232_layout} <@var{name}>
366 @cindex ft2232_layout
367 The layout of the FT2232 GPIO signals used to control output-enables and reset
368 signals. Valid layouts are
371 The "USBJTAG-1" layout described in the original OpenOCD diploma thesis
373 Amontec JTAGkey and JTAGkey-tiny
379 American Microsystems M5960
381 Luminary Micro EVB_LM3S811 as a JTAG interface (not onboard processor), no TRST or
382 SRST signals on external connector
386 Hitex STM32 Performance Stick
389 @item @b{ft2232_vid_pid} <@var{vid}> <@var{pid}>
390 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
391 default values are used. This command is not available on Windows.
392 @item @b{ft2232_latency} <@var{ms}>
393 On some systems using ft2232 based JTAG interfaces the FT_Read function call in
394 ft2232_read() fails to return the expected number of bytes. This can be caused by
395 USB communication delays and has proved hard to reproduce and debug. Setting the
396 FT2232 latency timer to a larger value increases delays for short USB packages but it
397 also reduces the risk of timeouts before receiving the expected number of bytes.
398 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
401 @section ep93xx options
402 @cindex ep93xx options
403 Currently, there are no options available for the ep93xx interface.
406 @section Target configuration
409 @item @b{target} <@var{type}> <@var{endianess}> <@var{reset_mode}> <@var{JTAG pos}>
412 Defines a target that should be debugged. Currently supported types are:
425 If you want to use a target board that is not on this list, see Adding a new
428 Endianess may be @option{little} or @option{big}.
430 The reset_mode specifies what should happen to the target when a reset occurs:
434 Immediately request a target halt after reset. This allows targets to be debugged
435 from the very first instruction. This is only possible with targets and JTAG
436 interfaces that correctly implement the reset signals.
439 Similar to @option{reset_halt}, but executes the script file defined to handle the
440 'reset' event for the target. Like @option{reset_halt} this only works with
441 correct reset implementations.
444 Simply let the target run after a reset.
447 Let the target run for some time (default: 1s), and then request halt.
450 A combination of @option{reset_init} and @option{run_and_halt}. The target is allowed
451 to run for some time, then halted, and the @option{reset} event script is executed.
454 On JTAG interfaces / targets where system reset and test-logic reset can't be driven
455 completely independent (like the LPC2000 series), or where the JTAG interface is
456 unavailable for some time during startup (like the STR7 series), you can't use
457 @option{reset_halt} or @option{reset_init}.
459 @item @b{target_script} <@var{target#}> <@var{event}> <@var{script_file}>
460 @cindex target_script
461 Event is either @option{reset}, @option{post_halt}, @option{pre_resume} or @option{gdb_program_config}
463 TODO: describe exact semantic of events
464 @item @b{run_and_halt_time} <@var{target#}> <@var{time_in_ms}>
465 @cindex run_and_halt_time
466 The amount of time the debugger should wait after releasing reset before it asserts
467 a debug request. This is used by the @option{run_and_halt} and @option{run_and_init}
469 @item @b{working_area} <@var{target#}> <@var{address}> <@var{size}>
470 <@var{backup}|@var{nobackup}>
472 Specifies a working area for the debugger to use. This may be used to speed-up
473 downloads to target memory and flash operations, or to perform otherwise unavailable
474 operations (some coprocessor operations on ARM7/9 systems, for example). The last
475 parameter decides whether the memory should be preserved <@var{backup}>. If possible, use
476 a working_area that doesn't need to be backed up, as that slows down operation.
479 @subsection arm7tdmi options
480 @cindex arm7tdmi options
481 target arm7tdmi <@var{endianess}> <@var{reset_mode}> <@var{jtag#}>
482 The arm7tdmi target definition requires at least one additional argument, specifying
483 the position of the target in the JTAG daisy-chain. The first JTAG device is number 0.
484 The optional [@var{variant}] parameter has been removed in recent versions.
485 The correct feature set is determined at runtime.
487 @subsection arm720t options
488 @cindex arm720t options
489 ARM720t options are similar to ARM7TDMI options.
491 @subsection arm9tdmi options
492 @cindex arm9tdmi options
493 ARM9TDMI options are similar to ARM7TDMI options. Supported variants are
494 @option{arm920t}, @option{arm922t} and @option{arm940t}.
495 This enables the hardware single-stepping support found on these cores.
497 @subsection arm920t options
498 @cindex arm920t options
499 ARM920t options are similar to ARM9TDMI options.
501 @subsection arm966e options
502 @cindex arm966e options
503 ARM966e options are similar to ARM9TDMI options.
505 @subsection xscale options
506 @cindex xscale options
507 Supported variants are @option{ixp42x}, @option{ixp45x}, @option{ixp46x},
508 @option{pxa250}, @option{pxa255}, @option{pxa26x}.
510 @section Flash configuration
511 @cindex Flash configuration
514 @item @b{flash bank} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}>
515 <@var{bus_width}> <@var{target#}> [@var{driver_options ...}]
517 Configures a flash bank at <@var{base}> of <@var{size}> bytes and <@var{chip_width}>
518 and <@var{bus_width}> bytes using the selected flash <driver>.
520 @item @b{flash autoerase} <@option{on}|@option{off}>
521 @cindex flash autoerase
522 auto erase flash banks prior to writing. Currently only works when using
523 @option{flash write_image} command. Default is @option{off}.
526 @subsection lpc2000 options
527 @cindex lpc2000 options
529 @b{flash bank lpc2000} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
530 <@var{clock}> [@var{calc_checksum}]
531 LPC flashes don't require the chip and bus width to be specified. Additional
532 parameters are the <@var{variant}>, which may be @var{lpc2000_v1} (older LPC21xx and LPC22xx)
533 or @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx), the number
534 of the target this flash belongs to (first is 0), the frequency at which the core
535 is currently running (in kHz - must be an integral number), and the optional keyword
536 @var{calc_checksum}, telling the driver to calculate a valid checksum for the exception
539 @subsection cfi options
542 @b{flash bank cfi} <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}>
544 CFI flashes require the number of the target they're connected to as an additional
545 argument. The CFI driver makes use of a working area (specified for the target)
546 to significantly speed up operation.
548 @subsection at91sam7 options
549 @cindex at91sam7 options
551 @b{flash bank at91sam7} 0 0 0 0 <@var{target#>}>
552 AT91SAM7 flashes only require the target#, all other values are looked up after
553 reading the chip-id and type.
555 @subsection str7 options
558 @b{flash bank str7x} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
559 variant can be either STR71x, STR73x or STR75x.
561 @subsection str9 options
564 @b{flash bank str9x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
565 The str9 needs the flash controller to be configured prior to Flash programming, eg.
567 str9x flash_config 0 4 2 0 0x80000
569 This will setup the BBSR, NBBSR, BBADR and NBBADR registers respectively.
571 @subsection str9 options (str9xpec driver)
573 @b{flash bank str9xpec} <@var{base}> <@var{size}> 0 0 <@var{target#}>
574 Before using the flash commands the turbo mode will need enabling using str9xpec
575 @option{enable_turbo} <@var{num>.}
577 Only use this driver for locking/unlocking the device or configuring the option bytes.
578 Use the standard str9 driver for programming.
580 @subsection stellaris (LM3Sxxx) options
581 @cindex stellaris (LM3Sxxx) options
583 @b{flash bank stellaris} <@var{base}> <@var{size}> 0 0 <@var{target#}>
584 stellaris flash plugin only require the target#.
586 @subsection stm32x options
587 @cindex stm32x options
589 @b{flash bank stm32x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
590 stm32x flash plugin only require the target#.
596 The Open On-Chip Debugger (OpenOCD) allows user interaction through a telnet interface
597 (default: port 4444) and a GDB server (default: port 3333). The command line interpreter
598 is available from both the telnet interface and a GDB session. To issue commands to the
599 interpreter from within a GDB session, use the @option{monitor} command, e.g. use
600 @option{monitor poll} to issue the @option{poll} command. All output is relayed through the
606 @item @b{sleep} <@var{msec}>
608 Wait for n milliseconds before resuming. Useful in connection with script files
609 (@var{script} command and @var{target_script} configuration).
613 Close the OpenOCD daemon, disconnecting all clients (GDB, Telnet).
615 @item @b{debug_level} [@var{n}]
617 Display or adjust debug level to n<0-3>
619 @item @b{log_output} <@var{file}>
621 Redirect logging to <file> (default: stderr)
623 @item @b{script} <@var{file}>
625 Execute commands from <file>
629 @subsection Target state handling
631 @item @b{poll} [@option{on}|@option{off}]
633 Poll the target for its current state. If the target is in debug mode, architecture
634 specific information about the current state are printed. An optional parameter
635 allows continuous polling to be enabled and disabled.
639 Send a halt request to the target. The debugger signals the debug request,
640 and waits for the target to enter debug mode.
642 @item @b{resume} [@var{address}]
644 Resume the target at its current code position, or at an optional address.
646 @item @b{step} [@var{address}]
648 Single-step the target at its current code position, or at an optional address.
650 @item @b{reset} [@option{run}|@option{halt}|@option{init}|@option{run_and_halt}
651 |@option{run_and_init}]
653 Do a hard-reset. The optional parameter specifies what should happen after the reset.
654 This optional parameter overwrites the setting specified in the configuration file,
655 making the new behaviour the default for the @option{reset} command.
662 Immediately halt the target (works only with certain configurations).
665 Immediately halt the target, and execute the reset script (works only with certain
668 @cindex reset run_and_halt
669 Let the target run for a certain amount of time, then request a halt.
671 @cindex reset run_and_init
672 Let the target run for a certain amount of time, then request a halt. Execute the
673 reset script once the target entered debug mode.
677 @subsection Memory access commands
678 These commands allow accesses of a specific size to the memory system:
680 @item @b{mdw} <@var{addr}> [@var{count}]
683 @item @b{mdh} <@var{addr}> [@var{count}]
685 display memory half-words
686 @item @b{mdb} <@var{addr}> [@var{count}]
689 @item @b{mww} <@var{addr}> <@var{value}>
692 @item @b{mwh} <@var{addr}> <@var{value}>
694 write memory half-word
695 @item @b{mwb} <@var{addr}> <@var{value}>
699 @item @b{load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
701 Load image <@var{file}> to target memory at <@var{address}>
702 @item @b{dump_image} <@var{file}> <@var{address}> <@var{size}>
704 Dump <@var{size}> bytes of target memory starting at <@var{address}> to a
705 (binary) <@var{file}>.
706 @item @b{verify_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
708 Verify <@var{file}> to target memory starting at <@var{address}>.
709 This will first attempt using a crc checksum, if this fails it will try a binary compare.
710 @item @b{load_binary} <@var{file}> <@var{address}> [DEPRECATED]
712 Load binary <@var{file}> to target memory at <@var{address}>
713 @item @b{dump_binary} <@var{file}> <@var{address}> <@var{size}> [DEPRECATED]
715 Dump <@var{size}> bytes of target memory starting at <@var{address}> to a
716 (binary) <@var{file}>.
719 @subsection Flash commands
720 @cindex Flash commands
722 @item @b{flash banks}
724 List configured flash banks
725 @item @b{flash info} <@var{num}>
727 Print info about flash bank <@option{num}>
728 @item @b{flash probe} <@var{num}>
730 Identify the flash, or validate the parameters of the configured flash. Operation
731 depends on the flash type.
732 @item @b{flash erase_check} <@var{num}>
733 @cindex flash erase_check
734 Check erase state of sectors in flash bank <@var{num}>. This is the only operation that
735 updates the erase state information displayed by @option{flash info}. That means you have
736 to issue an @option{erase_check} command after erasing or programming the device to get
738 @item @b{flash protect_check} <@var{num}>
739 @cindex flash protect_check
740 Check protection state of sectors in flash bank <num>.
742 @item @b{flash erase} <@var{num}> <@var{first}> <@var{last}> [DEPRECATED]
744 Erase sectors at bank <@var{num}>, starting at sector <@var{first}> up to and including
745 <@var{last}>. Sector numbering starts at 0. Depending on the flash type, erasing might
746 require the protection to be disabled first (e.g. Intel Advanced Bootblock flash using
747 the CFI driver). This command was replaced by the new command
748 @option{flash erase_sector} using the same syntax.
749 @item @b{flash erase_sector} <@var{num}> <@var{first}> <@var{last}>
750 @cindex flash erase_sector
751 Erase sectors at bank <@var{num}>, starting at sector <@var{first}> up to and including
752 <@var{last}>. Sector numbering starts at 0. Depending on the flash type, erasing might
753 require the protection to be disabled first (e.g. Intel Advanced Bootblock flash using
755 @item @b{flash erase_address} <@var{address}> <@var{length}>
756 @cindex flash erase_address
757 Erase sectors starting at <@var{address}> for <@var{length}> number of bytes
758 @item @b{flash write} <@var{num}> <@var{file}> <@var{offset}> [DEPRECATED]
760 Write the binary <@var{file}> to flash bank <@var{num}>, starting at <@var{offset}>
761 bytes from the beginning of the bank. This command was replaced by the new command
762 @option{flash write_binary} using the same syntax.
763 @item @b{flash write_binary} <@var{num}> <@var{file}> <@var{offset}>
764 @cindex flash write_binary
765 Write the binary <@var{file}> to flash bank <@var{num}>, starting at
766 <@option{offset}> bytes from the beginning of the bank.
767 @item @b{flash write_image} <@var{file}> [@var{offset}] [@var{type}]
768 @cindex flash write_image
769 Write the image <@var{file}> to the current target's flash bank(s). A relocation
770 [@var{offset}] can be specified and the file [@var{type}] can be specified
771 explicitly as @option{bin} (binary), @option{ihex} (Intel hex), @option{elf}
772 (ELF file) or @option{s19} (Motorola s19).
773 @item @b{flash protect} <@var{num}> <@var{first}> <@var{last}> <@option{on}|@option{off}>
774 @cindex flash protect
775 Enable (@var{on}) or disable (@var{off}) protection of flash sectors <@var{first}> to
776 <@var{last}> of @option{flash bank} <@var{num}>.
777 @item @b{flash auto_erase} <@var{on}|@var{off}>
778 @cindex flash auto_erase
779 Enable (@option{on}) to erase flash banks prior to writing using the flash @option{write_image} command
780 only. Default is (@option{off}), flash banks have to be erased using @option{flash erase} command.
784 @section Target Specific Commands
785 @cindex Target Specific Commands
787 @subsection AT91SAM7 specific commands
788 @cindex AT91SAM7 specific commands
789 The flash configuration is deduced from the chip identification register. The flash
790 controller handles erases automatically on a page (128/265 byte) basis so erase is
791 not necessary for flash programming. AT91SAM7 processors with less than 512K flash
792 only have a single flash bank embedded on chip. AT91SAM7xx512 have two flash planes
793 that can be erased separatly.Only an EraseAll command is supported by the controller
794 for each flash plane and this is called with
796 @item @b{flash erase} <@var{num}> @var{first_plane} @var{last_plane}
797 bulk erase flash planes first_plane to last_plane.
798 @item @b{at91sam7 gpnvm} <@var{num}> <@var{bit}> <@option{set}|@option{clear}>
799 @cindex at91sam7 gpnvm
800 set or clear a gpnvm bit for the processor
803 @subsection STR9 specific commands
804 @cindex STR9 specific commands
805 These are flash specific commands when using the str9xpec driver.
807 @item @b{str9xpec enable_turbo} <@var{num}>
808 @cindex str9xpec enable_turbo
809 enable turbo mode, simply this will remove the str9 from the chain and talk
810 directly to the embedded flash controller.
811 @item @b{str9xpec disable_turbo} <@var{num}>
812 @cindex str9xpec disable_turbo
813 restore the str9 into jtag chain.
814 @item @b{str9xpec lock} <@var{num}>
815 @cindex str9xpec lock
816 lock str9 device. The str9 will only respond to an unlock command that will
818 @item @b{str9xpec unlock} <@var{num}>
819 @cindex str9xpec unlock
821 @item @b{str9xpec options_read} <@var{num}>
822 @cindex str9xpec options_read
823 read str9 option bytes.
824 @item @b{str9xpec options_write} <@var{num}>
825 @cindex str9xpec options_write
826 write str9 option bytes.
829 @subsection STR9 configuration
830 @cindex STR9 configuration
832 @item @b{str9x flash_config} <@var{bank}> <@var{BBSR}> <@var{NBBSR}>
833 <@var{BBADR}> <@var{NBBADR}>
834 @cindex str9x flash_config
835 Configure str9 flash controller.
837 eg. str9x flash_config 0 4 2 0 0x80000
839 BBSR - Boot Bank Size register
840 NBBSR - Non Boot Bank Size register
841 BBADR - Boot Bank Start Address register
842 NBBADR - Boot Bank Start Address register
846 @subsection STR9 option byte configuration
847 @cindex STR9 option byte configuration
849 @item @b{str9xpec options_cmap} <@var{num}> <@option{bank0}|@option{bank1}>
850 @cindex str9xpec options_cmap
851 configure str9 boot bank.
852 @item @b{str9xpec options_lvdthd} <@var{num}> <@option{2.4v}|@option{2.7v}>
853 @cindex str9xpec options_lvdthd
854 configure str9 lvd threshold.
855 @item @b{str9xpec options_lvdsel} <@var{num}> <@option{vdd}|@option{vdd_vddq}>
856 @cindex str9xpec options_lvdsel
857 configure str9 lvd source.
858 @item @b{str9xpec options_lvdwarn} <@var{bank}> <@option{vdd}|@option{vdd_vddq}>
859 @cindex str9xpec options_lvdwarn
860 configure str9 lvd reset warning source.
863 @subsection STM32x specific commands
864 @cindex STM32x specific commands
866 These are flash specific commands when using the stm32x driver.
868 @item @b{stm32x lock} <@var{num}>
871 @item @b{stm32x unlock} <@var{num}>
872 @cindex stm32x unlock
874 @item @b{stm32x options_read} <@var{num}>
875 @cindex stm32x options_read
876 read stm32 option bytes.
877 @item @b{stm32x options_write} <@var{num}> <@option{SWWDG}|@option{HWWDG}>
878 <@option{RSTSTNDBY}|@option{NORSTSTNDBY}> <@option{RSTSTOP}|@option{NORSTSTOP}>
879 @cindex stm32x options_write
880 write stm32 option bytes.
881 @item @b{stm32x mass_erase} <@var{num}>
882 @cindex stm32x mass_erase
883 mass erase flash memory.
887 @section Architecture Specific Commands
888 @cindex Architecture Specific Commands
890 @subsection ARMV4/5 specific commands
891 @cindex ARMV4/5 specific commands
893 These commands are specific to ARM architecture v4 and v5, like all ARM7/9 systems
894 or Intel XScale (XScale isn't supported yet).
896 @item @b{armv4_5 reg}
898 Display a list of all banked core registers, fetching the current value from every
899 core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
901 @item @b{armv4_5 core_mode} [@option{arm}|@option{thumb}]
902 @cindex armv4_5 core_mode
903 Displays the core_mode, optionally changing it to either ARM or Thumb mode.
904 The target is resumed in the currently set @option{core_mode}.
907 @subsection ARM7/9 specific commands
908 @cindex ARM7/9 specific commands
910 These commands are specific to ARM7 and ARM9 targets, like ARM7TDMI, ARM720t,
911 ARM920t or ARM926EJ-S.
913 @item @b{arm7_9 sw_bkpts} <@option{enable}|@option{disable}>
914 @cindex arm7_9 sw_bkpts
915 Enable/disable use of software breakpoints. On ARMv4 systems, this reserves
916 one of the watchpoint registers to implement software breakpoints. Disabling
917 SW Bkpts frees that register again.
918 @item @b{arm7_9 force_hw_bkpts} <@option{enable}|@option{disable}>
919 @cindex arm7_9 force_hw_bkpts
920 When @option{force_hw_bkpts} is enabled, the @option{sw_bkpts} support is disabled, and all
921 breakpoints are turned into hardware breakpoints.
922 @item @b{arm7_9 dbgrq} <@option{enable}|@option{disable}>
924 Enable use of the DBGRQ bit to force entry into debug mode. This should be
925 safe for all but ARM7TDMI--S cores (like Philips LPC).
926 @item @b{arm7_9 fast_writes} <@option{enable}|@option{disable}>
927 @cindex arm7_9 fast_writes [DEPRECATED]
928 See @option{arm7_9 fast_memory_access} instead.
929 @item @b{arm7_9 fast_memory_access} <@option{enable}|@option{disable}>
930 @cindex arm7_9 fast_memory_access
931 Allow the OpenOCD to read and write memory without checking completion of
932 the operation. This provides a huge speed increase, especially with USB JTAG
933 cables (FT2232), but might be unsafe if used with targets running at a very low
934 speed, like the 32kHz startup clock of an AT91RM9200.
935 @item @b{arm7_9 dcc_downloads} <@option{enable}|@option{disable}>
936 @cindex arm7_9 dcc_downloads
937 Enable the use of the debug communications channel (DCC) to write larger (>128 byte)
938 amounts of memory. DCC downloads offer a huge speed increase, but might be potentially
939 unsafe, especially with targets running at a very low speed. This command was introduced
940 with OpenOCD rev. 60.
943 @subsection ARM920T specific commands
944 @cindex ARM920T specific commands
947 @item @b{arm920t cache_info}
948 @cindex arm920t cache_info
949 Print information about the caches found. This allows you to see if your target
950 is a ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
951 @item @b{arm920t md<bhw>_phys} <@var{addr}> [@var{count}]
952 @cindex arm920t md<bhw>_phys
953 Display memory at physical address addr.
954 @item @b{arm920t mw<bhw>_phys} <@var{addr}> <@var{value}>
955 @cindex arm920t mw<bhw>_phys
956 Write memory at physical address addr.
957 @item @b{arm920t read_cache} <@var{filename}>
958 @cindex arm920t read_cache
959 Dump the content of ICache and DCache to a file.
960 @item @b{arm920t read_mmu} <@var{filename}>
961 @cindex arm920t read_mmu
962 Dump the content of the ITLB and DTLB to a file.
963 @item @b{arm920t virt2phys} <@var{VA}>
964 @cindex arm920t virt2phys
965 Translate a virtual address to a physical address.
969 @section Debug commands
970 @cindex Debug commands
971 The following commands give direct access to the core, and are most likely
972 only useful while debugging the OpenOCD.
974 @item @b{arm7_9 write_xpsr} <@var{32-bit value}> <@option{0=cpsr}, @option{1=spsr}>
975 @cindex arm7_9 write_xpsr
976 Immediately write either the current program status register (CPSR) or the saved
977 program status register (SPSR), without changing the register cache (as displayed
978 by the @option{reg} and @option{armv4_5 reg} commands).
979 @item @b{arm7_9 write_xpsr_im8} <@var{8-bit value}> <@var{rotate 4-bit}>
980 <@var{0=cpsr},@var{1=spsr}>
981 @cindex arm7_9 write_xpsr_im8
982 Write the 8-bit value rotated right by 2*rotate bits, using an immediate write
983 operation (similar to @option{write_xpsr}).
984 @item @b{arm7_9 write_core_reg} <@var{num}> <@var{mode}> <@var{value}>
985 @cindex arm7_9 write_core_reg
986 Write a core register, without changing the register cache (as displayed by the
987 @option{reg} and @option{armv4_5 reg} commands). The <@var{mode}> argument takes the
988 encoding of the [M4:M0] bits of the PSR.
992 @section JTAG commands
993 @cindex JTAG commands
997 Print current scan chain configuration.
1000 Toggle reset lines <@var{trst}> <@var{srst}>.
1001 @item @b{endstate} <@var{tap_state}>
1003 Finish JTAG operations in <@var{tap_state}>.
1004 @item @b{runtest} <@var{num_cycles}>
1006 Move to Run-Test/Idle, and execute <@var{num_cycles}>
1007 @item @b{statemove} [@var{tap_state}]
1009 Move to current endstate or [@var{tap_state}]
1012 Execute IR scan <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
1015 Execute DR scan <@var{device}> [@var{dev2}] [@var{var2}] ...
1016 @item @b{verify_ircapture}
1017 @cindex verify_ircapture
1018 Verify value captured during Capture-IR <@option{enable}|@option{disable}>
1021 Allocate, display or delete variable <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
1024 Display/modify variable field <@var{var}> <@var{field}> [@var{value}|@var{flip}]
1027 @node Sample Scripts
1028 @chapter Sample Scripts
1031 This page will collect some script examples for different CPUs.
1033 The configuration script can be divided in the following section:
1035 @item daemon configuration
1037 @item jtag scan chain
1038 @item target configuration
1039 @item flash configuration
1042 Detailed information about each section can be found at OpenOCD configuration
1044 @section OMAP5912 Flash Debug
1045 @cindex OMAP5912 Flash Debug
1046 The following two scripts were used with a wiggler PP and and a TI OMAP5912
1047 dual core processor - (@uref{http://www.ti.com}), on a OMAP5912 OSK board
1048 - (@uref{http://www.spectrumdigital.com}).
1049 @subsection Openocd config
1051 #daemon configuration
1058 parport_cable wiggler
1061 #use combined on interfaces or targets that can't set TRST/SRST separately
1062 reset_config trst_and_srst
1065 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1066 jtag_device 38 0x0 0x0 0x0
1067 jtag_device 4 0x1 0x0 0xe
1068 jtag_device 8 0x0 0x0 0x0
1070 #target configuration
1071 daemon_startup reset
1073 #target <type> <endianness> <reset mode> <chainpos> <variant>
1074 target arm926ejs little run_and_init 1 arm926ejs
1075 target_script 0 reset omap5912_osk.init
1076 run_and_halt_time 0 30
1078 # omap5912 lcd frame buffer as working area
1079 working_area 0 0x20000000 0x3e800 nobackup
1081 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1082 flash bank cfi 0x00000000 0x1000000 2 2 0
1085 @subsection Openocd init
1097 mww 0xfffec808 0x000000f5
1098 mww 0xfffec808 0x000000a0
1100 mww 0xfffeb048 0x0000aaaa
1102 mww 0xfffeb048 0x00005555
1111 @section STR71x Script
1112 @cindex STR71x Script
1113 The following script was used with an Amontec JTAGkey and a STR710 / STR711 cpu:
1115 #daemon configuration
1121 ft2232_device_desc "Amontec JTAGkey A"
1122 ft2232_layout jtagkey
1123 ft2232_vid_pid 0x0403 0xcff8
1126 #use combined on interfaces or targets that can't set TRST/SRST separately
1127 reset_config trst_and_srst srst_pulls_trst
1130 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1131 jtag_device 4 0x1 0xf 0xe
1133 #target configuration
1134 daemon_startup reset
1136 #target <type> <startup mode>
1137 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1138 target arm7tdmi little run_and_halt 0 arm7tdmi
1139 run_and_halt_time 0 30
1141 working_area 0 0x2000C000 0x4000 nobackup
1143 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1144 flash bank str7x 0x40000000 0x00040000 0 0 0 STR71x
1147 @section STR750 Script
1148 @cindex STR750 Script
1149 The following script was used with an Amontec JTAGkey and a STR750 cpu:
1151 #daemon configuration
1157 ft2232_device_desc "Amontec JTAGkey A"
1158 ft2232_layout jtagkey
1159 ft2232_vid_pid 0x0403 0xcff8
1162 #use combined on interfaces or targets that can't set TRST/SRST separately
1163 #reset_config trst_and_srst srst_pulls_trst
1164 reset_config trst_and_srst srst_pulls_trst
1167 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1168 jtag_device 4 0x1 0xf 0xe
1170 #jtag nTRST and nSRST delay
1171 jtag_nsrst_delay 500
1172 jtag_ntrst_delay 500
1174 #target configuration
1175 daemon_startup reset
1177 #target <type> <startup mode>
1178 #target arm7tdmi <reset mode> <chainpos> <endianness> <variant>
1179 target arm7tdmi little run_and_halt 0 arm7tdmi
1180 run_and_halt_time 0 30
1182 working_area 0 0x40000000 0x4000 nobackup
1184 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1185 flash bank str7x 0x20000000 0x000040000 0 0 0 STR75x
1188 @section STR912 Script
1189 @cindex STR912 Script
1190 The following script was used with an Amontec JTAGkey and a STR912 cpu:
1192 #daemon configuration
1198 ft2232_device_desc "Amontec JTAGkey A"
1199 ft2232_layout jtagkey
1202 #use combined on interfaces or targets that can't set TRST/SRST separately
1203 reset_config trst_and_srst
1206 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1207 jtag_device 8 0x1 0x1 0xfe
1208 jtag_device 4 0x1 0xf 0xe
1209 jtag_device 5 0x1 0x1 0x1e
1211 #target configuration
1212 daemon_startup reset
1214 #target <type> <startup mode>
1215 #target arm966e <endianness> <reset mode> <chainpos> <variant>
1216 target arm966e little reset_halt 1 arm966e
1217 run_and_halt_time 0 30
1219 working_area 0 0x50000000 16384 nobackup
1221 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1222 flash bank str9x 0x00000000 0x00080000 0 0 0
1225 @section STR912 comstick
1226 @cindex STR912 comstick Script
1227 The following script was used with a Hitex STR9 Comstick:
1229 #daemon configuration
1235 ft2232_device_desc "STR9-comStick A"
1236 ft2232_layout comstick
1239 jtag_nsrst_delay 100
1240 jtag_ntrst_delay 100
1242 #use combined on interfaces or targets that can't set TRST/SRST separately
1243 reset_config trst_and_srst
1246 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1247 jtag_device 8 0x1 0x1 0xfe
1248 jtag_device 4 0x1 0xf 0xe
1249 jtag_device 5 0x1 0x1 0x1e
1251 #target configuration
1252 daemon_startup reset
1254 #target <type> <startup mode>
1255 #target arm966e <endianness> <reset mode> <chainpos> <variant>
1256 target arm966e little reset_halt 1 arm966e
1257 run_and_halt_time 0 30
1259 working_area 0 0x50000000 16384 nobackup
1261 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1262 flash bank str9x 0x00000000 0x00080000 0 0 0
1265 @section STM32x Script
1266 @cindex STM32x Script
1267 The following script was used with an Amontec JTAGkey and a STM32x cpu:
1269 #daemon configuration
1275 ft2232_device_desc "Amontec JTAGkey A"
1276 ft2232_layout jtagkey
1279 jtag_nsrst_delay 100
1280 jtag_ntrst_delay 100
1282 #use combined on interfaces or targets that can't set TRST/SRST separately
1283 reset_config trst_and_srst
1286 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1287 jtag_device 4 0x1 0xf 0xe
1288 jtag_device 5 0x1 0x1 0x1e
1290 #target configuration
1291 daemon_startup reset
1293 #target <type> <startup mode>
1294 #target cortex_m3 <endianness> <reset mode> <chainpos> <variant>
1295 target cortex_m3 little run_and_halt 0
1296 run_and_halt_time 0 30
1298 working_area 0 0x20000000 16384 nobackup
1300 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1301 flash bank stm32x 0x08000000 0x00020000 0 0 0
1304 @section STM32x Performance Stick
1305 @cindex STM32x Performance Stick Script
1306 The following script was used with the Hitex STM32 Performance Stick
1308 #daemon configuration
1314 ft2232_device_desc "STM32-PerformanceStick A"
1315 ft2232_layout stm32stick
1318 jtag_nsrst_delay 100
1319 jtag_ntrst_delay 100
1321 #use combined on interfaces or targets that can't set TRST/SRST separately
1322 reset_config trst_and_srst
1325 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1326 jtag_device 4 0x1 0xf 0xe
1327 jtag_device 5 0x1 0x1 0x1e
1328 jtag_device 4 0x1 0xf 0xe
1330 #target configuration
1331 daemon_startup reset
1333 #target <type> <startup mode>
1334 #target cortex_m3 <endianness> <reset mode> <chainpos> <variant>
1335 target cortex_m3 little run_and_halt 0
1336 run_and_halt_time 0 30
1338 working_area 0 0x20000000 16384 nobackup
1340 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1341 flash bank stm32x 0x08000000 0x00020000 0 0 0
1344 @section LPC2129 Script
1345 @cindex LPC2129 Script
1346 The following script was used with an wiggler PP and a LPC-2129 cpu:
1348 #daemon configuration
1355 parport_cable wiggler
1358 #use combined on interfaces or targets that can't set TRST/SRST separately
1359 reset_config trst_and_srst srst_pulls_trst
1362 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1363 jtag_device 4 0x1 0xf 0xe
1365 #target configuration
1366 daemon_startup reset
1368 #target <type> <startup mode>
1369 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1370 target arm7tdmi little run_and_halt 0 arm7tdmi-s_r4
1371 run_and_halt_time 0 30
1373 working_area 0 0x40000000 0x4000 nobackup
1375 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1376 flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14765 calc_checksum
1379 @section LPC2148 Script
1380 @cindex LPC2148 Script
1381 The following script was used with an Amontec JTAGkey and a LPC2148 cpu:
1383 #daemon configuration
1389 ft2232_device_desc "Amontec JTAGkey A"
1390 ft2232_layout jtagkey
1391 ft2232_vid_pid 0x0403 0xcff8
1394 #use combined on interfaces or targets that can't set TRST/SRST separately
1395 reset_config trst_and_srst srst_pulls_trst
1398 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1399 jtag_device 4 0x1 0xf 0xe
1401 #target configuration
1402 daemon_startup reset
1404 #target <type> <startup mode>
1405 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1406 target arm7tdmi little run_and_halt 0 arm7tdmi-s_r4
1407 run_and_halt_time 0 30
1409 working_area 0 0x40000000 0x8000 nobackup
1411 #flash configuration
1412 flash bank lpc2000 0x0 0x7d000 0 0 0 lpc2000_v1 14765 calc_checksum
1415 @section LPC2294 Script
1416 @cindex LPC2294 Script
1417 The following script was used with an Amontec JTAGkey and a LPC2294 cpu:
1419 #daemon configuration
1425 ft2232_device_desc "Amontec JTAGkey A"
1426 ft2232_layout jtagkey
1427 ft2232_vid_pid 0x0403 0xcff8
1430 #use combined on interfaces or targets that can't set TRST/SRST separately
1431 reset_config trst_and_srst srst_pulls_trst
1434 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1435 jtag_device 4 0x1 0xf 0xe
1437 #target configuration
1438 daemon_startup reset
1440 #target <type> <startup mode>
1441 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1442 target arm7tdmi little run_and_halt 0 arm7tdmi-s_r4
1443 run_and_halt_time 0 30
1445 working_area 0 0x40000000 0x4000 nobackup
1447 #flash configuration
1448 flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14765 calc_checksum
1451 @section AT91R40008 Script
1452 @cindex AT91R40008 Script
1453 The following script was used with an Amontec JTAGkey and a AT91R40008 cpu:
1455 #daemon configuration
1461 ft2232_device_desc "Amontec JTAGkey A"
1462 ft2232_layout jtagkey
1463 ft2232_vid_pid 0x0403 0xcff8
1465 jtag_nsrst_delay 200
1466 jtag_ntrst_delay 200
1468 #use combined on interfaces or targets that can't set TRST/SRST separately
1469 reset_config srst_only srst_pulls_trst
1472 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1473 jtag_device 4 0x1 0xf 0xe
1475 #target configuration
1476 daemon_startup reset
1478 #target <type> <startup mode>
1479 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1480 target arm7tdmi little run_and_halt 0 arm7tdmi
1481 run_and_halt_time 0 30
1484 @section AT91SAM7s Script
1485 @cindex AT91SAM7s Script
1486 The following script was used with an Olimex ARM-JTAG-OCD and a AT91SAM7S64 cpu:
1488 #daemon configuration
1494 ft2232_device_desc "Olimex OpenOCD JTAG A"
1495 ft2232_layout olimex-jtag
1496 ft2232_vid_pid 0x15BA 0x0003
1498 jtag_nsrst_delay 200
1499 jtag_ntrst_delay 200
1501 #use combined on interfaces or targets that can't set TRST/SRST separately
1502 reset_config srst_only srst_pulls_trst
1505 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1506 jtag_device 4 0x1 0xf 0xe
1508 #target configuration
1509 daemon_startup reset
1511 #target <type> <startup mode>
1512 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1513 target arm7tdmi little run_and_halt 0 arm7tdmi
1514 run_and_halt_time 0 30
1516 # flash-options AT91
1517 working_area 0 0x00200000 0x4000 nobackup
1518 flash bank at91sam7 0 0 0 0 0
1521 # erase command (telnet-interface) for complete flash:
1522 # flash erase <num> 0 numlockbits-1 (can be seen from output of flash info 0)
1523 # SAM7S64 with 16 lockbits and bank 0: flash erase 0 0 15
1524 # set/clear NVM-Bits:
1525 # at91sam7 gpnvm <num> <bit> <set|clear>
1526 # disable locking from SAM-BA:
1527 # flash protect 0 0 1 off
1530 @section XSCALE IXP42x Script
1531 @cindex XSCALE IXP42x Script
1532 The following script was used with an Amontec JTAGkey-Tiny and a xscale ixp42x cpu:
1534 #daemon configuration
1540 ft2232_device_desc "Amontec JTAGkey A"
1541 ft2232_layout jtagkey
1542 ft2232_vid_pid 0x0403 0xcff8
1544 jtag_nsrst_delay 200
1545 jtag_ntrst_delay 200
1547 #use combined on interfaces or targets that can't set TRST/SRST separately
1548 reset_config srst_only srst_pulls_trst
1551 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1552 jtag_device 7 0x1 0x7f 0x7e
1554 #target configuration
1555 daemon_startup reset
1557 #target <type> <startup mode>
1558 #target arm7tdmi <reset mode> <chainpos> <endianness> <variant>
1559 target xscale big run_and_halt 0 IXP42x
1560 run_and_halt_time 0 30
1563 @section Cirrus Logic EP9301 Script
1564 @cindex Cirrus Logic EP9301 Script
1565 The following script was used with FT2232 based JTAG interfaces and a
1566 Cirrus Logic EP9301 processor on an Olimex CS-E9301 board.
1568 #daemon configuration
1576 #ft2232_device_desc "Olimex OpenOCD JTAG"
1577 #ft2232_layout olimex-jtag
1578 #ft2232_vid_pid 0x15ba 0x0003
1580 #Amontec JTAGkey (and JTAGkey-Tiny)
1581 #Serial is only necessary if more than one JTAGkey is connected
1582 ft2232_device_desc "Amontec JTAGkey A"
1583 #ft2232_serial AMTJKV31
1584 #ft2232_serial T1P3S2W8
1585 ft2232_layout jtagkey
1586 ft2232_vid_pid 0x0403 0xcff8
1588 #wiggler/parallel port interface
1591 #parport_cable wiggler
1594 reset_config trst_and_srst
1597 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1598 jtag_device 4 0x1 0xf 0xe
1600 jtag_nsrst_delay 100
1601 jtag_ntrst_delay 100
1603 #target configuration
1604 daemon_startup attach
1606 #target <type> <endianess> <reset mode>
1607 target arm920t little reset_halt 0
1608 working_area 0 0x80014000 0x1000 backup
1610 #flash configuration
1611 #flash bank <driver> <base> <size> <chip_width> <bus_width> [driver_options ...]
1612 flash bank cfi 0x60000000 0x1000000 2 2 0
1615 @section Hilscher netX 100 / 500 Script
1616 @cindex Hilscher netX 100 / 500 Script
1617 The following script was used with an Amontec JTAGkey and a Hilscher
1620 #daemon configuration
1626 ft2232_device_desc "Amontec JTAGkey A"
1627 ft2232_layout jtagkey
1628 ft2232_vid_pid 0x0403 0xcff8
1631 #use combined on interfaces or targets that can't set TRST/SRST separately
1632 reset_config trst_and_srst
1635 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1636 jtag_device 4 0x1 0xf 0xe
1638 jtag_nsrst_delay 100
1639 jtag_ntrst_delay 100
1641 #target configuration
1642 daemon_startup reset
1644 #target <type> <endianness> <startup mode> <chainpos> <variant>
1645 target arm926ejs little run_and_halt 0 arm926ejs
1646 run_and_halt_time 0 500
1649 @section Marvell/Intel PXA270 Script
1650 @cindex Marvell/Intel PXA270 Script
1652 # config for Intel PXA270
1653 # not, as of 2007-06-22, openocd only works with the
1654 # libftd2xx library from ftdi. libftdi does not work.
1660 ft2232_layout olimex-jtag
1661 ft2232_vid_pid 0x15BA 0x0003
1662 ft2232_device_desc "Olimex OpenOCD JTAG"
1664 # set jtag_nsrst_delay to the delay introduced by your reset circuit
1665 # the rest of the needed delays are built into the openocd program
1666 jtag_nsrst_delay 260
1667 # set the jtag_ntrst_delay to the delay introduced by a reset circuit
1668 # the rest of the needed delays are built into the openocd program
1671 #use combined on interfaces or targets that can't set TRST/SRST separately
1672 reset_config trst_and_srst separate
1675 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1676 jtag_device 7 0x1 0x7f 0x7e
1678 #target configuration
1679 daemon_startup reset
1681 target xscale little reset_halt 0 pxa27x
1683 # maps to PXA internal RAM. If you are using a PXA255
1684 # you must initialize SDRAM or leave this option off
1685 working_area 0 0x5c000000 0x10000 nobackup
1687 run_and_halt_time 0 30
1689 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1690 # works for P30 flash
1691 flash bank cfi 0x00000000 0x1000000 2 4 0
1694 @node GDB and Openocd
1695 @chapter GDB and Openocd
1696 @cindex GDB and Openocd
1697 Openocd complies with the remote gdbserver protocol, and as such can be used
1698 to debug remote targets.
1700 @section Connecting to gdb
1701 @cindex Connecting to gdb
1702 A connection is typically started as follows:
1704 target remote localhost:3333
1706 This would cause gdb to connect to the gdbserver on the local pc using port 3333.
1708 To see a list of available openocd commands type @option{monitor help} on the
1711 Openocd supports the gdb @option{qSupported} packet, this enables information
1712 to be sent by the gdb server (openocd) to gdb. Typical information includes
1713 packet size and device memory map.
1715 Previous versions of openocd required the following gdb options to increase
1716 the packet size and speed up gdb communication.
1718 set remote memory-write-packet-size 1024
1719 set remote memory-write-packet-size fixed
1720 set remote memory-read-packet-size 1024
1721 set remote memory-read-packet-size fixed
1723 This is now handled in the @option{qSupported} PacketSize.
1725 @section Programming using gdb
1726 @cindex Programming using gdb
1728 By default the target memory map is not sent to gdb, this can be enabled by
1729 the following openocd config option:
1731 gdb_memory_map enable
1733 For this to function correctly a valid flash config must also be configured
1734 in openocd. For speed also configure a valid working area.
1736 Informing gdb of the memory map of the target will enable gdb to protect any
1737 flash area of the target and use hardware breakpoints by default. This means
1738 that the openocd option @option{arm7_9 force_hw_bkpts} is not required when
1741 To view the configured memory map in gdb, use the gdb command @option{info mem}
1742 All other unasigned addresses within gdb are treated as ram.
1744 If @option{gdb_flash_program enable} is also used, gdb will be able to
1745 program any flash memory using the vFlash interface.
1747 gdb will look at the target memory map when a load command is given, if any
1748 areas to be programmed lie within the target flash area the vFlash packets
1751 Incase the target needs configuring before gdb programming, a script can be executed.
1753 target_script 0 gdb_program_config config.script
1756 To verify any flash programming the gdb command @option{compare-sections}
1763 @item OpenOCD complains about a missing cygwin1.dll
1765 Make sure you have Cygwin installed, or at least a version of OpenOCD that
1766 claims to come with all the necessary dlls. When using Cygwin, try launching
1767 the OpenOCD from the Cygwin shell.
1769 @item I'm trying to set a breakpoint using GDB (or a frontend like Insight or
1770 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
1771 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
1773 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
1774 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720t or ARM920t,
1775 software breakpoints consume one of the two available hardware breakpoints,
1776 and are therefor disabled by default. If your code is running from RAM, you
1777 can enable software breakpoints with the @option{arm7_9 sw_bkpts enable} command. If
1778 your code resides in Flash, you can't use software breakpoints, but you can force
1779 OpenOCD to use hardware breakpoints instead: @option{arm7_9 force_hw_bkpts enable}.
1781 @item When erasing or writing LPC2000 on-chip flash, the operation fails sometimes
1782 and works sometimes fine.
1784 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
1785 clock at the time you're programming the flash. If you've specified the crystal's
1786 frequency, make sure the PLL is disabled, if you've specified the full core speed
1787 (e.g. 60MHz), make sure the PLL is enabled.
1789 @item When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
1790 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
1791 out while waiting for end of scan, rtck was disabled".
1793 Make sure your PC's parallel port operates in EPP mode. You might have to try several
1794 settings in your PC Bios (ECP, EPP, and different versions of those).
1796 @item When debugging with the OpenOCD and GDB (plain GDB, Insight, or Eclipse),
1797 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
1798 memory read caused data abort".
1800 The errors are non-fatal, and are the result of GDB trying to trace stack frames
1801 beyond the last valid frame. It might be possible to prevent this by setting up
1802 a proper "initial" stack frame, if you happen to know what exactly has to
1803 be done, feel free to add this here.
1805 @item I get the following message in the OpenOCD console (or log file):
1806 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
1808 This warning doesn't indicate any serious problem, as long as you don't want to
1809 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
1810 trst_and_srst srst_pulls_trst} to tell the OpenOCD that either your board,
1811 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
1812 independently. With this setup, it's not possible to halt the core right out of
1813 reset, everything else should work fine.
1815 @item When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
1816 Toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
1817 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
1818 quit with an error message. Is there a stability issue with OpenOCD?
1820 No, this is not a stability issue concering OpenOCD. Most users have solved
1821 this issue by simply using a self-powered USB Hub, which they connect their
1822 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
1823 supply stable enough for the Amontec JTAGkey to be operated.
1825 @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
1826 following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
1827 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
1828 What does that mean and what might be the reason for this?
1830 First of all, the reason might be the USB power supply. Try using a self-powered
1831 hub instead of a direct connection to your computer. Secondly, the error code 4
1832 corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
1833 Chip ran into some sort of error - this points us to a USB problem.
1835 @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
1836 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
1837 What does that mean and what might be the reason for this?
1839 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
1840 has closed the connection to OpenOCD. This might be a GDB issue.
1842 @item In the configuration file in the section where flash device configurations
1843 are described, there is a parameter for specifying the clock frequency for
1844 LPC2000 internal flash devices (e.g.
1845 @option{flash bank lpc2000 0x0 0x40000 0 0 lpc2000_v1 0 14746 calc_checksum}),
1846 which must be sepcified in kilohertz. However, I do have a quartz crystal of a
1847 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz, i.e. 14,745.600 kHz).
1848 Is it possible to specify real numbers for the clock frequency?
1850 No. The clock frequency specified here must be given as an integral number.
1851 However, this clock frequency is used by the In-Application-Programming (IAP)
1852 routines of the LPC2000 family only, which seems to be very tolerant concerning
1853 the given clock frequency, so a slight difference between the specified clock
1854 frequency and the actual clock frequency will not cause any trouble.
1856 @item Do I have to keep a specific order for the commands in the configuration file?
1858 Well, yes and no. Commands can be given in arbitrary order, yet the devices
1859 listed for the JTAG scan chain must be given in the right order (jtag_device),
1860 with the device closest to the TDO-Pin being listed first. In general,
1861 whenever objects of the same type exist which require an index number, then
1862 these objects must be given in the right order (jtag_devices, targets and flash
1863 banks - a target references a jtag_device and a flash bank references a target).
1865 @item Sometimes my debugging session terminates with an error. When I look into the
1866 log file, I can see these error messages: Error: arm7_9_common.c:561
1867 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP