1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle Open On-Chip Debugger (OpenOCD)
5 @dircategory Development
8 * OpenOCD: (openocd). Open On-Chip Debugger.
17 @item Copyright @copyright{} 2008 The OpenOCD Project
18 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
19 @item Copyright @copyright{} 2008 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
20 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
24 Permission is granted to copy, distribute and/or modify this document
25 under the terms of the GNU Free Documentation License, Version 1.2 or
26 any later version published by the Free Software Foundation; with no
27 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
28 Texts. A copy of the license is included in the section entitled ``GNU
29 Free Documentation License''.
34 @title Open On-Chip Debugger (OpenOCD)
35 @subtitle Edition @value{EDITION} for OpenOCD version @value{VERSION}
36 @subtitle @value{UPDATED}
38 @vskip 0pt plus 1filll
45 @node Top, About, , (dir)
48 This manual documents edition @value{EDITION} of the Open On-Chip Debugger
49 (OpenOCD) version @value{VERSION}, @value{UPDATED}.
54 * About:: About OpenOCD
55 * Developers:: OpenOCD Developers
56 * Building OpenOCD:: Building OpenOCD From SVN
57 * JTAG Hardware Dongles:: JTAG Hardware Dongles
58 * Running:: Running OpenOCD
59 * Simple Configuration Files:: Simple Configuration Files
60 * Config File Guidelines:: Config File Guidelines
61 * About JIM-Tcl:: About JIM-Tcl
62 * Daemon Configuration:: Daemon Configuration
63 * Interface - Dongle Configuration:: Interface - Dongle Configuration
64 * Reset Configuration:: Reset Configuration
65 * Tap Creation:: Tap Creation
66 * Target Configuration:: Target Configuration
67 * Flash Configuration:: Flash Configuration
68 * NAND Flash Commands:: NAND Flash Commands
69 * General Commands:: General Commands
70 * JTAG Commands:: JTAG Commands
71 * Sample Scripts:: Sample Target Scripts
73 * GDB and OpenOCD:: Using GDB and OpenOCD
74 * Tcl Scripting API:: Tcl Scripting API
75 * Upgrading:: Deprecated/Removed Commands
76 * Target Library:: Target Library
77 * FAQ:: Frequently Asked Questions
78 * Tcl Crash Course:: Tcl Crash Course
79 * License:: GNU Free Documentation License
80 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
81 @comment case issue with ``Index.html'' and ``index.html''
82 @comment Occurs when creating ``--html --no-split'' output
83 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
84 * OpenOCD Concept Index:: Concept Index
85 * OpenOCD Command Index:: Command Index
92 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
93 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
94 Since that time, the project has grown into an active open-source project,
95 supported by a diverse community of software and hardware developers from
98 @section What is OpenOCD?
100 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
101 in-system programming and boundary-scan testing for embedded target
104 @b{JTAG:} OpenOCD uses a ``hardware interface dongle'' to communicate
105 with the JTAG (IEEE 1149.1) compliant taps on your target board.
107 @b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
108 based, parallel port based, and other standalone boxes that run
109 OpenOCD internally. @xref{JTAG Hardware Dongles}.
111 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
112 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
113 Cortex-M3 (Luminary Stellaris LM3 and ST STM32) based cores to be
114 debugged via the GDB protocol.
116 @b{Flash Programing:} Flash writing is supported for external CFI
117 compatible NOR flashes (Intel and AMD/Spansion command set) and several
118 internal flashes (LPC2000, AT91SAM7, STR7x, STR9x, LM3, and
119 STM32x). Preliminary support for various NAND flash controllers
120 (LPC3180, Orion, S3C24xx, more) controller is included.
122 @section OpenOCD Web Site
124 The OpenOCD web site provides the latest public news from the community:
126 @uref{http://openocd.berlios.de/web/}
130 @chapter OpenOCD Developer Resources
133 If you are interested in improving the state of OpenOCD's debugging and
134 testing support, new contributions will be welcome. Motivated developers
135 can produce new target, flash or interface drivers, improve the
136 documentation, as well as more conventional bug fixes and enhancements.
138 The resources in this chapter are available for developers wishing to explore
139 or expand the OpenOCD source code.
141 @section OpenOCD Subversion Repository
143 The ``Building From Source'' section provides instructions to retrieve
144 and and build the latest version of the OpenOCD source code.
145 @xref{Building OpenOCD}.
147 Developers that want to contribute patches to the OpenOCD system are
148 @b{strongly} encouraged to base their work off of the most recent trunk
149 revision. Patches created against older versions may require additional
150 work from their submitter in order to be updated for newer releases.
152 @section Doxygen Developer Manual
154 During the development of the 0.2.0 release, the OpenOCD project began
155 providing a Doxygen reference manual. This document contains more
156 technical information about the software internals, development
157 processes, and similar documentation:
159 @uref{http://openocd.berlios.de/doc/doxygen/index.html}
161 This document is a work-in-progress, but contributions would be welcome
162 to fill in the gaps. All of the source files are provided in-tree,
163 listed in the Doxyfile configuration in the top of the repository trunk.
165 @section OpenOCD Developer Mailing List
167 The OpenOCD Developer Mailing List provides the primary means of
168 communication between developers:
170 @uref{https://lists.berlios.de/mailman/listinfo/openocd-development}
172 All drivers developers are enouraged to also subscribe to the list of
173 SVN commits to keep pace with the ongoing changes:
175 @uref{https://lists.berlios.de/mailman/listinfo/openocd-svn}
177 @node Building OpenOCD
178 @chapter Building OpenOCD
181 @section Pre-Built Tools
182 If you are interested in getting actual work done rather than building
183 OpenOCD, then check if your interface supplier provides binaries for
184 you. Chances are that that binary is from some SVN version that is more
185 stable than SVN trunk where bleeding edge development takes place.
187 @section Packagers Please Read!
189 You are a @b{PACKAGER} of OpenOCD if you
192 @item @b{Sell dongles} and include pre-built binaries
193 @item @b{Supply tools} i.e.: A complete development solution
194 @item @b{Supply IDEs} like Eclipse, or RHIDE, etc.
195 @item @b{Build packages} i.e.: RPM files, or DEB files for a Linux Distro
198 As a @b{PACKAGER}, you will experience first reports of most issues.
199 When you fix those problems for your users, your solution may help
200 prevent hundreds (if not thousands) of other questions from other users.
202 If something does not work for you, please work to inform the OpenOCD
203 developers know how to improve the system or documentation to avoid
204 future problems, and follow-up to help us ensure the issue will be fully
205 resolved in our future releases.
207 That said, the OpenOCD developers would also like you to follow a few
211 @item @b{Always build with printer ports enabled.}
212 @item @b{Try to use LIBFTDI + LIBUSB where possible. You cover more bases.}
216 @item @b{Why YES to LIBFTDI + LIBUSB?}
218 @item @b{LESS} work - libusb perhaps already there
219 @item @b{LESS} work - identical code, multiple platforms
220 @item @b{MORE} dongles are supported
221 @item @b{MORE} platforms are supported
222 @item @b{MORE} complete solution
224 @item @b{Why not LIBFTDI + LIBUSB} (i.e.: ftd2xx instead)?
226 @item @b{LESS} speed - some say it is slower
227 @item @b{LESS} complex to distribute (external dependencies)
231 @section Building From Source
233 You can download the current SVN version with an SVN client of your choice from the
234 following repositories:
236 @uref{svn://svn.berlios.de/openocd/trunk}
240 @uref{http://svn.berlios.de/svnroot/repos/openocd/trunk}
242 Using the SVN command line client, you can use the following command to fetch the
243 latest version (make sure there is no (non-svn) directory called "openocd" in the
247 svn checkout svn://svn.berlios.de/openocd/trunk openocd
250 Building OpenOCD requires a recent version of the GNU autotools (autoconf >= 2.59 and automake >= 1.9).
251 For building on Windows,
252 you have to use Cygwin. Make sure that your @env{PATH} environment variable contains no
253 other locations with Unix utils (like UnxUtils) - these can't handle the Cygwin
254 paths, resulting in obscure dependency errors (This is an observation I've gathered
255 from the logs of one user - correct me if I'm wrong).
257 You further need the appropriate driver files, if you want to build support for
258 a FTDI FT2232 based interface:
261 @item @b{ftdi2232} libftdi (@uref{http://www.intra2net.com/opensource/ftdi/})
262 @item @b{ftd2xx} libftd2xx (@uref{http://www.ftdichip.com/Drivers/D2XX.htm})
263 @item When using the Amontec JTAGkey, you have to get the drivers from the Amontec
264 homepage (@uref{http://www.amontec.com}), as the JTAGkey uses a non-standard VID/PID.
267 libftdi is supported under Windows. Do not use versions earlier than 0.14.
269 In general, the D2XX driver provides superior performance (several times as fast),
270 but has the draw-back of being binary-only - though that isn't that bad, as it isn't
271 a kernel module, only a user space library.
273 To build OpenOCD (on both Linux and Cygwin), use the following commands:
279 Bootstrap generates the configure script, and prepares building on your system.
282 ./configure [options, see below]
285 Configure generates the Makefiles used to build OpenOCD.
292 Make builds OpenOCD, and places the final executable in ./src/, the last step, ``make install'' is optional.
294 The configure script takes several options, specifying which JTAG interfaces
295 should be included (among other things):
299 @option{--enable-parport} - Enable building the PC parallel port driver.
301 @option{--enable-parport_ppdev} - Enable use of ppdev (/dev/parportN) for parport.
303 @option{--enable-parport_giveio} - Enable use of giveio for parport instead of ioperm.
305 @option{--enable-amtjtagaccel} - Enable building the Amontec JTAG-Accelerator driver.
307 @option{--enable-ecosboard} - Enable building support for eCosBoard based JTAG debugger.
309 @option{--enable-ioutil} - Enable ioutil functions - useful for standalone OpenOCD implementations.
311 @option{--enable-httpd} - Enable builtin httpd server - useful for standalone OpenOCD implementations.
313 @option{--enable-ep93xx} - Enable building support for EP93xx based SBCs.
315 @option{--enable-at91rm9200} - Enable building support for AT91RM9200 based SBCs.
317 @option{--enable-gw16012} - Enable building support for the Gateworks GW16012 JTAG programmer.
319 @option{--enable-ft2232_ftd2xx} - Numerous USB type ARM JTAG dongles use the FT2232C chip from this FTDICHIP.COM chip (closed source).
321 @option{--enable-ft2232_libftdi} - An open source (free) alternative to FTDICHIP.COM ftd2xx solution (Linux, MacOS, Cygwin).
323 @option{--with-ftd2xx-win32-zipdir=PATH} - If using FTDICHIP.COM ft2232c, point at the directory where the Win32 FTDICHIP.COM 'CDM' driver zip file was unpacked.
325 @option{--with-ftd2xx-linux-tardir=PATH} - Linux only. Equivalent of @option{--with-ftd2xx-win32-zipdir}, where you unpacked the TAR.GZ file.
327 @option{--with-ftd2xx-lib=shared|static} - Linux only. Default: static. Specifies how the FTDICHIP.COM libftd2xx driver should be linked. Note: 'static' only works in conjunction with @option{--with-ftd2xx-linux-tardir}. The 'shared' value is supported (12/26/2008), however you must manually install the required header files and shared libraries in an appropriate place. This uses ``libusb'' internally.
329 @option{--enable-presto_libftdi} - Enable building support for ASIX Presto programmer using the libftdi driver.
331 @option{--enable-presto_ftd2xx} - Enable building support for ASIX Presto programmer using the FTD2XX driver.
333 @option{--enable-usbprog} - Enable building support for the USBprog JTAG programmer.
335 @option{--enable-oocd_trace} - Enable building support for the OpenOCD+trace ETM capture device.
337 @option{--enable-jlink} - Enable building support for the Segger J-Link JTAG programmer.
339 @option{--enable-vsllink} - Enable building support for the Versaloon-Link JTAG programmer.
341 @option{--enable-rlink} - Enable building support for the Raisonance RLink JTAG programmer.
343 @option{--enable-arm-jtag-ew} - Enable building support for the Olimex ARM-JTAG-EW programmer.
345 @option{--enable-dummy} - Enable building the dummy port driver.
348 @section Parallel Port Dongles
350 If you want to access the parallel port using the PPDEV interface you have to specify
351 both the @option{--enable-parport} AND the @option{--enable-parport_ppdev} option since
352 the @option{--enable-parport_ppdev} option actually is an option to the parport driver
353 (see @uref{http://forum.sparkfun.com/viewtopic.php?t=3795} for more info).
355 The same is true for the @option{--enable-parport_giveio} option, you have to
356 use both the @option{--enable-parport} AND the @option{--enable-parport_giveio} option if you want to use giveio instead of ioperm parallel port access method.
358 @section FT2232C Based USB Dongles
360 There are 2 methods of using the FTD2232, either (1) using the
361 FTDICHIP.COM closed source driver, or (2) the open (and free) driver
362 libftdi. Some claim the (closed) FTDICHIP.COM solution is faster.
364 The FTDICHIP drivers come as either a (win32) ZIP file, or a (Linux)
365 TAR.GZ file. You must unpack them ``some where'' convient. As of this
366 writing (12/26/2008) FTDICHIP does not supply means to install these
367 files ``in an appropriate place'' As a result, there are two
368 ``./configure'' options that help.
370 Below is an example build process:
372 1) Check out the latest version of ``openocd'' from SVN.
374 2) Download & unpack either the Windows or Linux FTD2xx drivers
375 (@uref{http://www.ftdichip.com/Drivers/D2XX.htm}).
378 /home/duane/ftd2xx.win32 => the Cygwin/Win32 ZIP file contents.
379 /home/duane/libftd2xx0.4.16 => the Linux TAR.GZ file contents.
382 3) Configure with these options:
385 Cygwin FTDICHIP solution:
386 ./configure --prefix=/home/duane/mytools \
387 --enable-ft2232_ftd2xx \
388 --with-ftd2xx-win32-zipdir=/home/duane/ftd2xx.win32
390 Linux FTDICHIP solution:
391 ./configure --prefix=/home/duane/mytools \
392 --enable-ft2232_ftd2xx \
393 --with-ft2xx-linux-tardir=/home/duane/libftd2xx0.4.16
395 Cygwin/Linux LIBFTDI solution:
397 1a) For Windows: The Windows port of LIBUSB is in place.
398 1b) For Linux: libusb has been built/installed and is in place.
400 2) And libftdi has been built and installed
401 Note: libftdi - relies upon libusb.
403 ./configure --prefix=/home/duane/mytools \
404 --enable-ft2232_libftdi
408 4) Then just type ``make'', and perhaps ``make install''.
411 @section Miscellaneous Configure Options
415 @option{--disable-option-checking} - Ignore unrecognized @option{--enable} and @option{--with} options.
417 @option{--enable-gccwarnings} - Enable extra gcc warnings during build.
420 @option{--enable-release} - Enable building of an OpenOCD release, generally
421 this is for developers. It simply omits the svn version string when the
422 openocd @option{-v} is executed.
425 @node JTAG Hardware Dongles
426 @chapter JTAG Hardware Dongles
435 Defined: @b{dongle}: A small device that plugins into a computer and serves as
436 an adapter .... [snip]
438 In the OpenOCD case, this generally refers to @b{a small adapater} one
439 attaches to your computer via USB or the Parallel Printer Port. The
440 execption being the Zylin ZY1000 which is a small box you attach via
441 an ethernet cable. The Zylin ZY1000 has the advantage that it does not
442 require any drivers to be installed on the developer PC. It also has
443 a built in web interface. It supports RTCK/RCLK or adaptive clocking
444 and has a built in relay to power cycle targets remotely.
447 @section Choosing a Dongle
449 There are three things you should keep in mind when choosing a dongle.
452 @item @b{Voltage} What voltage is your target? 1.8, 2.8, 3.3, or 5V? Does your dongle support it?
453 @item @b{Connection} Printer Ports - Does your computer have one?
454 @item @b{Connection} Is that long printer bit-bang cable practical?
455 @item @b{RTCK} Do you require RTCK? Also known as ``adaptive clocking''
458 @section Stand alone Systems
460 @b{ZY1000} See: @url{http://www.zylin.com/zy1000.html} Technically, not a
461 dongle, but a standalone box. The ZY1000 has the advantage that it does
462 not require any drivers installed on the developer PC. It also has
463 a built in web interface. It supports RTCK/RCLK or adaptive clocking
464 and has a built in relay to power cycle targets remotely.
466 @section USB FT2232 Based
468 There are many USB JTAG dongles on the market, many of them are based
469 on a chip from ``Future Technology Devices International'' (FTDI)
470 known as the FTDI FT2232.
472 See: @url{http://www.ftdichip.com} or @url{http://www.ftdichip.com/Products/FT2232H.htm}
474 As of 28/Nov/2008, the following are supported:
478 @* Link @url{http://www.hs-augsburg.de/~hhoegl/proj/usbjtag/usbjtag.html}
480 @* See: @url{http://www.amontec.com/jtagkey.shtml}
482 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
484 @* See: @url{http://www.signalyzer.com}
485 @item @b{evb_lm3s811}
486 @* See: @url{http://www.luminarymicro.com} - The Luminary Micro Stellaris LM3S811 eval board has an FTD2232C chip built in.
487 @item @b{olimex-jtag}
488 @* See: @url{http://www.olimex.com}
490 @* See: @url{http://www.tincantools.com}
491 @item @b{turtelizer2}
492 @* See: @url{http://www.ethernut.de}, or @url{http://www.ethernut.de/en/hardware/turtelizer/index.html}
494 @* Link: @url{http://www.hitex.com/index.php?id=383}
496 @* Link @url{http://www.hitex.com/stm32-stick}
497 @item @b{axm0432_jtag}
498 @* Axiom AXM-0432 Link @url{http://www.axman.com}
500 @* Link @url{http://www.hitex.com/index.php?id=cortino}
503 @section USB JLINK based
504 There are several OEM versions of the Segger @b{JLINK} adapter. It is
505 an example of a micro controller based JTAG adapter, it uses an
506 AT91SAM764 internally.
509 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
510 @* Link: @url{http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3892}
511 @item @b{SEGGER JLINK}
512 @* Link: @url{http://www.segger.com/jlink.html}
514 @* Link: @url{http://www.iar.com/website1/1.0.1.0/369/1/index.php}
517 @section USB RLINK based
518 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer, permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for SWD and not JTAG, thus not supported.
521 @item @b{Raisonance RLink}
522 @* Link: @url{http://www.raisonance.com/products/RLink.php}
523 @item @b{STM32 Primer}
524 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
525 @item @b{STM32 Primer2}
526 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
532 @* Link: @url{http://www.embedded-projects.net/usbprog} - which uses an Atmel MEGA32 and a UBN9604
534 @item @b{USB - Presto}
535 @* Link: @url{http://tools.asix.net/prg_presto.htm}
537 @item @b{Versaloon-Link}
538 @* Link: @url{http://www.simonqian.com/en/Versaloon}
540 @item @b{ARM-JTAG-EW}
541 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
544 @section IBM PC Parallel Printer Port Based
546 The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
547 and the MacGraigor Wiggler. There are many clones and variations of
552 @item @b{Wiggler} - There are many clones of this.
553 @* Link: @url{http://www.macraigor.com/wiggler.htm}
555 @item @b{DLC5} - From XILINX - There are many clones of this
556 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
557 produced, PDF schematics are easily found and it is easy to make.
559 @item @b{Amontec - JTAG Accelerator}
560 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
563 @* Link: @url{http://www.gateworks.com/products/avila_accessories/gw16042.php}
566 @* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
568 @item @b{Wiggler_ntrst_inverted}
569 @* Yet another variation - See the source code, src/jtag/parport.c
571 @item @b{old_amt_wiggler}
572 @* Unknown - probably not on the market today
575 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
578 @* Link: @url{http://www.amontec.com/chameleon.shtml}
584 @* ispDownload from Lattice Semiconductor @url{http://www.latticesemi.com/lit/docs/devtools/dlcable.pdf}
587 @* From ST Microsystems, link:
588 @url{http://www.st.com/stonline/products/literature/um/7889.pdf}
589 Title: FlashLINK JTAG programing cable for PSD and uPSD
597 @* An EP93xx based Linux machine using the GPIO pins directly.
600 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
606 @cindex running OpenOCD
608 @cindex --debug_level
612 The @option{--help} option shows:
616 --help | -h display this help
617 --version | -v display OpenOCD version
618 --file | -f use configuration file <name>
619 --search | -s dir to search for config files and scripts
620 --debug | -d set debug level <0-3>
621 --log_output | -l redirect log output to file <name>
622 --command | -c run <command>
623 --pipe | -p use pipes when talking to gdb
626 By default OpenOCD reads the file configuration file ``openocd.cfg''
627 in the current directory. To specify a different (or multiple)
628 configuration file, you can use the ``-f'' option. For example:
631 openocd -f config1.cfg -f config2.cfg -f config3.cfg
634 Once started, OpenOCD runs as a daemon, waiting for connections from
635 clients (Telnet, GDB, Other).
637 If you are having problems, you can enable internal debug messages via
640 Also it is possible to interleave commands w/config scripts using the
641 @option{-c} command line switch.
643 To enable debug output (when reporting problems or working on OpenOCD
644 itself), use the @option{-d} command line switch. This sets the
645 @option{debug_level} to "3", outputting the most information,
646 including debug messages. The default setting is "2", outputting only
647 informational messages, warnings and errors. You can also change this
648 setting from within a telnet or gdb session using @option{debug_level
649 <n>} @xref{debug_level}.
651 You can redirect all output from the daemon to a file using the
652 @option{-l <logfile>} switch.
654 Search paths for config/script files can be added to OpenOCD by using
655 the @option{-s <search>} switch. The current directory and the OpenOCD
656 target library is in the search path by default.
658 For details on the @option{-p} option. @xref{Connecting to GDB}.
660 Note! OpenOCD will launch the GDB & telnet server even if it can not
661 establish a connection with the target. In general, it is possible for
662 the JTAG controller to be unresponsive until the target is set up
663 correctly via e.g. GDB monitor commands in a GDB init script.
665 @node Simple Configuration Files
666 @chapter Simple Configuration Files
667 @cindex configuration
670 There are 4 basic ways of ``configurating'' OpenOCD to run, they are:
673 @item A small openocd.cfg file which ``sources'' other configuration files
674 @item A monolithic openocd.cfg file
675 @item Many -f filename options on the command line
676 @item Your Mixed Solution
679 @section Small configuration file method
681 This is the preferred method. It is simple and works well for many
682 people. The developers of OpenOCD would encourage you to use this
683 method. If you create a new configuration please email new
684 configurations to the development list.
686 Here is an example of an openocd.cfg file for an ATMEL at91sam7x256
689 source [find interface/signalyzer.cfg]
691 # GDB can also flash my flash!
692 gdb_memory_map enable
693 gdb_flash_program enable
695 source [find target/sam7x256.cfg]
698 There are many example configuration scripts you can work with. You
699 should look in the directory: @t{$(INSTALLDIR)/lib/openocd}. You
703 @item @b{board} - eval board level configurations
704 @item @b{interface} - specific dongle configurations
705 @item @b{target} - the target chips
706 @item @b{tcl} - helper scripts
707 @item @b{xscale} - things specific to the xscale.
710 Look first in the ``boards'' area, then the ``targets'' area. Often a board
711 configuration is a good example to work from.
713 @section Many -f filename options
714 Some believe this is a wonderful solution, others find it painful.
716 You can use a series of ``-f filename'' options on the command line,
717 OpenOCD will read each filename in sequence, for example:
720 openocd -f file1.cfg -f file2.cfg -f file2.cfg
723 You can also intermix various commands with the ``-c'' command line
726 @section Monolithic file
727 The ``Monolithic File'' dispenses with all ``source'' statements and
728 puts everything in one self contained (monolithic) file. This is not
731 Please try to ``source'' various files or use the multiple -f
734 @section Advice for you
735 Often, one uses a ``mixed approach''. Where possible, please try to
736 ``source'' common things, and if needed cut/paste parts of the
737 standard distribution configuration files as needed.
739 @b{REMEMBER:} The ``important parts'' of your configuration file are:
742 @item @b{Interface} - Defines the dongle
743 @item @b{Taps} - Defines the JTAG Taps
744 @item @b{GDB Targets} - What GDB talks to
745 @item @b{Flash Programing} - Very Helpful
748 Some key things you should look at and understand are:
751 @item The reset configuration of your debug environment as a whole
752 @item Is there a ``work area'' that OpenOCD can use?
753 @* For ARM - work areas mean up to 10x faster downloads.
754 @item For MMU/MPU based ARM chips (i.e.: ARM9 and later) will that work area still be available?
755 @item For complex targets (multiple chips) the JTAG SPEED becomes an issue.
760 @node Config File Guidelines
761 @chapter Config File Guidelines
763 This section/chapter is aimed at developers and integrators of
764 OpenOCD. These are guidelines for creating new boards and new target
765 configurations as of 28/Nov/2008.
767 However, you, the user of OpenOCD, should be somewhat familiar with
768 this section as it should help explain some of the internals of what
769 you might be looking at.
771 The user should find the following directories under @t{$(INSTALLDIR)/lib/openocd} :
775 @*Think JTAG Dongle. Files that configure the JTAG dongle go here.
777 @* Think Circuit Board, PWA, PCB, they go by many names. Board files
778 contain initialization items that are specific to a board - for
779 example: The SDRAM initialization sequence for the board, or the type
780 of external flash and what address it is found at. Any initialization
781 sequence to enable that external flash or SDRAM should be found in the
782 board file. Boards may also contain multiple targets, i.e.: Two CPUs, or
783 a CPU and an FPGA or CPLD.
785 @* Think chip. The ``target'' directory represents a JTAG tap (or
786 chip) OpenOCD should control, not a board. Two common types of targets
787 are ARM chips and FPGA or CPLD chips.
790 @b{If needed...} The user in their ``openocd.cfg'' file or the board
791 file might override a specific feature in any of the above files by
792 setting a variable or two before sourcing the target file. Or adding
793 various commands specific to their situation.
795 @section Interface Config Files
797 The user should be able to source one of these files via a command like this:
800 source [find interface/FOOBAR.cfg]
802 openocd -f interface/FOOBAR.cfg
805 A preconfigured interface file should exist for every interface in use
806 today, that said, perhaps some interfaces have only been used by the
807 sole developer who created it.
809 @b{FIXME/NOTE:} We need to add support for a variable like Tcl variable
810 tcl_platform(platform), it should be called jim_platform (because it
811 is jim, not real tcl) and it should contain 1 of 3 words: ``linux'',
812 ``cygwin'' or ``mingw''
814 Interface files should be found in @t{$(INSTALLDIR)/lib/openocd/interface}
816 @section Board Config Files
818 @b{Note: BOARD directory NEW as of 28/nov/2008}
820 The user should be able to source one of these files via a command like this:
823 source [find board/FOOBAR.cfg]
825 openocd -f board/FOOBAR.cfg
829 The board file should contain one or more @t{source [find
830 target/FOO.cfg]} statements along with any board specific things.
832 In summary the board files should contain (if present)
835 @item External flash configuration (i.e.: NOR flash on CS0, two NANDs on CS2)
836 @item SDRAM configuration (size, speed, etc.
837 @item Board specific IO configuration (i.e.: GPIO pins might disable a 2nd flash)
838 @item Multiple TARGET source statements
839 @item All things that are not ``inside a chip''
840 @item Things inside a chip go in a 'target' file
843 @section Target Config Files
845 The user should be able to source one of these files via a command like this:
848 source [find target/FOOBAR.cfg]
850 openocd -f target/FOOBAR.cfg
853 In summary the target files should contain
858 @item Reset configuration
860 @item CPU/Chip/CPU-Core specific features
864 @subsection Important variable names
866 By default, the end user should never need to set these
867 variables. However, if the user needs to override a setting they only
868 need to set the variable in a simple way.
872 @* This gives a name to the overall chip, and is used as part of the
873 tap identifier dotted name.
875 @* By default little - unless the chip or board is not normally used that way.
877 @* When OpenOCD examines the JTAG chain, it will attempt to identify
878 every chip. If the @t{-expected-id} is nonzero, OpenOCD attempts
879 to verify the tap id number verses configuration file and may issue an
880 error or warning like this. The hope is that this will help to pinpoint
881 problems in OpenOCD configurations.
884 Info: JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
885 Error: ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
886 Error: ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
887 Error: ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
890 @item @b{_TARGETNAME}
891 @* By convention, this variable is created by the target configuration
892 script. The board configuration file may make use of this variable to
893 configure things like a ``reset init'' script, or other things
894 specific to that board and that target.
896 If the chip has 2 targets, use the names @b{_TARGETNAME0},
897 @b{_TARGETNAME1}, ... etc.
899 @b{Remember:} The ``board file'' may include multiple targets.
901 At no time should the name ``target0'' (the default target name if
902 none was specified) be used. The name ``target0'' is a hard coded name
903 - the next target on the board will be some other number.
904 In the same way, avoid using target numbers even when they are
905 permitted; use the right target name(s) for your board.
907 The user (or board file) should reasonably be able to:
910 source [find target/FOO.cfg]
911 $_TARGETNAME configure ... FOO specific parameters
913 source [find target/BAR.cfg]
914 $_TARGETNAME configure ... BAR specific parameters
919 @subsection Tcl Variables Guide Line
920 The Full Tcl/Tk language supports ``namespaces'' - JIM-Tcl does not.
922 Thus the rule we follow in OpenOCD is this: Variables that begin with
923 a leading underscore are temporary in nature, and can be modified and
924 used at will within a ?TARGET? configuration file.
926 @b{EXAMPLE:} The user should be able to do this:
930 # PXA270 #1 network side, big endian
931 # PXA270 #2 video side, little endian
935 source [find target/pxa270.cfg]
936 # variable: _TARGETNAME = network.cpu
937 # other commands can refer to the "network.cpu" tap.
938 $_TARGETNAME configure .... params for this CPU..
942 source [find target/pxa270.cfg]
943 # variable: _TARGETNAME = video.cpu
944 # other commands can refer to the "video.cpu" tap.
945 $_TARGETNAME configure .... params for this CPU..
949 source [find target/spartan3.cfg]
951 # Since $_TARGETNAME is temporal..
952 # these names still work!
953 network.cpu configure ... params
954 video.cpu configure ... params
958 @subsection Default Value Boiler Plate Code
960 All target configuration files should start with this (or a modified form)
964 if @{ [info exists CHIPNAME] @} @{
965 set _CHIPNAME $CHIPNAME
967 set _CHIPNAME sam7x256
970 if @{ [info exists ENDIAN] @} @{
976 if @{ [info exists CPUTAPID ] @} @{
977 set _CPUTAPID $CPUTAPID
979 set _CPUTAPID 0x3f0f0f0f
984 @subsection Creating Taps
985 After the ``defaults'' are choosen [see above] the taps are created.
987 @b{SIMPLE example:} such as an Atmel AT91SAM7X256
991 set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
992 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
997 This is an SNIP/example for an STR912 - which has 3 internal taps. Key features shown:
1000 @item @b{Unform tap names} - See: Tap Naming Convention
1001 @item @b{_TARGETNAME} is created at the end where used.
1005 if @{ [info exists FLASHTAPID ] @} @{
1006 set _FLASHTAPID $FLASHTAPID
1008 set _FLASHTAPID 0x25966041
1010 jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id $_FLASHTAPID
1012 if @{ [info exists CPUTAPID ] @} @{
1013 set _CPUTAPID $CPUTAPID
1015 set _CPUTAPID 0x25966041
1017 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0xf -irmask 0xe -expected-id $_CPUTAPID
1020 if @{ [info exists BSTAPID ] @} @{
1021 set _BSTAPID $BSTAPID
1023 set _BSTAPID 0x1457f041
1025 jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID
1027 set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
1030 @b{Tap Naming Convention}
1032 See the command ``jtag newtap'' for detail, but in brief the names you should use are:
1041 @item @b{unknownN} - it happens :-(
1044 @subsection Reset Configuration
1046 Some chips have specific ways the TRST and SRST signals are
1047 managed. If these are @b{CHIP SPECIFIC} they go here, if they are
1048 @b{BOARD SPECIFIC} they go in the board file.
1050 @subsection Work Areas
1052 Work areas are small RAM areas used by OpenOCD to speed up downloads,
1053 and to download small snippets of code to program flash chips.
1055 If the chip includes a form of ``on-chip-ram'' - and many do - define
1056 a reasonable work area and use the ``backup'' option.
1058 @b{PROBLEMS:} On more complex chips, this ``work area'' may become
1059 inaccessible if/when the application code enables or disables the MMU.
1061 @subsection ARM Core Specific Hacks
1063 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1064 special high speed download features - enable it.
1066 If the chip has an ARM ``vector catch'' feature - by default enable
1067 it for Undefined Instructions, Data Abort, and Prefetch Abort, if the
1068 user is really writing a handler for those situations - they can
1069 easily disable it. Experiance has shown the ``vector catch'' is
1070 helpful - for common programing errors.
1072 If present, the MMU, the MPU and the CACHE should be disabled.
1074 Some ARM cores are equipped with trace support, which permits
1075 examination of the instruction and data bus activity. Trace
1076 activity is controlled through an ``Embedded Trace Module'' (ETM)
1077 on one of the core's scan chains. The ETM emits voluminous data
1078 through a ``trace port''. The trace port is accessed in one
1079 of two ways. When its signals are pinned out from the chip,
1080 boards may provide a special high speed debugging connector;
1081 software support for this is not configured by default, use
1082 the ``--enable-oocd_trace'' option. Alternatively, trace data
1083 may be stored an on-chip SRAM which is packaged as an ``Embedded
1084 Trace Buffer'' (ETB). An ETB has its own TAP, usually right after
1085 its associated ARM core. OpenOCD supports the ETM, and your
1086 target configuration should set it up with the relevant trace
1087 port: ``etb'' for chips which use that, else the board-specific
1088 option will be either ``oocd_trace'' or ``dummy''.
1091 etm config $_TARGETNAME 16 normal full etb
1092 etb config $_TARGETNAME $_CHIPNAME.etb
1095 @subsection Internal Flash Configuration
1097 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1099 @b{Never ever} in the ``target configuration file'' define any type of
1100 flash that is external to the chip. (For example a BOOT flash on
1101 Chip Select 0.) Such flash information goes in a board file - not
1102 the TARGET (chip) file.
1106 @item at91sam7x256 - has 256K flash YES enable it.
1107 @item str912 - has flash internal YES enable it.
1108 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1109 @item pxa270 - again - CS0 flash - it goes in the board file.
1113 @chapter About JIM-Tcl
1117 OpenOCD includes a small ``TCL Interpreter'' known as JIM-TCL. You can
1118 learn more about JIM here: @url{http://jim.berlios.de}
1121 @item @b{JIM vs. Tcl}
1122 @* JIM-TCL is a stripped down version of the well known Tcl language,
1123 which can be found here: @url{http://www.tcl.tk}. JIM-Tcl has far
1124 fewer features. JIM-Tcl is a single .C file and a single .H file and
1125 impliments the basic Tcl command set along. In contrast: Tcl 8.6 is a
1126 4.2 MB .zip file containing 1540 files.
1128 @item @b{Missing Features}
1129 @* Our practice has been: Add/clone the real Tcl feature if/when
1130 needed. We welcome JIM Tcl improvements, not bloat.
1133 @* OpenOCD configuration scripts are JIM Tcl Scripts. OpenOCD's
1134 command interpreter today (28/nov/2008) is a mixture of (newer)
1135 JIM-Tcl commands, and (older) the orginal command interpreter.
1138 @* At the OpenOCD telnet command line (or via the GDB mon command) one
1139 can type a Tcl for() loop, set variables, etc.
1141 @item @b{Historical Note}
1142 @* JIM-Tcl was introduced to OpenOCD in spring 2008.
1144 @item @b{Need a crash course in Tcl?}
1145 @* See: @xref{Tcl Crash Course}.
1149 @node Daemon Configuration
1150 @chapter Daemon Configuration
1151 @cindex initialization
1152 The commands here are commonly found in the openocd.cfg file and are
1153 used to specify what TCP/IP ports are used, and how GDB should be
1156 @section Configuration Stage
1157 @cindex configuration stage
1158 @cindex configuration command
1160 When the OpenOCD server process starts up, it enters a
1161 @emph{configuration stage} which is the only time that
1162 certain commands, @emph{configuration commands}, may be issued.
1163 Those configuration commands include declaration of TAPs
1164 and other basic setup.
1165 The server must leave the configuration stage before it
1166 may access or activate TAPs.
1167 After it leaves this stage, configuration commands may no
1170 @deffn {Config Command} init
1171 This command terminates the configuration stage and
1172 enters the normal command mode. This can be useful to add commands to
1173 the startup scripts and commands such as resetting the target,
1174 programming flash, etc. To reset the CPU upon startup, add "init" and
1175 "reset" at the end of the config script or at the end of the OpenOCD
1176 command line using the @option{-c} command line switch.
1178 If this command does not appear in any startup/configuration file
1179 OpenOCD executes the command for you after processing all
1180 configuration files and/or command line options.
1182 @b{NOTE:} This command normally occurs at or near the end of your
1183 openocd.cfg file to force OpenOCD to ``initialize'' and make the
1184 targets ready. For example: If your openocd.cfg file needs to
1185 read/write memory on your target, @command{init} must occur before
1186 the memory read/write commands. This includes @command{nand probe}.
1189 @section TCP/IP Ports
1193 The OpenOCD server accepts remote commands in several syntaxes.
1194 Each syntax uses a different TCP/IP port, which you may specify
1195 only during configuration (before those ports are opened).
1197 @deffn {Command} gdb_port (number)
1199 Specify or query the first port used for incoming GDB connections.
1200 The GDB port for the
1201 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
1202 When not specified during the configuration stage,
1203 the port @var{number} defaults to 3333.
1206 @deffn {Command} tcl_port (number)
1207 Specify or query the port used for a simplified RPC
1208 connection that can be used by clients to issue TCL commands and get the
1209 output from the Tcl engine.
1210 Intended as a machine interface.
1211 When not specified during the configuration stage,
1212 the port @var{number} defaults to 6666.
1215 @deffn {Command} telnet_port (number)
1216 Specify or query the
1217 port on which to listen for incoming telnet connections.
1218 This port is intended for interaction with one human through TCL commands.
1219 When not specified during the configuration stage,
1220 the port @var{number} defaults to 4444.
1223 @section GDB Configuration
1224 @anchor{GDB Configuration}
1226 @cindex GDB configuration
1227 You can reconfigure some GDB behaviors if needed.
1228 The ones listed here are static and global.
1229 @xref{Target Create}, about declaring individual targets.
1230 @xref{Target Events}, about configuring target-specific event handling.
1232 @deffn {Command} gdb_breakpoint_override <hard|soft|disable>
1233 @anchor{gdb_breakpoint_override}
1234 Force breakpoint type for gdb @command{break} commands.
1235 The raison d'etre for this option is to support GDB GUI's which don't
1236 distinguish hard versus soft breakpoints, if the default OpenOCD and
1237 GDB behaviour is not sufficient. GDB normally uses hardware
1238 breakpoints if the memory map has been set up for flash regions.
1240 This option replaces older arm7_9 target commands that addressed
1244 @deffn {Config command} gdb_detach <resume|reset|halt|nothing>
1245 Configures what OpenOCD will do when GDB detaches from the daemon.
1246 Default behaviour is @var{resume}.
1249 @deffn {Config command} gdb_flash_program <enable|disable>
1250 @anchor{gdb_flash_program}
1251 Set to @var{enable} to cause OpenOCD to program the flash memory when a
1252 vFlash packet is received.
1253 The default behaviour is @var{enable}.
1256 @deffn {Config command} gdb_memory_map <enable|disable>
1257 Set to @var{enable} to cause OpenOCD to send the memory configuration to GDB when
1258 requested. GDB will then know when to set hardware breakpoints, and program flash
1259 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
1260 for flash programming to work.
1261 Default behaviour is @var{enable}.
1262 @xref{gdb_flash_program}.
1265 @deffn {Config command} gdb_report_data_abort <enable|disable>
1266 Specifies whether data aborts cause an error to be reported
1267 by GDB memory read packets.
1268 The default behaviour is @var{disable};
1269 use @var{enable} see these errors reported.
1272 @node Interface - Dongle Configuration
1273 @chapter Interface - Dongle Configuration
1274 Interface commands are normally found in an interface configuration
1275 file which is sourced by your openocd.cfg file. These commands tell
1276 OpenOCD what type of JTAG dongle you have and how to talk to it.
1277 @section Simple Complete Interface Examples
1278 @b{A Turtelizer FT2232 Based JTAG Dongle}
1282 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter A"
1283 ft2232_layout turtelizer2
1284 ft2232_vid_pid 0x0403 0xbdc8
1291 @b{A Raisonance RLink}
1300 parport_cable wiggler
1305 interface arm-jtag-ew
1307 @section Interface Command
1309 The interface command tells OpenOCD what type of JTAG dongle you are
1310 using. Depending on the type of dongle, you may need to have one or
1311 more additional commands.
1315 @item @b{interface} <@var{name}>
1317 @*Use the interface driver <@var{name}> to connect to the
1318 target. Currently supported interfaces are
1323 @* PC parallel port bit-banging (Wigglers, PLD download cable, ...)
1325 @item @b{amt_jtagaccel}
1326 @* Amontec Chameleon in its JTAG Accelerator configuration connected to a PC's EPP
1330 @* FTDI FT2232 (USB) based devices using either the open-source libftdi or the binary only
1331 FTD2XX driver. The FTD2XX is superior in performance, but not available on every
1332 platform. The libftdi uses libusb, and should be portable to all systems that provide
1336 @*Cirrus Logic EP93xx based single-board computer bit-banging (in development)
1339 @* ASIX PRESTO USB JTAG programmer.
1342 @* usbprog is a freely programmable USB adapter.
1345 @* Gateworks GW16012 JTAG programmer.
1348 @* Segger jlink USB adapter
1351 @* Raisonance RLink USB adapter
1354 @* vsllink is part of Versaloon which is a versatile USB programmer.
1356 @item @b{arm-jtag-ew}
1357 @* Olimex ARM-JTAG-EW USB adapter
1358 @comment - End parameters
1360 @comment - End Interface
1362 @subsection parport options
1365 @item @b{parport_port} <@var{number}>
1366 @cindex parport_port
1367 @*Either the address of the I/O port (default: 0x378 for LPT1) or the number of
1368 the @file{/dev/parport} device
1370 When using PPDEV to access the parallel port, use the number of the parallel port:
1371 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
1372 you may encounter a problem.
1373 @item @b{parport_cable} <@var{name}>
1374 @cindex parport_cable
1375 @*The layout of the parallel port cable used to connect to the target.
1376 Currently supported cables are
1380 The original Wiggler layout, also supported by several clones, such
1381 as the Olimex ARM-JTAG
1384 Same as original wiggler except an led is fitted on D5.
1385 @item @b{wiggler_ntrst_inverted}
1386 @cindex wiggler_ntrst_inverted
1387 Same as original wiggler except TRST is inverted.
1388 @item @b{old_amt_wiggler}
1389 @cindex old_amt_wiggler
1390 The Wiggler configuration that comes with Amontec's Chameleon Programmer. The new
1391 version available from the website uses the original Wiggler layout ('@var{wiggler}')
1394 The Amontec Chameleon's CPLD when operated in configuration mode. This is only used to
1395 program the Chameleon itself, not a connected target.
1398 The Xilinx Parallel cable III.
1401 The parallel port adapter found on the 'Karo Triton 1 Development Board'.
1402 This is also the layout used by the HollyGates design
1403 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
1406 The ST Parallel cable.
1409 Same as original wiggler except SRST and TRST connections reversed and
1410 TRST is also inverted.
1413 Altium Universal JTAG cable.
1415 @item @b{parport_write_on_exit} <@var{on}|@var{off}>
1416 @cindex parport_write_on_exit
1417 @*This will configure the parallel driver to write a known value to the parallel
1418 interface on exiting OpenOCD
1421 @subsection amt_jtagaccel options
1423 @item @b{parport_port} <@var{number}>
1424 @cindex parport_port
1425 @*Either the address of the I/O port (default: 0x378 for LPT1) or the number of the
1426 @file{/dev/parport} device
1428 @subsection ft2232 options
1431 @item @b{ft2232_device_desc} <@var{description}>
1432 @cindex ft2232_device_desc
1433 @*The USB device description of the FTDI FT2232 device. If not
1434 specified, the FTDI default value is used. This setting is only valid
1435 if compiled with FTD2XX support.
1437 @b{TODO:} Confirm the following: On Windows the name needs to end with
1438 a ``space A''? Or not? It has to do with the FTD2xx driver. When must
1439 this be added and when must it not be added? Why can't the code in the
1440 interface or in OpenOCD automatically add this if needed? -- Duane.
1442 @item @b{ft2232_serial} <@var{serial-number}>
1443 @cindex ft2232_serial
1444 @*The serial number of the FTDI FT2232 device. If not specified, the FTDI default
1446 @item @b{ft2232_layout} <@var{name}>
1447 @cindex ft2232_layout
1448 @*The layout of the FT2232 GPIO signals used to control output-enables and reset
1449 signals. Valid layouts are
1452 "USBJTAG-1" layout described in the original OpenOCD diploma thesis
1454 Amontec JTAGkey and JTAGkey-Tiny
1455 @item @b{signalyzer}
1457 @item @b{olimex-jtag}
1460 American Microsystems M5960
1461 @item @b{evb_lm3s811}
1462 Luminary Micro EVB_LM3S811 as a JTAG interface (not onboard processor), no TRST or
1463 SRST signals on external connector
1466 @item @b{stm32stick}
1467 Hitex STM32 Performance Stick
1468 @item @b{flyswatter}
1469 Tin Can Tools Flyswatter
1470 @item @b{turtelizer2}
1471 egnite Software turtelizer2
1474 @item @b{axm0432_jtag}
1477 Hitex Cortino JTAG interface
1480 @item @b{ft2232_vid_pid} <@var{vid}> <@var{pid}>
1481 @*The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
1482 default values are used. Multiple <@var{vid}>, <@var{pid}> pairs may be given, e.g.
1484 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
1486 @item @b{ft2232_latency} <@var{ms}>
1487 @*On some systems using FT2232 based JTAG interfaces the FT_Read function call in
1488 ft2232_read() fails to return the expected number of bytes. This can be caused by
1489 USB communication delays and has proved hard to reproduce and debug. Setting the
1490 FT2232 latency timer to a larger value increases delays for short USB packets but it
1491 also reduces the risk of timeouts before receiving the expected number of bytes.
1492 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
1495 @subsection ep93xx options
1496 @cindex ep93xx options
1497 Currently, there are no options available for the ep93xx interface.
1501 JTAG clock setup is part of system setup.
1502 It @emph{does not belong with interface setup} since any interface
1503 only knows a few of the constraints for the JTAG clock speed.
1504 Sometimes the JTAG speed is
1505 changed during the target initialization process: (1) slow at
1506 reset, (2) program the CPU clocks, (3) run fast.
1507 Both the "slow" and "fast" clock rates are functions of the
1508 oscillators used, the chip, the board design, and sometimes
1509 power management software that may be active.
1511 The speed used during reset can be adjusted using pre_reset
1512 and post_reset event handlers.
1513 @xref{Target Events}.
1515 If your system supports adaptive clocking (RTCK), configuring
1516 JTAG to use that is probably the most robust approach.
1517 However, it introduces delays to synchronize clocks; so it
1518 may not be the fastest solution.
1520 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
1521 instead of @command{jtag_khz}.
1523 @deffn {Command} jtag_khz max_speed_kHz
1524 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
1525 JTAG interfaces usually support a limited number of
1526 speeds. The speed actually used won't be faster
1527 than the speed specified.
1529 As a rule of thumb, if you specify a clock rate make
1530 sure the JTAG clock is no more than @math{1/6th CPU-Clock}.
1531 This is especially true for synthesized cores (ARMxxx-S).
1533 Speed 0 (khz) selects RTCK method.
1535 If your system uses RTCK, you won't need to change the
1536 JTAG clocking after setup.
1537 Not all interfaces, boards, or targets support ``rtck''.
1538 If the interface device can not
1539 support it, an error is returned when you try to use RTCK.
1542 @defun jtag_rclk fallback_speed_kHz
1544 This Tcl proc (defined in startup.tcl) attempts to enable RTCK/RCLK.
1545 If that fails (maybe the interface, board, or target doesn't
1546 support it), falls back to the specified frequency.
1548 # Fall back to 3mhz if RTCK is not supported
1553 @node Reset Configuration
1554 @chapter Reset Configuration
1555 @cindex Reset Configuration
1557 Every system configuration may require a different reset
1558 configuration. This can also be quite confusing.
1559 Please see the various board files for examples.
1561 @b{Note} to maintainers and integrators:
1562 Reset configuration touches several things at once.
1563 Normally the board configuration file
1564 should define it and assume that the JTAG adapter supports
1565 everything that's wired up to the board's JTAG connector.
1566 However, the target configuration file could also make note
1567 of something the silicon vendor has done inside the chip,
1568 which will be true for most (or all) boards using that chip.
1569 And when the JTAG adapter doesn't support everything, the
1570 system configuration file will need to override parts of
1571 the reset configuration provided by other files.
1573 @section Types of Reset
1575 There are many kinds of reset possible through JTAG, but
1576 they may not all work with a given board and adapter.
1577 That's part of why reset configuration can be error prone.
1581 @emph{System Reset} ... the @emph{SRST} hardware signal
1582 resets all chips connected to the JTAG adapter, such as processors,
1583 power management chips, and I/O controllers. Normally resets triggered
1584 with this signal behave exactly like pressing a RESET button.
1586 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
1587 just the TAP controllers connected to the JTAG adapter.
1588 Such resets should not be visible to the rest of the system; resetting a
1589 device's the TAP controller just puts that controller into a known state.
1591 @emph{Emulation Reset} ... many devices can be reset through JTAG
1592 commands. These resets are often distinguishable from system
1593 resets, either explicitly (a "reset reason" register says so)
1594 or implicitly (not all parts of the chip get reset).
1596 @emph{Other Resets} ... system-on-chip devices often support
1597 several other types of reset.
1598 You may need to arrange that a watchdog timer stops
1599 while debugging, preventing a watchdog reset.
1600 There may be individual module resets.
1603 In the best case, OpenOCD can hold SRST, then reset
1604 the TAPs via TRST and send commands through JTAG to halt the
1605 CPU at the reset vector before the 1st instruction is executed.
1606 Then when it finally releases the SRST signal, the system is
1607 halted under debugger control before any code has executed.
1608 This is the behavior required to support the @command{reset halt}
1609 and @command{reset init} commands; after @command{reset init} a
1610 board-specific script might do things like setting up DRAM.
1611 (@xref{Reset Command}.)
1613 @section SRST and TRST Signal Issues
1615 Because SRST and TRST are hardware signals, they can have a
1616 variety of system-specific constraints. Some of the most
1621 @item @emph{Signal not available} ... Some boards don't wire
1622 SRST or TRST to the JTAG connector. Some JTAG adapters don't
1623 support such signals even if they are wired up.
1624 Use the @command{reset_config} @var{signals} options to say
1625 when one of those signals is not connected.
1626 When SRST is not available, your code might not be able to rely
1627 on controllers having been fully reset during code startup.
1629 @item @emph{Signals shorted} ... Sometimes a chip, board, or
1630 adapter will connect SRST to TRST, instead of keeping them separate.
1631 Use the @command{reset_config} @var{combination} options to say
1632 when those signals aren't properly independent.
1634 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
1635 delay circuit, reset supervisor, or on-chip features can extend
1636 the effect of a JTAG adapter's reset for some time after the adapter
1637 stops issuing the reset. For example, there may be chip or board
1638 requirements that all reset pulses last for at least a
1639 certain amount of time; and reset buttons commonly have
1640 hardware debouncing.
1641 Use the @command{jtag_nsrst_delay} and @command{jtag_ntrst_delay}
1642 commands to say when extra delays are needed.
1644 @item @emph{Drive type} ... Reset lines often have a pullup
1645 resistor, letting the JTAG interface treat them as open-drain
1646 signals. But that's not a requirement, so the adapter may need
1647 to use push/pull output drivers.
1648 Also, with weak pullups it may be advisable to drive
1649 signals to both levels (push/pull) to minimize rise times.
1650 Use the @command{reset_config} @var{trst_type} and
1651 @var{srst_type} parameters to say how to drive reset signals.
1654 There can also be other issues.
1655 Some devices don't fully conform to the JTAG specifications.
1656 Others have chip-specific extensions like extra steps needed
1657 during TAP reset, or a requirement to use the normally-optional TRST
1659 Trivial system-specific differences are common, such as
1660 SRST and TRST using slightly different names.
1662 @section Commands for Handling Resets
1664 @deffn {Command} jtag_nsrst_delay milliseconds
1665 How long (in milliseconds) OpenOCD should wait after deasserting
1666 nSRST (active-low system reset) before starting new JTAG operations.
1667 When a board has a reset button connected to SRST line it will
1668 probably have hardware debouncing, implying you should use this.
1671 @deffn {Command} jtag_ntrst_delay milliseconds
1672 How long (in milliseconds) OpenOCD should wait after deasserting
1673 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
1676 @deffn {Command} reset_config signals [combination [trst_type [srst_type]]]
1677 This command tells OpenOCD the reset configuration
1678 of your combination of JTAG interface, board, and target.
1679 If the JTAG interface provides SRST, but the board doesn't connect
1680 that signal properly, then OpenOCD can't use it. @var{signals} can
1681 be @option{none}, @option{trst_only}, @option{srst_only} or
1682 @option{trst_and_srst}.
1684 The @var{combination} is an optional value specifying broken reset
1685 signal implementations. @option{srst_pulls_trst} states that the
1686 test logic is reset together with the reset of the system (e.g. Philips
1687 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
1688 the system is reset together with the test logic (only hypothetical, I
1689 haven't seen hardware with such a bug, and can be worked around).
1690 @option{combined} implies both @option{srst_pulls_trst} and
1691 @option{trst_pulls_srst}. The default behaviour if no option given is
1694 The optional @var{trst_type} and @var{srst_type} parameters allow the
1695 driver type of the reset lines to be specified. Possible values are
1696 @option{trst_push_pull} (default) and @option{trst_open_drain} for the
1697 test reset signal, and @option{srst_open_drain} (default) and
1698 @option{srst_push_pull} for the system reset. These values only affect
1699 JTAG interfaces with support for different drivers, like the Amontec
1700 JTAGkey and JTAGAccelerator.
1705 @chapter Tap Creation
1706 @cindex tap creation
1707 @cindex tap configuration
1709 In order for OpenOCD to control a target, a JTAG tap must be
1712 Commands to create taps are normally found in a configuration file and
1713 are not normally typed by a human.
1715 When a tap is created a @b{dotted.name} is created for the tap. Other
1716 commands use that dotted.name to manipulate or refer to the tap.
1720 @item @b{Debug Target} A tap can be used by a GDB debug target
1721 @item @b{Flash Programing} Some chips program the flash directly via JTAG,
1722 instead of indirectly by making a CPU do it.
1723 @item @b{Boundry Scan} Some chips support boundary scan.
1727 @section jtag newtap
1728 @b{@t{jtag newtap CHIPNAME TAPNAME configparams ....}}
1733 @cindex tap geometry
1735 @comment START options
1738 @* is a symbolic name of the chip.
1740 @* is a symbol name of a tap present on the chip.
1741 @item @b{Required configparams}
1742 @* Every tap has 3 required configparams, and several ``optional
1743 parameters'', the required parameters are:
1744 @comment START REQUIRED
1746 @item @b{-irlen NUMBER} - the length in bits of the instruction register, mostly 4 or 5 bits.
1747 @item @b{-ircapture NUMBER} - the IDCODE capture command, usually 0x01.
1748 @item @b{-irmask NUMBER} - the corresponding mask for the IR register. For
1749 some devices, there are bits in the IR that aren't used. This lets you mask
1750 them off when doing comparisons. In general, this should just be all ones for
1752 @comment END REQUIRED
1754 An example of a FOOBAR Tap
1756 jtag newtap foobar tap -irlen 7 -ircapture 0x42 -irmask 0x55
1758 Creates the tap ``foobar.tap'' with the instruction register (IR) is 7
1759 bits long, during Capture-IR 0x42 is loaded into the IR, and bits
1760 [6,4,2,0] are checked.
1762 @item @b{Optional configparams}
1763 @comment START Optional
1765 @item @b{-expected-id NUMBER}
1766 @* By default it is zero. If non-zero represents the
1767 expected tap ID used when the JTAG chain is examined. Repeat
1768 the option as many times as required if multiple id's can be
1769 expected. See below.
1772 @* By default not specified the tap is enabled. Some chips have a
1773 JTAG route controller (JRC) that is used to enable and/or disable
1774 specific JTAG taps. You can later enable or disable any JTAG tap via
1775 the command @b{jtag tapenable DOTTED.NAME} or @b{jtag tapdisable
1777 @comment END Optional
1780 @comment END OPTIONS
1783 @comment START NOTES
1785 @item @b{Technically}
1786 @* newtap is a sub command of the ``jtag'' command
1787 @item @b{Big Picture Background}
1788 @*GDB Talks to OpenOCD using the GDB protocol via
1789 TCP/IP. OpenOCD then uses the JTAG interface (the dongle) to
1790 control the JTAG chain on your board. Your board has one or more chips
1791 in a @i{daisy chain configuration}. Each chip may have one or more
1792 JTAG taps. GDB ends up talking via OpenOCD to one of the taps.
1793 @item @b{NAME Rules}
1794 @*Names follow ``C'' symbol name rules (start with alpha ...)
1795 @item @b{TAPNAME - Conventions}
1797 @item @b{tap} - should be used only FPGA or CPLD like devices with a single tap.
1798 @item @b{cpu} - the main CPU of the chip, alternatively @b{foo.arm} and @b{foo.dsp}
1799 @item @b{flash} - if the chip has a flash tap, example: str912.flash
1800 @item @b{bs} - for boundary scan if this is a seperate tap.
1801 @item @b{etb} - for an embedded trace buffer (example: an ARM ETB11)
1802 @item @b{jrc} - for JTAG route controller (example: OMAP3530 found on Beagleboards)
1803 @item @b{unknownN} - where N is a number if you have no idea what the tap is for
1804 @item @b{Other names} - Freescale IMX31 has a SDMA (smart dma) with a JTAG tap, that tap should be called the ``sdma'' tap.
1805 @item @b{When in doubt} - use the chip maker's name in their data sheet.
1807 @item @b{DOTTED.NAME}
1808 @* @b{CHIPNAME}.@b{TAPNAME} creates the tap name, aka: the
1809 @b{Dotted.Name} is the @b{CHIPNAME} and @b{TAPNAME} combined with a
1810 dot (period); for example: @b{xilinx.tap}, @b{str912.flash},
1811 @b{omap3530.jrc}, or @b{stm32.cpu} The @b{dotted.name} is used in
1812 numerous other places to refer to various taps.
1814 @* The order this command appears via the config files is
1816 @item @b{Multi Tap Example}
1817 @* This example is based on the ST Microsystems STR912. See the ST
1818 document titled: @b{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
1819 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
1821 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}
1822 @*@b{checked: 28/nov/2008}
1824 The diagram shows that the TDO pin connects to the flash tap, flash TDI
1825 connects to the CPU debug tap, CPU TDI connects to the boundary scan
1826 tap which then connects to the TDI pin.
1830 # create tap: 'str912.flash'
1831 jtag newtap str912 flash ... params ...
1832 # create tap: 'str912.cpu'
1833 jtag newtap str912 cpu ... params ...
1834 # create tap: 'str912.bs'
1835 jtag newtap str912 bs ... params ...
1838 @item @b{Note: Deprecated} - Index Numbers
1839 @* Prior to 28/nov/2008, JTAG taps where numbered from 0..N this
1840 feature is still present, however its use is highly discouraged and
1841 should not be counted upon. Update all of your scripts to use
1842 TAP names rather than numbers.
1843 @item @b{Multiple chips}
1844 @* If your board has multiple chips, you should be
1845 able to @b{source} two configuration files, in the proper order, and
1846 have the taps created in the proper order.
1849 @comment at command level
1850 @comment DOCUMENT old command
1851 @section jtag_device - REMOVED
1853 @b{jtag_device} <@var{IR length}> <@var{IR capture}> <@var{IR mask}> <@var{IDCODE instruction}>
1857 @* @b{Removed: 28/nov/2008} This command has been removed and replaced
1858 by the ``jtag newtap'' command. The documentation remains here so that
1859 one can easily convert the old syntax to the new syntax. About the old
1860 syntax: The old syntax is positional, i.e.: The 3rd parameter is the
1861 ``irmask''. The new syntax requires named prefixes, and supports
1862 additional options, for example ``-expected-id 0x3f0f0f0f''. Please refer to the
1863 @b{jtag newtap} command for details.
1865 OLD: jtag_device 8 0x01 0xe3 0xfe
1866 NEW: jtag newtap CHIPNAME TAPNAME -irlen 8 -ircapture 0x01 -irmask 0xe3
1869 @section Enable/Disable Taps
1870 @b{Note:} These commands are intended to be used as a machine/script
1871 interface. Humans might find the ``scan_chain'' command more helpful
1872 when querying the state of the JTAG taps.
1874 @b{By default, all taps are enabled}
1877 @item @b{jtag tapenable} @var{DOTTED.NAME}
1878 @item @b{jtag tapdisable} @var{DOTTED.NAME}
1879 @item @b{jtag tapisenabled} @var{DOTTED.NAME}
1884 @cindex route controller
1886 These commands are used when your target has a JTAG route controller
1887 that effectively adds or removes a tap from the JTAG chain in a
1890 The ``standard way'' to remove a tap would be to place the tap in
1891 bypass mode. But with the advent of modern chips, this is not always a
1892 good solution. Some taps operate slowly, others operate fast, and
1893 there are other JTAG clock synchronisation problems one must face. To
1894 solve that problem, the JTAG route controller was introduced. Rather
1895 than ``bypass'' the tap, the tap is completely removed from the
1896 circuit and skipped.
1899 From OpenOCD's point of view, a JTAG tap is in one of 3 states:
1902 @item @b{Enabled - Not In ByPass} and has a variable bit length
1903 @item @b{Enabled - In ByPass} and has a length of exactly 1 bit.
1904 @item @b{Disabled} and has a length of ZERO and is removed from the circuit.
1907 The IEEE JTAG definition has no concept of a ``disabled'' tap.
1908 @b{Historical note:} this feature was added 28/nov/2008
1910 @b{jtag tapisenabled DOTTED.NAME}
1912 This command returns 1 if the named tap is currently enabled, 0 if not.
1913 This command exists so that scripts that manipulate a JRC (like the
1914 OMAP3530 has) can determine if OpenOCD thinks a tap is presently
1915 enabled or disabled.
1918 @node Target Configuration
1919 @chapter Target Configuration
1922 This chapter discusses how to create a GDB debug target. Before
1923 creating a ``target'' a JTAG tap DOTTED.NAME must exist first.
1925 @section targets [NAME]
1926 @b{Note:} This command name is PLURAL - not singular.
1928 With NO parameter, this plural @b{targets} command lists all known
1929 targets in a human friendly form.
1931 With a parameter, this plural @b{targets} command sets the current
1932 target to the given name. (i.e.: If there are multiple debug targets)
1937 CmdName Type Endian ChainPos State
1938 -- ---------- ---------- ---------- -------- ----------
1939 0: target0 arm7tdmi little 0 halted
1942 @section target COMMANDS
1943 @b{Note:} This command name is SINGULAR - not plural. It is used to
1944 manipulate specific targets, to create targets and other things.
1946 Once a target is created, a TARGETNAME (object) command is created;
1947 see below for details.
1949 The TARGET command accepts these sub-commands:
1951 @item @b{create} .. parameters ..
1952 @* creates a new target, see below for details.
1954 @* Lists all supported target types (perhaps some are not yet in this document).
1956 @* Lists all current debug target names, for example: 'str912.cpu' or 'pxa27.cpu' example usage:
1958 foreach t [target names] {
1959 puts [format "Target: %s\n" $t]
1963 @* Returns the current target. OpenOCD always has, or refers to the ``current target'' in some way.
1964 By default, commands like: ``mww'' (used to write memory) operate on the current target.
1965 @item @b{number} @b{NUMBER}
1966 @* Internally OpenOCD maintains a list of targets - in numerical index
1967 (0..N-1) this command returns the name of the target at index N.
1970 set thename [target number $x]
1971 puts [format "Target %d is: %s\n" $x $thename]
1974 @* Returns the number of targets known to OpenOCD (see number above)
1977 set c [target count]
1978 for { set x 0 } { $x < $c } { incr x } {
1979 # Assuming you have created this function
1980 print_target_details $x
1986 @section TARGETNAME (object) commands
1987 @b{Use:} Once a target is created, an ``object name'' that represents the
1988 target is created. By convention, the target name is identical to the
1989 tap name. In a multiple target system, one can preceed many common
1990 commands with a specific target name and effect only that target.
1992 str912.cpu mww 0x1234 0x42
1993 omap3530.cpu mww 0x5555 123
1996 @b{Model:} The Tcl/Tk language has the concept of object commands. A
1997 good example is a on screen button, once a button is created a button
1998 has a name (a path in Tk terms) and that name is useable as a 1st
1999 class command. For example in Tk, one can create a button and later
2000 configure it like this:
2004 button .foobar -background red -command @{ foo @}
2006 .foobar configure -foreground blue
2008 set x [.foobar cget -background]
2010 puts [format "The button is %s" $x]
2013 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
2014 button. Commands available as a ``target object'' are:
2016 @comment START targetobj commands.
2018 @item @b{configure} - configure the target; see Target Config/Cget Options below
2019 @item @b{cget} - query the target configuration; see Target Config/Cget Options below
2020 @item @b{curstate} - current target state (running, halt, etc.
2022 @* Intended for a human to see/read the currently configure target events.
2023 @item @b{Various Memory Commands} See the ``mww'' command elsewhere.
2024 @comment start memory
2034 @item @b{Memory To Array, Array To Memory}
2035 @* These are aimed at a machine interface to memory
2037 @item @b{mem2array ARRAYNAME WIDTH ADDRESS COUNT}
2038 @item @b{array2mem ARRAYNAME WIDTH ADDRESS COUNT}
2040 @* @b{ARRAYNAME} is the name of an array variable
2041 @* @b{WIDTH} is 8/16/32 - indicating the memory access size
2042 @* @b{ADDRESS} is the target memory address
2043 @* @b{COUNT} is the number of elements to process
2045 @item @b{Used during ``reset''}
2046 @* These commands are used internally by the OpenOCD scripts to deal
2047 with odd reset situations and are not documented here.
2049 @item @b{arp_examine}
2053 @item @b{arp_waitstate}
2055 @item @b{invoke-event} @b{EVENT-NAME}
2056 @* Invokes the specific event manually for the target
2059 @section Target Events
2061 @anchor{Target Events}
2062 At various times, certain things can happen, or you want them to happen.
2066 @item What should happen when GDB connects? Should your target reset?
2067 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
2068 @item During reset, do you need to write to certain memory location to reconfigure the SDRAM?
2071 All of the above items are handled by target events.
2073 To specify an event action, either during target creation, or later
2074 via ``$_TARGETNAME configure'' see this example.
2076 Syntactially, the option is: ``-event NAME BODY'' where NAME is a
2077 target event name, and BODY is a Tcl procedure or string of commands
2080 The programmers model is the ``-command'' option used in Tcl/Tk
2081 buttons and events. Below are two identical examples, the first
2082 creates and invokes small procedure. The second inlines the procedure.
2085 proc my_attach_proc @{ @} @{
2089 mychip.cpu configure -event gdb-attach my_attach_proc
2090 mychip.cpu configure -event gdb-attach @{ puts "Reset..." ; reset halt @}
2093 @section Current Events
2094 The following events are available:
2096 @item @b{debug-halted}
2097 @* The target has halted for debug reasons (i.e.: breakpoint)
2098 @item @b{debug-resumed}
2099 @* The target has resumed (i.e.: gdb said run)
2100 @item @b{early-halted}
2101 @* Occurs early in the halt process
2102 @item @b{examine-end}
2103 @* Currently not used (goal: when JTAG examine completes)
2104 @item @b{examine-start}
2105 @* Currently not used (goal: when JTAG examine starts)
2106 @item @b{gdb-attach}
2107 @* When GDB connects
2108 @item @b{gdb-detach}
2109 @* When GDB disconnects
2111 @* When the taret has halted and GDB is not doing anything (see early halt)
2112 @item @b{gdb-flash-erase-start}
2113 @* Before the GDB flash process tries to erase the flash
2114 @item @b{gdb-flash-erase-end}
2115 @* After the GDB flash process has finished erasing the flash
2116 @item @b{gdb-flash-write-start}
2117 @* Before GDB writes to the flash
2118 @item @b{gdb-flash-write-end}
2119 @* After GDB writes to the flash
2121 @* Before the taret steps, gdb is trying to start/resume the target
2123 @* The target has halted
2124 @item @b{old-gdb_program_config}
2125 @* DO NOT USE THIS: Used internally
2126 @item @b{old-pre_resume}
2127 @* DO NOT USE THIS: Used internally
2128 @item @b{reset-assert-pre}
2129 @* Before reset is asserted on the tap.
2130 @item @b{reset-assert-post}
2131 @* Reset is now asserted on the tap.
2132 @item @b{reset-deassert-pre}
2133 @* Reset is about to be released on the tap
2134 @item @b{reset-deassert-post}
2135 @* Reset has been released on the tap
2137 @* Currently not used.
2138 @item @b{reset-halt-post}
2139 @* Currently not usd
2140 @item @b{reset-halt-pre}
2141 @* Currently not used
2142 @item @b{reset-init}
2143 @* Used by @b{reset init} command for board-specific initialization.
2144 This is where you would configure PLLs and clocking, set up DRAM so
2145 you can download programs that don't fit in on-chip SRAM, set up pin
2146 multiplexing, and so on.
2147 @item @b{reset-start}
2148 @* Currently not used
2149 @item @b{reset-wait-pos}
2150 @* Currently not used
2151 @item @b{reset-wait-pre}
2152 @* Currently not used
2153 @item @b{resume-start}
2154 @* Before any target is resumed
2155 @item @b{resume-end}
2156 @* After all targets have resumed
2160 @* Target has resumed
2161 @item @b{tap-enable}
2162 @* Executed by @b{jtag tapenable DOTTED.NAME} command. Example:
2164 jtag configure DOTTED.NAME -event tap-enable @{
2169 @item @b{tap-disable}
2170 @*Executed by @b{jtag tapdisable DOTTED.NAME} command. Example:
2172 jtag configure DOTTED.NAME -event tap-disable @{
2173 puts "Disabling CPU"
2179 @section Target Create
2180 @anchor{Target Create}
2182 @cindex target creation
2185 @b{target} @b{create} <@var{NAME}> <@var{TYPE}> <@var{PARAMS ...}>
2187 @*This command creates a GDB debug target that refers to a specific JTAG tap.
2188 @comment START params
2191 @* Is the name of the debug target. By convention it should be the tap
2192 DOTTED.NAME. This name is also used to create the target object
2193 command, and in other places the target needs to be identified.
2195 @* Specifies the target type, i.e.: ARM7TDMI, or Cortex-M3. Currently supported targets are:
2196 @comment START types
2213 @*PARAMs are various target configuration parameters. The following ones are mandatory:
2214 @comment START mandatory
2216 @item @b{-endian big|little}
2217 @item @b{-chain-position DOTTED.NAME}
2218 @comment end MANDATORY
2223 @section Target Config/Cget Options
2224 These options can be specified when the target is created, or later
2225 via the configure option or to query the target via cget.
2227 You should specify a working area if you can; typically it uses some
2228 on-chip SRAM. Such a working area can speed up many things, including bulk
2229 writes to target memory; flash operations like checking to see if memory needs
2230 to be erased; GDB memory checksumming; and may help perform otherwise
2231 unavailable operations (like some coprocessor operations on ARM7/9 systems).
2233 @item @b{-type} - returns the target type
2234 @item @b{-event NAME BODY} see Target events
2235 @item @b{-work-area-virt [ADDRESS]} specify/set the work area base address
2236 which will be used when an MMU is active.
2237 @item @b{-work-area-phys [ADDRESS]} specify/set the work area base address
2238 which will be used when an MMU is inactive.
2239 @item @b{-work-area-size [ADDRESS]} specify/set the work area
2240 @item @b{-work-area-backup [0|1]} does the work area get backed up;
2241 by default, it doesn't. When possible, use a working_area that doesn't
2242 need to be backed up, since performing a backup slows down operations.
2243 @item @b{-endian [big|little]}
2244 @item @b{-variant [NAME]} some chips have variants OpenOCD needs to know about
2245 @item @b{-chain-position DOTTED.NAME} the tap name this target refers to.
2249 for @{ set x 0 @} @{ $x < [target count] @} @{ incr x @} @{
2250 set name [target number $x]
2251 set y [$name cget -endian]
2252 set z [$name cget -type]
2253 puts [format "Chip %d is %s, Endian: %s, type: %s" $x $y $z]
2257 @section Target Variants
2260 @* Unknown (please write me)
2262 @* Unknown (please write me) (similar to arm7tdmi)
2264 @* Variants: @option{arm920t}, @option{arm922t} and @option{arm940t}
2265 This enables the hardware single-stepping support found on these
2270 @* None (this is also used as the ARM946)
2272 @* use variant <@var{-variant lm3s}> when debugging Luminary lm3s targets. This will cause
2273 OpenOCD to use a software reset rather than asserting SRST to avoid a issue with clearing
2274 the debug registers. This is fixed in Fury Rev B, DustDevil Rev B, Tempest, these revisions will
2275 be detected and the normal reset behaviour used.
2277 @* Supported variants are @option{ixp42x}, @option{ixp45x}, @option{ixp46x},@option{pxa250}, @option{pxa255}, @option{pxa26x}.
2279 @* Supported variants are @option{arm1136}, @option{arm1156}, @option{arm1176}
2281 @* Use variant @option{ejtag_srst} when debugging targets that do not
2282 provide a functional SRST line on the EJTAG connector. This causes
2283 OpenOCD to instead use an EJTAG software reset command to reset the
2284 processor. You still need to enable @option{srst} on the reset
2285 configuration command to enable OpenOCD hardware reset functionality.
2286 @comment END variants
2288 @section working_area - Command Removed
2289 @cindex working_area
2290 @*@b{Please use the ``$_TARGETNAME configure -work-area-... parameters instead}
2291 @* This documentation remains because there are existing scripts that
2292 still use this that need to be converted.
2294 working_area target# address size backup| [virtualaddress]
2296 @* The target# is a the 0 based target numerical index.
2298 @node Flash Configuration
2299 @chapter Flash programming
2300 @cindex Flash Configuration
2302 OpenOCD has different commands for NOR and NAND flash;
2303 the ``flash'' command works with NOR flash, while
2304 the ``nand'' command works with NAND flash.
2305 This partially reflects different hardware technologies:
2306 NOR flash usually supports direct CPU instruction and data bus access,
2307 while data from a NAND flash must be copied to memory before it can be
2308 used. (SPI flash must also be copied to memory before use.)
2309 However, the documentation also uses ``flash'' as a generic term;
2310 for example, ``Put flash configuration in board-specific files''.
2312 @b{Note:} As of 28/nov/2008 OpenOCD does not know how to program a SPI
2313 flash that a micro may boot from. Perhaps you, the reader, would like to
2314 contribute support for this.
2318 @item Configure via the command @b{flash bank}
2319 @* Normally this is done in a configuration file.
2320 @item Operate on the flash via @b{flash SOMECOMMAND}
2321 @* Often commands to manipulate the flash are typed by a human, or run
2322 via a script in some automated way. For example: To program the boot
2323 flash on your board.
2325 @* Flashing via GDB requires the flash be configured via ``flash
2326 bank'', and the GDB flash features be enabled.
2327 @xref{GDB Configuration}.
2330 @section Flash commands
2331 @cindex Flash commands
2332 @subsection flash banks
2335 @*List configured flash banks
2336 @*@b{NOTE:} the singular form: 'flash bank' is used to configure the flash banks.
2337 @subsection flash info
2338 @b{flash info} <@var{num}>
2340 @*Print info about flash bank <@option{num}>
2341 @subsection flash probe
2342 @b{flash probe} <@var{num}>
2344 @*Identify the flash, or validate the parameters of the configured flash. Operation
2345 depends on the flash type.
2346 @subsection flash erase_check
2347 @b{flash erase_check} <@var{num}>
2348 @cindex flash erase_check
2349 @*Check erase state of sectors in flash bank <@var{num}>. This is the only operation that
2350 updates the erase state information displayed by @option{flash info}. That means you have
2351 to issue an @option{erase_check} command after erasing or programming the device to get
2352 updated information.
2353 @subsection flash protect_check
2354 @b{flash protect_check} <@var{num}>
2355 @cindex flash protect_check
2356 @*Check protection state of sectors in flash bank <num>.
2357 @option{flash erase_sector} using the same syntax.
2358 @subsection flash erase_sector
2359 @b{flash erase_sector} <@var{num}> <@var{first}> <@var{last}>
2360 @cindex flash erase_sector
2361 @anchor{flash erase_sector}
2362 @*Erase sectors at bank <@var{num}>, starting at sector <@var{first}> up to and including
2363 <@var{last}>. Sector numbering starts at 0. Depending on the flash type, erasing may
2364 require the protection to be disabled first (e.g. Intel Advanced Bootblock flash using
2366 @subsection flash erase_address
2367 @b{flash erase_address} <@var{address}> <@var{length}>
2368 @cindex flash erase_address
2369 @*Erase sectors starting at <@var{address}> for <@var{length}> bytes
2370 @subsection flash write_bank
2371 @b{flash write_bank} <@var{num}> <@var{file}> <@var{offset}>
2372 @cindex flash write_bank
2373 @anchor{flash write_bank}
2374 @*Write the binary <@var{file}> to flash bank <@var{num}>, starting at
2375 <@option{offset}> bytes from the beginning of the bank.
2376 @subsection flash write_image
2377 @b{flash write_image} [@var{erase}] <@var{file}> [@var{offset}] [@var{type}]
2378 @cindex flash write_image
2379 @anchor{flash write_image}
2380 @*Write the image <@var{file}> to the current target's flash bank(s). A relocation
2381 [@var{offset}] can be specified and the file [@var{type}] can be specified
2382 explicitly as @option{bin} (binary), @option{ihex} (Intel hex), @option{elf}
2383 (ELF file) or @option{s19} (Motorola s19). Flash memory will be erased prior to programming
2384 if the @option{erase} parameter is given.
2385 @subsection flash protect
2386 @b{flash protect} <@var{num}> <@var{first}> <@var{last}> <@option{on}|@option{off}>
2387 @cindex flash protect
2388 @*Enable (@var{on}) or disable (@var{off}) protection of flash sectors <@var{first}> to
2389 <@var{last}> of @option{flash bank} <@var{num}>.
2391 @subsection mFlash commands
2392 @cindex mFlash commands
2394 @item @b{mflash probe}
2395 @cindex mflash probe
2397 @item @b{mflash write} <@var{num}> <@var{file}> <@var{offset}>
2398 @cindex mflash write
2399 Write the binary <@var{file}> to mflash bank <@var{num}>, starting at
2400 <@var{offset}> bytes from the beginning of the bank.
2401 @item @b{mflash dump} <@var{num}> <@var{file}> <@var{offset}> <@var{size}>
2403 Dump <size> bytes, starting at <@var{offset}> bytes from the beginning of the <@var{num}> bank
2407 @section flash bank command
2408 The @b{flash bank} command is used to configure one or more flash chips (or banks in OpenOCD terms)
2411 @b{flash bank} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}>
2412 <@var{bus_width}> <@var{target}> [@var{driver_options ...}]
2415 @*Configures a flash bank at <@var{base}> of <@var{size}> bytes and <@var{chip_width}>
2416 and <@var{bus_width}> bytes using the selected flash <driver>.
2418 @subsection External Flash - cfi options
2420 CFI flashes are external flash chips - often they are connected to a
2421 specific chip select on the CPU. By default, at hard reset, most
2422 CPUs have the ablity to ``boot'' from some flash chip - typically
2423 attached to the CPU's CS0 pin.
2425 For other chip selects: OpenOCD does not know how to configure, or
2426 access a specific chip select. Instead you, the human, might need to
2427 configure additional chip selects via other commands (like: mww) , or
2428 perhaps configure a GPIO pin that controls the ``write protect'' pin
2431 @b{flash bank cfi} <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}>
2432 <@var{target}> [@var{jedec_probe}|@var{x16_as_x8}]
2433 @*CFI flashes require the name or number of the target they're connected to
2435 argument. The CFI driver makes use of a working area (specified for the target)
2436 to significantly speed up operation.
2438 @var{chip_width} and @var{bus_width} are specified in bytes.
2440 The @var{jedec_probe} option is used to detect certain non-CFI flash ROMs, like AM29LV010 and similar types.
2444 @subsection Internal Flash (Microcontrollers)
2445 @subsubsection lpc2000 options
2446 @cindex lpc2000 options
2448 @b{flash bank lpc2000} <@var{base}> <@var{size}> 0 0 <@var{target}> <@var{variant}>
2449 <@var{clock}> [@var{calc_checksum}]
2450 @*LPC flashes don't require the chip and bus width to be specified. Additional
2451 parameters are the <@var{variant}>, which may be @var{lpc2000_v1} (older LPC21xx and LPC22xx)
2452 or @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx),
2453 the name or number of the target this flash belongs to (first is 0),
2454 the frequency at which the core
2455 is currently running (in kHz - must be an integral number), and the optional keyword
2456 @var{calc_checksum}, telling the driver to calculate a valid checksum for the exception
2460 @subsubsection at91sam7 options
2461 @cindex at91sam7 options
2463 @b{flash bank at91sam7} 0 0 0 0 <@var{target}>
2464 @*AT91SAM7 flashes only require the @var{target}, all other values are looked up after
2465 reading the chip-id and type.
2467 @subsubsection str7 options
2468 @cindex str7 options
2470 @b{flash bank str7x} <@var{base}> <@var{size}> 0 0 <@var{target}> <@var{variant}>
2471 @*variant can be either STR71x, STR73x or STR75x.
2473 @subsubsection str9 options
2474 @cindex str9 options
2476 @b{flash bank str9x} <@var{base}> <@var{size}> 0 0 <@var{target}>
2477 @*The str9 needs the flash controller to be configured prior to Flash programming, e.g.
2479 str9x flash_config 0 4 2 0 0x80000
2481 This will setup the BBSR, NBBSR, BBADR and NBBADR registers respectively.
2483 @subsubsection str9 options (str9xpec driver)
2485 @b{flash bank str9xpec} <@var{base}> <@var{size}> 0 0 <@var{target}>
2486 @*Before using the flash commands the turbo mode must be enabled using str9xpec
2487 @option{enable_turbo} <@var{num>.}
2489 Only use this driver for locking/unlocking the device or configuring the option bytes.
2490 Use the standard str9 driver for programming. @xref{STR9 specific commands}.
2492 @subsubsection Stellaris (LM3Sxxx) options
2493 @cindex Stellaris (LM3Sxxx) options
2495 @b{flash bank stellaris} <@var{base}> <@var{size}> 0 0 <@var{target}>
2496 @*Stellaris flash plugin only require the @var{target}.
2498 @subsubsection stm32x options
2499 @cindex stm32x options
2501 @b{flash bank stm32x} <@var{base}> <@var{size}> 0 0 <@var{target}>
2502 @*stm32x flash plugin only require the @var{target}.
2504 @subsubsection aduc702x options
2505 @cindex aduc702x options
2507 @b{flash bank aduc702x} 0 0 0 0 <@var{target}>
2508 @*The aduc702x flash plugin works with Analog Devices model numbers ADUC7019 through ADUC7028. The setup command only requires the @var{target} argument (all devices in this family have the same memory layout).
2510 @subsection mFlash Configuration
2511 @cindex mFlash Configuration
2512 @b{mflash bank} <@var{soc}> <@var{base}> <@var{RST pin}> <@var{target}>
2514 @*Configures a mflash for <@var{soc}> host bank at
2515 <@var{base}>. Pin number format is dependent on host GPIO calling convention.
2516 Currently, mflash bank support s3c2440 and pxa270.
2518 (ex. of s3c2440) mflash <@var{RST pin}> is GPIO B1.
2520 mflash bank s3c2440 0x10000000 1b 0
2522 (ex. of pxa270) mflash <@var{RST pin}> is GPIO 43.
2524 mflash bank pxa270 0x08000000 43 0
2527 @section Microcontroller specific Flash Commands
2529 @subsection AT91SAM7 specific commands
2530 @cindex AT91SAM7 specific commands
2531 The flash configuration is deduced from the chip identification register. The flash
2532 controller handles erases automatically on a page (128/265 byte) basis, so erase is
2533 not necessary for flash programming. AT91SAM7 processors with less than 512K flash
2534 only have a single flash bank embedded on chip. AT91SAM7xx512 have two flash planes
2535 that can be erased separatly. Only an EraseAll command is supported by the controller
2536 for each flash plane and this is called with
2538 @item @b{flash erase} <@var{num}> @var{first_plane} @var{last_plane}
2539 @*bulk erase flash planes first_plane to last_plane.
2540 @item @b{at91sam7 gpnvm} <@var{num}> <@var{bit}> <@option{set}|@option{clear}>
2541 @cindex at91sam7 gpnvm
2542 @*set or clear a gpnvm bit for the processor
2545 @subsection STR9 specific commands
2546 @cindex STR9 specific commands
2547 @anchor{STR9 specific commands}
2548 These are flash specific commands when using the str9xpec driver.
2550 @item @b{str9xpec enable_turbo} <@var{num}>
2551 @cindex str9xpec enable_turbo
2552 @*enable turbo mode, will simply remove the str9 from the chain and talk
2553 directly to the embedded flash controller.
2554 @item @b{str9xpec disable_turbo} <@var{num}>
2555 @cindex str9xpec disable_turbo
2556 @*restore the str9 into JTAG chain.
2557 @item @b{str9xpec lock} <@var{num}>
2558 @cindex str9xpec lock
2559 @*lock str9 device. The str9 will only respond to an unlock command that will
2561 @item @b{str9xpec unlock} <@var{num}>
2562 @cindex str9xpec unlock
2563 @*unlock str9 device.
2564 @item @b{str9xpec options_read} <@var{num}>
2565 @cindex str9xpec options_read
2566 @*read str9 option bytes.
2567 @item @b{str9xpec options_write} <@var{num}>
2568 @cindex str9xpec options_write
2569 @*write str9 option bytes.
2572 Note: Before using the str9xpec driver here is some background info to help
2573 you better understand how the drivers works. OpenOCD has two flash drivers for
2577 Standard driver @option{str9x} programmed via the str9 core. Normally used for
2578 flash programming as it is faster than the @option{str9xpec} driver.
2580 Direct programming @option{str9xpec} using the flash controller. This is an
2581 ISC compilant (IEEE 1532) tap connected in series with the str9 core. The str9
2582 core does not need to be running to program using this flash driver. Typical use
2583 for this driver is locking/unlocking the target and programming the option bytes.
2586 Before we run any commands using the @option{str9xpec} driver we must first disable
2587 the str9 core. This example assumes the @option{str9xpec} driver has been
2588 configured for flash bank 0.
2590 # assert srst, we do not want core running
2591 # while accessing str9xpec flash driver
2593 # turn off target polling
2596 str9xpec enable_turbo 0
2598 str9xpec options_read 0
2599 # re-enable str9 core
2600 str9xpec disable_turbo 0
2604 The above example will read the str9 option bytes.
2605 When performing a unlock remember that you will not be able to halt the str9 - it
2606 has been locked. Halting the core is not required for the @option{str9xpec} driver
2607 as mentioned above, just issue the commands above manually or from a telnet prompt.
2609 @subsection STR9 configuration
2610 @cindex STR9 configuration
2612 @item @b{str9x flash_config} <@var{bank}> <@var{BBSR}> <@var{NBBSR}>
2613 <@var{BBADR}> <@var{NBBADR}>
2614 @cindex str9x flash_config
2615 @*Configure str9 flash controller.
2617 e.g. str9x flash_config 0 4 2 0 0x80000
2619 BBSR - Boot Bank Size register
2620 NBBSR - Non Boot Bank Size register
2621 BBADR - Boot Bank Start Address register
2622 NBBADR - Boot Bank Start Address register
2626 @subsection STR9 option byte configuration
2627 @cindex STR9 option byte configuration
2629 @item @b{str9xpec options_cmap} <@var{num}> <@option{bank0}|@option{bank1}>
2630 @cindex str9xpec options_cmap
2631 @*configure str9 boot bank.
2632 @item @b{str9xpec options_lvdthd} <@var{num}> <@option{2.4v}|@option{2.7v}>
2633 @cindex str9xpec options_lvdthd
2634 @*configure str9 lvd threshold.
2635 @item @b{str9xpec options_lvdsel} <@var{num}> <@option{vdd}|@option{vdd_vddq}>
2636 @cindex str9xpec options_lvdsel
2637 @*configure str9 lvd source.
2638 @item @b{str9xpec options_lvdwarn} <@var{bank}> <@option{vdd}|@option{vdd_vddq}>
2639 @cindex str9xpec options_lvdwarn
2640 @*configure str9 lvd reset warning source.
2643 @subsection STM32x specific commands
2644 @cindex STM32x specific commands
2646 These are flash specific commands when using the stm32x driver.
2648 @item @b{stm32x lock} <@var{num}>
2650 @*lock stm32 device.
2651 @item @b{stm32x unlock} <@var{num}>
2652 @cindex stm32x unlock
2653 @*unlock stm32 device.
2654 @item @b{stm32x options_read} <@var{num}>
2655 @cindex stm32x options_read
2656 @*read stm32 option bytes.
2657 @item @b{stm32x options_write} <@var{num}> <@option{SWWDG}|@option{HWWDG}>
2658 <@option{RSTSTNDBY}|@option{NORSTSTNDBY}> <@option{RSTSTOP}|@option{NORSTSTOP}>
2659 @cindex stm32x options_write
2660 @*write stm32 option bytes.
2661 @item @b{stm32x mass_erase} <@var{num}>
2662 @cindex stm32x mass_erase
2663 @*mass erase flash memory.
2666 @subsection Stellaris specific commands
2667 @cindex Stellaris specific commands
2669 These are flash specific commands when using the Stellaris driver.
2671 @item @b{stellaris mass_erase} <@var{num}>
2672 @cindex stellaris mass_erase
2673 @*mass erase flash memory.
2676 @node NAND Flash Commands
2677 @chapter NAND Flash Commands
2680 Compared to NOR or SPI flash, NAND devices are inexpensive
2681 and high density. Today's NAND chips, and multi-chip modules,
2682 commonly hold multiple GigaBytes of data.
2684 NAND chips consist of a number of ``erase blocks'' of a given
2685 size (such as 128 KBytes), each of which is divided into a
2686 number of pages (of perhaps 512 or 2048 bytes each). Each
2687 page of a NAND flash has an ``out of band'' (OOB) area to hold
2688 Error Correcting Code (ECC) and other metadata, usually 16 bytes
2689 of OOB for every 512 bytes of page data.
2691 One key characteristic of NAND flash is that its error rate
2692 is higher than that of NOR flash. In normal operation, that
2693 ECC is used to correct and detect errors. However, NAND
2694 blocks can also wear out and become unusable; those blocks
2695 are then marked "bad". NAND chips are even shipped from the
2696 manufacturer with a few bad blocks. The highest density chips
2697 use a technology (MLC) that wears out more quickly, so ECC
2698 support is increasingly important as a way to detect blocks
2699 that have begun to fail, and help to preserve data integrity
2700 with techniques such as wear leveling.
2702 Software is used to manage the ECC. Some controllers don't
2703 support ECC directly; in those cases, software ECC is used.
2704 Other controllers speed up the ECC calculations with hardware.
2705 Single-bit error correction hardware is routine. Controllers
2706 geared for newer MLC chips may correct 4 or more errors for
2707 every 512 bytes of data.
2709 You will need to make sure that any data you write using
2710 OpenOCD includes the apppropriate kind of ECC. For example,
2711 that may mean passing the @code{oob_softecc} flag when
2712 writing NAND data, or ensuring that the correct hardware
2715 The basic steps for using NAND devices include:
2717 @item Declare via the command @command{nand device}
2718 @* Do this in a board-specific configuration file,
2719 passing parameters as needed by the controller.
2720 @item Configure each device using @command{nand probe}.
2721 @* Do this only after the associated target is set up,
2722 such as in its reset-init script or in procures defined
2723 to access that device.
2724 @item Operate on the flash via @command{nand subcommand}
2725 @* Often commands to manipulate the flash are typed by a human, or run
2726 via a script in some automated way. Common task include writing a
2727 boot loader, operating system, or other data needed to initialize or
2731 @b{NOTE:} At the time this text was written, the largest NAND
2732 flash fully supported by OpenOCD is 2 GiBytes (16 GiBits).
2733 This is because the variables used to hold offsets and lengths
2734 are only 32 bits wide.
2735 (Larger chips may work in some cases, unless an offset or length
2736 is larger than 0xffffffff, the largest 32-bit unsigned integer.)
2737 Some larger devices will work, since they are actually multi-chip
2738 modules with two smaller chips and individual chipselect lines.
2740 @section NAND Configuration Commands
2741 @cindex NAND configuration
2743 NAND chips must be declared in configuration scripts,
2744 plus some additional configuration that's done after
2745 OpenOCD has initialized.
2747 @deffn {Config Command} {nand device} controller target [configparams...]
2748 Declares a NAND device, which can be read and written to
2749 after it has been configured through @command{nand probe}.
2750 In OpenOCD, devices are single chips; this is unlike some
2751 operating systems, which may manage multiple chips as if
2752 they were a single (larger) device.
2753 In some cases, configuring a device will activate extra
2754 commands; see the controller-specific documentation.
2756 @b{NOTE:} This command is not available after OpenOCD
2757 initialization has completed. Use it in board specific
2758 configuration files, not interactively.
2761 @item @var{controller} ... identifies a the controller driver
2762 associated with the NAND device being declared.
2763 @xref{NAND Driver List}.
2764 @item @var{target} ... names the target used when issuing
2765 commands to the NAND controller.
2766 @comment Actually, it's currently a controller-specific parameter...
2767 @item @var{configparams} ... controllers may support, or require,
2768 additional parameters. See the controller-specific documentation
2769 for more information.
2773 @deffn Command {nand list}
2774 Prints a one-line summary of each device declared
2775 using @command{nand device}, numbered from zero.
2776 Note that un-probed devices show no details.
2779 @deffn Command {nand probe} num
2780 Probes the specified device to determine key characteristics
2781 like its page and block sizes, and how many blocks it has.
2782 The @var{num} parameter is the value shown by @command{nand list}.
2783 You must (successfully) probe a device before you can use
2784 it with most other NAND commands.
2787 @section Erasing, Reading, Writing to NAND Flash
2789 @deffn Command {nand dump} num filename offset length [oob_option]
2790 @cindex NAND reading
2791 Reads binary data from the NAND device and writes it to the file,
2792 starting at the specified offset.
2793 The @var{num} parameter is the value shown by @command{nand list}.
2795 Use a complete path name for @var{filename}, so you don't depend
2796 on the directory used to start the OpenOCD server.
2798 The @var{offset} and @var{length} must be exact multiples of the
2799 device's page size. They describe a data region; the OOB data
2800 associated with each such page may also be accessed.
2802 @b{NOTE:} At the time this text was written, no error correction
2803 was done on the data that's read, unless raw access was disabled
2804 and the underlying NAND controller driver had a @code{read_page}
2805 method which handled that error correction.
2807 By default, only page data is saved to the specified file.
2808 Use an @var{oob_option} parameter to save OOB data:
2810 @item no oob_* parameter
2811 @*Output file holds only page data; OOB is discarded.
2812 @item @code{oob_raw}
2813 @*Output file interleaves page data and OOB data;
2814 the file will be longer than "length" by the size of the
2815 spare areas associated with each data page.
2816 Note that this kind of "raw" access is different from
2817 what's implied by @command{nand raw_access}, which just
2818 controls whether a hardware-aware access method is used.
2819 @item @code{oob_only}
2820 @*Output file has only raw OOB data, and will
2821 be smaller than "length" since it will contain only the
2822 spare areas associated with each data page.
2826 @deffn Command {nand erase} num offset length
2827 @cindex NAND erasing
2828 Erases blocks on the specified NAND device, starting at the
2829 specified @var{offset} and continuing for @var{length} bytes.
2830 Both of those values must be exact multiples of the device's
2831 block size, and the region they specify must fit entirely in the chip.
2832 The @var{num} parameter is the value shown by @command{nand list}.
2834 @b{NOTE:} This command will try to erase bad blocks, when told
2835 to do so, which will probably invalidate the manufacturer's bad
2837 For the remainder of the current server session, @command{nand info}
2838 will still report that the block ``is'' bad.
2841 @deffn Command {nand write} num filename offset [option...]
2842 @cindex NAND writing
2843 Writes binary data from the file into the specified NAND device,
2844 starting at the specified offset. Those pages should already
2845 have been erased; you can't change zero bits to one bits.
2846 The @var{num} parameter is the value shown by @command{nand list}.
2848 Use a complete path name for @var{filename}, so you don't depend
2849 on the directory used to start the OpenOCD server.
2851 The @var{offset} must be an exact multiple of the device's page size.
2852 All data in the file will be written, assuming it doesn't run
2853 past the end of the device.
2854 Only full pages are written, and any extra space in the last
2855 page will be filled with 0xff bytes. (That includes OOB data,
2856 if that's being written.)
2858 @b{NOTE:} At the time this text was written, bad blocks are
2859 ignored. That is, this routine will not skip bad blocks,
2860 but will instead try to write them. This can cause problems.
2862 Provide at most one @var{option} parameter. With some
2863 NAND drivers, the meanings of these parameters may change
2864 if @command{nand raw_access} was used to disable hardware ECC.
2866 @item no oob_* parameter
2867 @*File has only page data, which is written.
2868 If raw acccess is in use, the OOB area will not be written.
2869 Otherwise, if the underlying NAND controller driver has
2870 a @code{write_page} routine, that routine may write the OOB
2871 with hardware-computed ECC data.
2872 @item @code{oob_only}
2873 @*File has only raw OOB data, which is written to the OOB area.
2874 Each page's data area stays untouched. @i{This can be a dangerous
2875 option}, since it can invalidate the ECC data.
2876 You may need to force raw access to use this mode.
2877 @item @code{oob_raw}
2878 @*File interleaves data and OOB data, both of which are written
2879 If raw access is enabled, the data is written first, then the
2881 Otherwise, if the underlying NAND controller driver has
2882 a @code{write_page} routine, that routine may modify the OOB
2883 before it's written, to include hardware-computed ECC data.
2884 @item @code{oob_softecc}
2885 @*File has only page data, which is written.
2886 The OOB area is filled with 0xff, except for a standard 1-bit
2887 software ECC code stored in conventional locations.
2888 You might need to force raw access to use this mode, to prevent
2889 the underlying driver from applying hardware ECC.
2890 @item @code{oob_softecc_kw}
2891 @*File has only page data, which is written.
2892 The OOB area is filled with 0xff, except for a 4-bit software ECC
2893 specific to the boot ROM in Marvell Kirkwood SoCs.
2894 You might need to force raw access to use this mode, to prevent
2895 the underlying driver from applying hardware ECC.
2899 @section Other NAND commands
2900 @cindex NAND other commands
2902 @deffn Command {nand check_bad_blocks} [offset length]
2903 Checks for manufacturer bad block markers on the specified NAND
2904 device. If no parameters are provided, checks the whole
2905 device; otherwise, starts at the specified @var{offset} and
2906 continues for @var{length} bytes.
2907 Both of those values must be exact multiples of the device's
2908 block size, and the region they specify must fit entirely in the chip.
2909 The @var{num} parameter is the value shown by @command{nand list}.
2911 @b{NOTE:} Before using this command you should force raw access
2912 with @command{nand raw_access enable} to ensure that the underlying
2913 driver will not try to apply hardware ECC.
2916 @deffn Command {nand info} num
2917 The @var{num} parameter is the value shown by @command{nand list}.
2918 This prints the one-line summary from "nand list", plus for
2919 devices which have been probed this also prints any known
2920 status for each block.
2923 @deffn Command {nand raw_access} num <enable|disable>
2924 Sets or clears an flag affecting how page I/O is done.
2925 The @var{num} parameter is the value shown by @command{nand list}.
2927 This flag is cleared (disabled) by default, but changing that
2928 value won't affect all NAND devices. The key factor is whether
2929 the underlying driver provides @code{read_page} or @code{write_page}
2930 methods. If it doesn't provide those methods, the setting of
2931 this flag is irrelevant; all access is effectively ``raw''.
2933 When those methods exist, they are normally used when reading
2934 data (@command{nand dump} or reading bad block markers) or
2935 writing it (@command{nand write}). However, enabling
2936 raw access (setting the flag) prevents use of those methods,
2937 bypassing hardware ECC logic.
2938 @i{This can be a dangerous option}, since writing blocks
2939 with the wrong ECC data can cause them to be marked as bad.
2942 @section NAND Drivers; Driver-specific Options and Commands
2943 @anchor{NAND Driver List}
2944 As noted above, the @command{nand device} command allows
2945 driver-specific options and behaviors.
2946 Some controllers also activate controller-specific commands.
2948 @deffn {NAND Driver} davinci
2949 This driver handles the NAND controllers found on DaVinci family
2950 chips from Texas Instruments.
2951 It takes three extra parameters:
2952 address of the NAND chip;
2953 hardware ECC mode to use (hwecc1, hwecc4, hwecc4_infix);
2954 address of the AEMIF controller on this processor.
2956 nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000
2958 All DaVinci processors support the single-bit ECC hardware,
2959 and newer ones also support the four-bit ECC hardware.
2960 The @code{write_page} and @code{read_page} methods are used
2961 to implement those ECC modes, unless they are disabled using
2962 the @command{nand raw_access} command.
2965 @deffn {NAND Driver} lpc3180
2966 These controllers require an extra @command{nand device}
2967 parameter: the clock rate used by the controller.
2968 @deffn Command {nand lpc3180 select} num [mlc|slc]
2969 Configures use of the MLC or SLC controller mode.
2970 MLC implies use of hardware ECC.
2971 The @var{num} parameter is the value shown by @command{nand list}.
2974 At this writing, this driver includes @code{write_page}
2975 and @code{read_page} methods. Using @command{nand raw_access}
2976 to disable those methods will prevent use of hardware ECC
2977 in the MLC controller mode, but won't change SLC behavior.
2979 @comment current lpc3180 code won't issue 5-byte address cycles
2981 @deffn {NAND Driver} orion
2982 These controllers require an extra @command{nand device}
2983 parameter: the address of the controller.
2985 nand device orion 0xd8000000
2987 These controllers don't define any specialized commands.
2988 At this writing, their drivers don't include @code{write_page}
2989 or @code{read_page} methods, so @command{nand raw_access} won't
2990 change any behavior.
2993 @deffn {NAND Driver} {s3c2410, s3c2412, s3c2440, s3c2443}
2994 These S3C24xx family controllers don't have any special
2995 @command{nand device} options, and don't define any
2996 specialized commands.
2997 At this writing, their drivers don't include @code{write_page}
2998 or @code{read_page} methods, so @command{nand raw_access} won't
2999 change any behavior.
3002 @node General Commands
3003 @chapter General Commands
3006 The commands documented in this chapter here are common commands that
3007 you, as a human, may want to type and see the output of. Configuration type
3008 commands are documented elsewhere.
3012 @item @b{Source Of Commands}
3013 @* OpenOCD commands can occur in a configuration script (discussed
3014 elsewhere) or typed manually by a human or supplied programatically,
3015 or via one of several TCP/IP Ports.
3017 @item @b{From the human}
3018 @* A human should interact with the telnet interface (default port: 4444)
3019 or via GDB (default port 3333).
3021 To issue commands from within a GDB session, use the @option{monitor}
3022 command, e.g. use @option{monitor poll} to issue the @option{poll}
3023 command. All output is relayed through the GDB session.
3025 @item @b{Machine Interface}
3026 The Tcl interface's intent is to be a machine interface. The default Tcl
3031 @section Daemon Commands
3033 @subsection sleep [@var{msec}]
3035 @*Wait for n milliseconds before resuming. Useful in connection with script files
3036 (@var{script} command and @var{target_script} configuration).
3038 @subsection shutdown
3040 @*Close the OpenOCD daemon, disconnecting all clients (GDB, telnet, other).
3042 @subsection debug_level [@var{n}]
3044 @anchor{debug_level}
3045 @*Display or adjust debug level to n<0-3>
3047 @subsection fast [@var{enable|disable}]
3049 @*Default disabled. Set default behaviour of OpenOCD to be "fast and dangerous". For instance ARM7/9 DCC memory
3050 downloads and fast memory access will work if the JTAG interface isn't too fast and
3051 the core doesn't run at a too low frequency. Note that this option only changes the default
3052 and that the indvidual options, like DCC memory downloads, can be enabled and disabled
3055 The target specific "dangerous" optimisation tweaking options may come and go
3056 as more robust and user friendly ways are found to ensure maximum throughput
3057 and robustness with a minimum of configuration.
3059 Typically the "fast enable" is specified first on the command line:
3062 openocd -c "fast enable" -c "interface dummy" -f target/str710.cfg
3065 @subsection echo <@var{message}>
3067 @*Output message to stdio. e.g. echo "Programming - please wait"
3069 @subsection log_output <@var{file}>
3071 @*Redirect logging to <file> (default: stderr)
3073 @subsection script <@var{file}>
3075 @*Execute commands from <file>
3076 See also: ``source [find FILENAME]''
3078 @section Target state handling
3079 @subsection power <@var{on}|@var{off}>
3081 @*Turn power switch to target on/off.
3082 No arguments: print status.
3083 Not all interfaces support this.
3085 @subsection reg [@option{#}|@option{name}] [value]
3087 @*Access a single register by its number[@option{#}] or by its [@option{name}].
3088 No arguments: list all available registers for the current target.
3089 Number or name argument: display a register.
3090 Number or name and value arguments: set register value.
3092 @subsection poll [@option{on}|@option{off}]
3094 @*Poll the target for its current state. If the target is in debug mode, architecture
3095 specific information about the current state is printed. An optional parameter
3096 allows continuous polling to be enabled and disabled.
3098 @subsection halt [@option{ms}]
3100 @*Send a halt request to the target and wait for it to halt for up to [@option{ms}] milliseconds.
3101 Default [@option{ms}] is 5 seconds if no arg given.
3102 Optional arg @option{ms} is a timeout in milliseconds. Using 0 as the [@option{ms}]
3103 will stop OpenOCD from waiting.
3105 @subsection wait_halt [@option{ms}]
3107 @*Wait for the target to enter debug mode. Optional [@option{ms}] is
3108 a timeout in milliseconds. Default [@option{ms}] is 5 seconds if no
3111 @subsection resume [@var{address}]
3113 @*Resume the target at its current code position, or at an optional address.
3114 OpenOCD will wait 5 seconds for the target to resume.
3116 @subsection step [@var{address}]
3118 @*Single-step the target at its current code position, or at an optional address.
3120 @anchor{Reset Command}
3121 @subsection reset [@option{run}|@option{halt}|@option{init}]
3123 @*Perform a hard-reset. The optional parameter specifies what should
3124 happen after the reset.
3125 If there is no parameter, a @command{reset run} is executed.
3126 The other options will not work on all systems.
3127 @xref{Reset Configuration}.
3131 @*Let the target run.
3134 @*Immediately halt the target (works only with certain configurations).
3137 @*Immediately halt the target, and execute the reset script (works only with certain
3141 @subsection soft_reset_halt
3143 @*Requesting target halt and executing a soft reset. This is often used
3144 when a target cannot be reset and halted. The target, after reset is
3145 released begins to execute code. OpenOCD attempts to stop the CPU and
3146 then sets the program counter back to the reset vector. Unfortunately
3147 the code that was executed may have left the hardware in an unknown
3151 @section Memory access commands
3153 display available RAM memory.
3154 @subsection Memory peek/poke type commands
3155 These commands allow accesses of a specific size to the memory
3156 system. Often these are used to configure the current target in some
3157 special way. For example - one may need to write certian values to the
3158 SDRAM controller to enable SDRAM.
3161 @item To change the current target see the ``targets'' (plural) command
3162 @item In system level scripts these commands are deprecated, please use the TARGET object versions.
3166 @item @b{mdw} <@var{addr}> [@var{count}]
3168 @*display memory words (32bit)
3169 @item @b{mdh} <@var{addr}> [@var{count}]
3171 @*display memory half-words (16bit)
3172 @item @b{mdb} <@var{addr}> [@var{count}]
3174 @*display memory bytes (8bit)
3175 @item @b{mww} <@var{addr}> <@var{value}>
3177 @*write memory word (32bit)
3178 @item @b{mwh} <@var{addr}> <@var{value}>
3180 @*write memory half-word (16bit)
3181 @item @b{mwb} <@var{addr}> <@var{value}>
3183 @*write memory byte (8bit)
3186 @section Image loading commands
3187 @subsection load_image
3188 @b{load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
3191 @*Load image <@var{file}> to target memory at <@var{address}>
3192 @subsection fast_load_image
3193 @b{fast_load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
3194 @cindex fast_load_image
3195 @anchor{fast_load_image}
3196 @*Normally you should be using @b{load_image} or GDB load. However, for
3197 testing purposes or when I/O overhead is significant(OpenOCD running on an embedded
3198 host), storing the image in memory and uploading the image to the target
3199 can be a way to upload e.g. multiple debug sessions when the binary does not change.
3200 Arguments are the same as @b{load_image}, but the image is stored in OpenOCD host
3201 memory, i.e. does not affect target. This approach is also useful when profiling
3202 target programming performance as I/O and target programming can easily be profiled
3204 @subsection fast_load
3208 @*Loads an image stored in memory by @b{fast_load_image} to the current target. Must be preceeded by fast_load_image.
3209 @subsection dump_image
3210 @b{dump_image} <@var{file}> <@var{address}> <@var{size}>
3213 @*Dump <@var{size}> bytes of target memory starting at <@var{address}> to a
3214 (binary) <@var{file}>.
3215 @subsection verify_image
3216 @b{verify_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
3217 @cindex verify_image
3218 @*Verify <@var{file}> against target memory starting at <@var{address}>.
3219 This will first attempt a comparison using a CRC checksum, if this fails it will try a binary compare.
3222 @section Breakpoint commands
3223 @cindex Breakpoint commands
3225 @item @b{bp} <@var{addr}> <@var{len}> [@var{hw}]
3227 @*set breakpoint <address> <length> [hw]
3228 @item @b{rbp} <@var{addr}>
3230 @*remove breakpoint <adress>
3231 @item @b{wp} <@var{addr}> <@var{len}> <@var{r}|@var{w}|@var{a}> [@var{value}] [@var{mask}]
3233 @*set watchpoint <address> <length> <r/w/a> [value] [mask]
3234 @item @b{rwp} <@var{addr}>
3236 @*remove watchpoint <adress>
3239 @section Misc Commands
3240 @cindex Other Target Commands
3242 @item @b{profile} <@var{seconds}> <@var{gmon.out}>
3244 Profiling samples the CPU's program counter as quickly as possible, which is useful for non-intrusive stochastic profiling.
3248 @section Target Specific Commands
3249 @cindex Target Specific Commands
3253 @section Architecture Specific Commands
3254 @cindex Architecture Specific Commands
3256 @subsection ARMV4/5 specific commands
3257 @cindex ARMV4/5 specific commands
3259 These commands are specific to ARM architecture v4 and v5, like all ARM7/9 systems
3260 or Intel XScale (XScale isn't supported yet).
3262 @item @b{armv4_5 reg}
3264 @*Display a list of all banked core registers, fetching the current value from every
3265 core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
3267 @item @b{armv4_5 core_mode} [@var{arm}|@var{thumb}]
3268 @cindex armv4_5 core_mode
3269 @*Displays the core_mode, optionally changing it to either ARM or Thumb mode.
3270 The target is resumed in the currently set @option{core_mode}.
3273 @subsection ARM7/9 specific commands
3274 @cindex ARM7/9 specific commands
3276 These commands are specific to ARM7 and ARM9 targets, like ARM7TDMI, ARM720t,
3277 ARM920T or ARM926EJ-S.
3279 @item @b{arm7_9 dbgrq} <@var{enable}|@var{disable}>
3280 @cindex arm7_9 dbgrq
3281 @*Enable use of the DBGRQ bit to force entry into debug mode. This should be
3282 safe for all but ARM7TDMI--S cores (like Philips LPC).
3283 @item @b{arm7_9 fast_memory_access} <@var{enable}|@var{disable}>
3284 @cindex arm7_9 fast_memory_access
3285 @anchor{arm7_9 fast_memory_access}
3286 @*Allow OpenOCD to read and write memory without checking completion of
3287 the operation. This provides a huge speed increase, especially with USB JTAG
3288 cables (FT2232), but might be unsafe if used with targets running at very low
3289 speeds, like the 32kHz startup clock of an AT91RM9200.
3290 @item @b{arm7_9 dcc_downloads} <@var{enable}|@var{disable}>
3291 @cindex arm7_9 dcc_downloads
3292 @*Enable the use of the debug communications channel (DCC) to write larger (>128 byte)
3293 amounts of memory. DCC downloads offer a huge speed increase, but might be potentially
3294 unsafe, especially with targets running at very low speeds. This command was introduced
3295 with OpenOCD rev. 60, and requires a few bytes of working area.
3298 @subsection ARM720T specific commands
3299 @cindex ARM720T specific commands
3302 @item @b{arm720t cp15} <@var{num}> [@var{value}]
3303 @cindex arm720t cp15
3304 @*display/modify cp15 register <@option{num}> [@option{value}].
3305 @item @b{arm720t md<bhw>_phys} <@var{addr}> [@var{count}]
3306 @cindex arm720t md<bhw>_phys
3307 @*Display memory at physical address addr.
3308 @item @b{arm720t mw<bhw>_phys} <@var{addr}> <@var{value}>
3309 @cindex arm720t mw<bhw>_phys
3310 @*Write memory at physical address addr.
3311 @item @b{arm720t virt2phys} <@var{va}>
3312 @cindex arm720t virt2phys
3313 @*Translate a virtual address to a physical address.
3316 @subsection ARM9TDMI specific commands
3317 @cindex ARM9TDMI specific commands
3320 @item @b{arm9tdmi vector_catch} <@var{all}|@var{none}>
3321 @cindex arm9tdmi vector_catch
3322 @*Catch arm9 interrupt vectors, can be @option{all} @option{none} or any of the following:
3323 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt} @option{reserved}
3324 @option{irq} @option{fiq}.
3326 Can also be used on other ARM9 based cores such as ARM966, ARM920T and ARM926EJ-S.
3329 @subsection ARM966E specific commands
3330 @cindex ARM966E specific commands
3333 @item @b{arm966e cp15} <@var{num}> [@var{value}]
3334 @cindex arm966e cp15
3335 @*display/modify cp15 register <@option{num}> [@option{value}].
3338 @subsection ARM920T specific commands
3339 @cindex ARM920T specific commands
3342 @item @b{arm920t cp15} <@var{num}> [@var{value}]
3343 @cindex arm920t cp15
3344 @*display/modify cp15 register <@option{num}> [@option{value}].
3345 @item @b{arm920t cp15i} <@var{num}> [@var{value}] [@var{address}]
3346 @cindex arm920t cp15i
3347 @*display/modify cp15 (interpreted access) <@option{opcode}> [@option{value}] [@option{address}]
3348 @item @b{arm920t cache_info}
3349 @cindex arm920t cache_info
3350 @*Print information about the caches found. This allows to see whether your target
3351 is an ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
3352 @item @b{arm920t md<bhw>_phys} <@var{addr}> [@var{count}]
3353 @cindex arm920t md<bhw>_phys
3354 @*Display memory at physical address addr.
3355 @item @b{arm920t mw<bhw>_phys} <@var{addr}> <@var{value}>
3356 @cindex arm920t mw<bhw>_phys
3357 @*Write memory at physical address addr.
3358 @item @b{arm920t read_cache} <@var{filename}>
3359 @cindex arm920t read_cache
3360 @*Dump the content of ICache and DCache to a file.
3361 @item @b{arm920t read_mmu} <@var{filename}>
3362 @cindex arm920t read_mmu
3363 @*Dump the content of the ITLB and DTLB to a file.
3364 @item @b{arm920t virt2phys} <@var{va}>
3365 @cindex arm920t virt2phys
3366 @*Translate a virtual address to a physical address.
3369 @subsection ARM926EJ-S specific commands
3370 @cindex ARM926EJ-S specific commands
3373 @item @b{arm926ejs cp15} <@var{num}> [@var{value}]
3374 @cindex arm926ejs cp15
3375 @*display/modify cp15 register <@option{num}> [@option{value}].
3376 @item @b{arm926ejs cache_info}
3377 @cindex arm926ejs cache_info
3378 @*Print information about the caches found.
3379 @item @b{arm926ejs md<bhw>_phys} <@var{addr}> [@var{count}]
3380 @cindex arm926ejs md<bhw>_phys
3381 @*Display memory at physical address addr.
3382 @item @b{arm926ejs mw<bhw>_phys} <@var{addr}> <@var{value}>
3383 @cindex arm926ejs mw<bhw>_phys
3384 @*Write memory at physical address addr.
3385 @item @b{arm926ejs virt2phys} <@var{va}>
3386 @cindex arm926ejs virt2phys
3387 @*Translate a virtual address to a physical address.
3390 @subsection CORTEX_M3 specific commands
3391 @cindex CORTEX_M3 specific commands
3394 @item @b{cortex_m3 maskisr} <@var{on}|@var{off}>
3395 @cindex cortex_m3 maskisr
3396 @*Enable masking (disabling) interrupts during target step/resume.
3400 @section Debug commands
3401 @cindex Debug commands
3402 The following commands give direct access to the core, and are most likely
3403 only useful while debugging OpenOCD.
3405 @item @b{arm7_9 write_xpsr} <@var{32-bit value}> <@option{0=cpsr}, @option{1=spsr}>
3406 @cindex arm7_9 write_xpsr
3407 @*Immediately write either the current program status register (CPSR) or the saved
3408 program status register (SPSR), without changing the register cache (as displayed
3409 by the @option{reg} and @option{armv4_5 reg} commands).
3410 @item @b{arm7_9 write_xpsr_im8} <@var{8-bit value}> <@var{rotate 4-bit}>
3411 <@var{0=cpsr},@var{1=spsr}>
3412 @cindex arm7_9 write_xpsr_im8
3413 @*Write the 8-bit value rotated right by 2*rotate bits, using an immediate write
3414 operation (similar to @option{write_xpsr}).
3415 @item @b{arm7_9 write_core_reg} <@var{num}> <@var{mode}> <@var{value}>
3416 @cindex arm7_9 write_core_reg
3417 @*Write a core register, without changing the register cache (as displayed by the
3418 @option{reg} and @option{armv4_5 reg} commands). The <@var{mode}> argument takes the
3419 encoding of the [M4:M0] bits of the PSR.
3422 @section Target Requests
3423 @cindex Target Requests
3424 OpenOCD can handle certain target requests, currently debugmsg are only supported for arm7_9 and cortex_m3.
3425 See libdcc in the contrib dir for more details.
3427 @item @b{target_request debugmsgs} <@var{enable}|@var{disable}|@var{charmsg}>
3428 @cindex target_request debugmsgs
3429 @*Enable/disable target debugmsgs requests. debugmsgs enable messages to be sent to the debugger while the target is running. @var{charmsg} receives messages if Linux kernel ``Kernel low-level debugging via EmbeddedICE DCC channel'' option is enabled.
3433 @chapter JTAG Commands
3434 @cindex JTAG Commands
3435 Generally most people will not use the bulk of these commands. They
3436 are mostly used by the OpenOCD developers or those who need to
3437 directly manipulate the JTAG taps.
3439 In general these commands control JTAG taps at a very low level. For
3440 example if you need to control a JTAG Route Controller (i.e.: the
3441 OMAP3530 on the Beagle Board has one) you might use these commands in
3442 a script or an event procedure.
3446 @item @b{scan_chain}
3448 @*Print current scan chain configuration.
3449 @item @b{jtag_reset} <@var{trst}> <@var{srst}>
3451 @*Toggle reset lines.
3452 @item @b{endstate} <@var{tap_state}>
3454 @*Finish JTAG operations in <@var{tap_state}>.
3455 @item @b{runtest} <@var{num_cycles}>
3457 @*Move to Run-Test/Idle, and execute <@var{num_cycles}>
3458 @item @b{statemove} [@var{tap_state}]
3460 @*Move to current endstate or [@var{tap_state}]
3461 @item @b{irscan} <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
3463 @*Execute IR scan <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
3464 @item @b{drscan} <@var{device}> [@var{dev2}] [@var{var2}] ...
3466 @*Execute DR scan <@var{device}> [@var{dev2}] [@var{var2}] ...
3467 @item @b{verify_ircapture} <@option{enable}|@option{disable}>
3468 @cindex verify_ircapture
3469 @*Verify value captured during Capture-IR. Default is enabled.
3470 @item @b{var} <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
3472 @*Allocate, display or delete variable <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
3473 @item @b{field} <@var{var}> <@var{field}> [@var{value}|@var{flip}]
3475 Display/modify variable field <@var{var}> <@var{field}> [@var{value}|@var{flip}].
3480 Available tap_states are:
3520 If OpenOCD runs on an embedded host(as ZY1000 does), then TFTP can
3521 be used to access files on PCs (either the developer's PC or some other PC).
3523 The way this works on the ZY1000 is to prefix a filename by
3524 "/tftp/ip/" and append the TFTP path on the TFTP
3525 server (tftpd). E.g. "load_image /tftp/10.0.0.96/c:\temp\abc.elf" will
3526 load c:\temp\abc.elf from the developer pc (10.0.0.96) into memory as
3527 if the file was hosted on the embedded host.
3529 In order to achieve decent performance, you must choose a TFTP server
3530 that supports a packet size bigger than the default packet size (512 bytes). There
3531 are numerous TFTP servers out there (free and commercial) and you will have to do
3532 a bit of googling to find something that fits your requirements.
3534 @node Sample Scripts
3535 @chapter Sample Scripts
3538 This page shows how to use the Target Library.
3540 The configuration script can be divided into the following sections:
3542 @item Daemon configuration
3544 @item JTAG scan chain
3545 @item Target configuration
3546 @item Flash configuration
3549 Detailed information about each section can be found at OpenOCD configuration.
3551 @section AT91R40008 example
3552 @cindex AT91R40008 example
3553 To start OpenOCD with a target script for the AT91R40008 CPU and reset
3554 the CPU upon startup of the OpenOCD daemon.
3556 openocd -f interface/parport.cfg -f target/at91r40008.cfg -c init -c reset
3560 @node GDB and OpenOCD
3561 @chapter GDB and OpenOCD
3563 OpenOCD complies with the remote gdbserver protocol, and as such can be used
3564 to debug remote targets.
3566 @section Connecting to GDB
3567 @cindex Connecting to GDB
3568 @anchor{Connecting to GDB}
3569 Use GDB 6.7 or newer with OpenOCD if you run into trouble. For
3570 instance GDB 6.3 has a known bug that produces bogus memory access
3571 errors, which has since been fixed: look up 1836 in
3572 @url{http://sourceware.org/cgi-bin/gnatsweb.pl?database=gdb}
3574 @*OpenOCD can communicate with GDB in two ways:
3577 A socket (TCP/IP) connection is typically started as follows:
3579 target remote localhost:3333
3581 This would cause GDB to connect to the gdbserver on the local pc using port 3333.
3583 A pipe connection is typically started as follows:
3585 target remote | openocd --pipe
3587 This would cause GDB to run OpenOCD and communicate using pipes (stdin/stdout).
3588 Using this method has the advantage of GDB starting/stopping OpenOCD for the debug
3592 @*To see a list of available OpenOCD commands type @option{monitor help} on the
3595 OpenOCD supports the gdb @option{qSupported} packet, this enables information
3596 to be sent by the GDB remote server (i.e. OpenOCD) to GDB. Typical information includes
3597 packet size and the device's memory map.
3599 Previous versions of OpenOCD required the following GDB options to increase
3600 the packet size and speed up GDB communication:
3602 set remote memory-write-packet-size 1024
3603 set remote memory-write-packet-size fixed
3604 set remote memory-read-packet-size 1024
3605 set remote memory-read-packet-size fixed
3607 This is now handled in the @option{qSupported} PacketSize and should not be required.
3609 @section Programming using GDB
3610 @cindex Programming using GDB
3612 By default the target memory map is sent to GDB. This can be disabled by
3613 the following OpenOCD configuration option:
3615 gdb_memory_map disable
3617 For this to function correctly a valid flash configuration must also be set
3618 in OpenOCD. For faster performance you should also configure a valid
3621 Informing GDB of the memory map of the target will enable GDB to protect any
3622 flash areas of the target and use hardware breakpoints by default. This means
3623 that the OpenOCD option @command{gdb_breakpoint_override} is not required when
3624 using a memory map. @xref{gdb_breakpoint_override}.
3626 To view the configured memory map in GDB, use the GDB command @option{info mem}
3627 All other unassigned addresses within GDB are treated as RAM.
3629 GDB 6.8 and higher set any memory area not in the memory map as inaccessible.
3630 This can be changed to the old behaviour by using the following GDB command
3632 set mem inaccessible-by-default off
3635 If @command{gdb_flash_program enable} is also used, GDB will be able to
3636 program any flash memory using the vFlash interface.
3638 GDB will look at the target memory map when a load command is given, if any
3639 areas to be programmed lie within the target flash area the vFlash packets
3642 If the target needs configuring before GDB programming, an event
3643 script can be executed:
3645 $_TARGETNAME configure -event EVENTNAME BODY
3648 To verify any flash programming the GDB command @option{compare-sections}
3651 @node Tcl Scripting API
3652 @chapter Tcl Scripting API
3653 @cindex Tcl Scripting API
3657 The commands are stateless. E.g. the telnet command line has a concept
3658 of currently active target, the Tcl API proc's take this sort of state
3659 information as an argument to each proc.
3661 There are three main types of return values: single value, name value
3662 pair list and lists.
3664 Name value pair. The proc 'foo' below returns a name/value pair
3670 > set foo(you) Oyvind
3671 > set foo(mouse) Micky
3672 > set foo(duck) Donald
3680 me Duane you Oyvind mouse Micky duck Donald
3682 Thus, to get the names of the associative array is easy:
3684 foreach { name value } [set foo] {
3685 puts "Name: $name, Value: $value"
3689 Lists returned must be relatively small. Otherwise a range
3690 should be passed in to the proc in question.
3692 @section Internal low-level Commands
3694 By low-level, the intent is a human would not directly use these commands.
3696 Low-level commands are (should be) prefixed with "openocd_", e.g. openocd_flash_banks
3697 is the low level API upon which "flash banks" is implemented.
3700 @item @b{ocd_mem2array} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
3702 Read memory and return as a Tcl array for script processing
3703 @item @b{ocd_array2mem} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
3705 Convert a Tcl array to memory locations and write the values
3706 @item @b{ocd_flash_banks} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}> <@var{target}> [@option{driver options} ...]
3708 Return information about the flash banks
3711 OpenOCD commands can consist of two words, e.g. "flash banks". The
3712 startup.tcl "unknown" proc will translate this into a Tcl proc
3713 called "flash_banks".
3715 @section OpenOCD specific Global Variables
3719 Real Tcl has ::tcl_platform(), and platform::identify, and many other
3720 variables. JimTCL, as implemented in OpenOCD creates $HostOS which
3721 holds one of the following values:
3724 @item @b{winxx} Built using Microsoft Visual Studio
3725 @item @b{linux} Linux is the underlying operating sytem
3726 @item @b{darwin} Darwin (mac-os) is the underlying operating sytem.
3727 @item @b{cygwin} Running under Cygwin
3728 @item @b{mingw32} Running under MingW32
3729 @item @b{other} Unknown, none of the above.
3732 Note: 'winxx' was choosen because today (March-2009) no distinction is made between Win32 and Win64.
3735 @chapter Deprecated/Removed Commands
3736 @cindex Deprecated/Removed Commands
3737 Certain OpenOCD commands have been deprecated/removed during the various revisions.
3740 @item @b{arm7_9 fast_writes}
3741 @cindex arm7_9 fast_writes
3742 @*use @option{arm7_9 fast_memory_access} command with same args. @xref{arm7_9 fast_memory_access}.
3743 @item @b{arm7_9 force_hw_bkpts}
3744 @cindex arm7_9 force_hw_bkpts
3745 @*Use @command{gdb_breakpoint_override} instead. Note that GDB will use hardware breakpoints
3746 for flash if the GDB memory map has been set up(default when flash is declared in
3747 target configuration). @xref{gdb_breakpoint_override}.
3748 @item @b{arm7_9 sw_bkpts}
3749 @cindex arm7_9 sw_bkpts
3750 @*On by default. @xref{gdb_breakpoint_override}.
3751 @item @b{daemon_startup}
3752 @cindex daemon_startup
3753 @*this config option has been removed, simply adding @option{init} and @option{reset halt} to
3754 the end of your config script will give the same behaviour as using @option{daemon_startup reset}
3755 and @option{target cortex_m3 little reset_halt 0}.
3756 @item @b{dump_binary}
3758 @*use @option{dump_image} command with same args. @xref{dump_image}.
3759 @item @b{flash erase}
3761 @*use @option{flash erase_sector} command with same args. @xref{flash erase_sector}.
3762 @item @b{flash write}
3764 @*use @option{flash write_bank} command with same args. @xref{flash write_bank}.
3765 @item @b{flash write_binary}
3766 @cindex flash write_binary
3767 @*use @option{flash write_bank} command with same args. @xref{flash write_bank}.
3768 @item @b{flash auto_erase}
3769 @cindex flash auto_erase
3770 @*use @option{flash write_image} command passing @option{erase} as the first parameter. @xref{flash write_image}.
3772 @item @b{jtag_speed} value
3773 @*@xref{JTAG Speed}.
3774 Usually, a value of zero means maximum
3775 speed. The actual effect of this option depends on the JTAG interface used.
3777 @item wiggler: maximum speed / @var{number}
3778 @item ft2232: 6MHz / (@var{number}+1)
3779 @item amt jtagaccel: 8 / 2**@var{number}
3780 @item jlink: maximum speed in kHz (0-12000), 0 will use RTCK
3781 @item rlink: 24MHz / @var{number}, but only for certain values of @var{number}
3782 @comment end speed list.
3785 @item @b{load_binary}
3787 @*use @option{load_image} command with same args. @xref{load_image}.
3788 @item @b{run_and_halt_time}
3789 @cindex run_and_halt_time
3790 @*This command has been removed for simpler reset behaviour, it can be simulated with the
3797 @item @b{target} <@var{type}> <@var{endian}> <@var{jtag-position}>
3799 @*use the create subcommand of @option{target}.
3800 @item @b{target_script} <@var{target#}> <@var{eventname}> <@var{scriptname}>
3801 @cindex target_script
3802 @*use <@var{target_name}> configure -event <@var{eventname}> "script <@var{scriptname}>"
3803 @item @b{working_area}
3804 @cindex working_area
3805 @*use the @option{configure} subcommand of @option{target} to set the work-area-virt, work-area-phy, work-area-size, and work-area-backup properties of the target.
3812 @item @b{RTCK, also known as: Adaptive Clocking - What is it?}
3815 @cindex adaptive clocking
3818 In digital circuit design it is often refered to as ``clock
3819 synchronisation'' the JTAG interface uses one clock (TCK or TCLK)
3820 operating at some speed, your target is operating at another. The two
3821 clocks are not synchronised, they are ``asynchronous''
3823 In order for the two to work together they must be synchronised. Otherwise
3824 the two systems will get out of sync with each other and nothing will
3825 work. There are 2 basic options:
3828 Use a special circuit.
3830 One clock must be some multiple slower than the other.
3833 @b{Does this really matter?} For some chips and some situations, this
3834 is a non-issue (i.e.: A 500MHz ARM926) but for others - for example some
3835 Atmel SAM7 and SAM9 chips start operation from reset at 32kHz -
3836 program/enable the oscillators and eventually the main clock. It is in
3837 those critical times you must slow the JTAG clock to sometimes 1 to
3840 Imagine debugging a 500MHz ARM926 hand held battery powered device
3841 that ``deep sleeps'' at 32kHz between every keystroke. It can be
3844 @b{Solution #1 - A special circuit}
3846 In order to make use of this, your JTAG dongle must support the RTCK
3847 feature. Not all dongles support this - keep reading!
3849 The RTCK signal often found in some ARM chips is used to help with
3850 this problem. ARM has a good description of the problem described at
3851 this link: @url{http://www.arm.com/support/faqdev/4170.html} [checked
3852 28/nov/2008]. Link title: ``How does the JTAG synchronisation logic
3853 work? / how does adaptive clocking work?''.
3855 The nice thing about adaptive clocking is that ``battery powered hand
3856 held device example'' - the adaptiveness works perfectly all the
3857 time. One can set a break point or halt the system in the deep power
3858 down code, slow step out until the system speeds up.
3860 @b{Solution #2 - Always works - but may be slower}
3862 Often this is a perfectly acceptable solution.
3864 In most simple terms: Often the JTAG clock must be 1/10 to 1/12 of
3865 the target clock speed. But what that ``magic division'' is varies
3866 depending on the chips on your board. @b{ARM rule of thumb} Most ARM
3867 based systems require an 8:1 division. @b{Xilinx rule of thumb} is
3868 1/12 the clock speed.
3870 Note: Many FTDI2232C based JTAG dongles are limited to 6MHz.
3872 You can still debug the 'low power' situations - you just need to
3873 manually adjust the clock speed at every step. While painful and
3874 tedious, it is not always practical.
3876 It is however easy to ``code your way around it'' - i.e.: Cheat a little,
3877 have a special debug mode in your application that does a ``high power
3878 sleep''. If you are careful - 98% of your problems can be debugged
3881 To set the JTAG frequency use the command:
3889 @item @b{Win32 Pathnames} Why don't backslashes work in Windows paths?
3891 OpenOCD uses Tcl and a backslash is an escape char. Use @{ and @}
3892 around Windows filenames.
3905 @item @b{Missing: cygwin1.dll} OpenOCD complains about a missing cygwin1.dll.
3907 Make sure you have Cygwin installed, or at least a version of OpenOCD that
3908 claims to come with all the necessary DLLs. When using Cygwin, try launching
3909 OpenOCD from the Cygwin shell.
3911 @item @b{Breakpoint Issue} I'm trying to set a breakpoint using GDB (or a frontend like Insight or
3912 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
3913 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
3915 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
3916 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720T or ARM920T,
3917 software breakpoints consume one of the two available hardware breakpoints.
3919 @item @b{LPC2000 Flash} When erasing or writing LPC2000 on-chip flash, the operation fails at random.
3921 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
3922 clock at the time you're programming the flash. If you've specified the crystal's
3923 frequency, make sure the PLL is disabled. If you've specified the full core speed
3924 (e.g. 60MHz), make sure the PLL is enabled.
3926 @item @b{Amontec Chameleon} When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
3927 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
3928 out while waiting for end of scan, rtck was disabled".
3930 Make sure your PC's parallel port operates in EPP mode. You might have to try several
3931 settings in your PC BIOS (ECP, EPP, and different versions of those).
3933 @item @b{Data Aborts} When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
3934 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
3935 memory read caused data abort".
3937 The errors are non-fatal, and are the result of GDB trying to trace stack frames
3938 beyond the last valid frame. It might be possible to prevent this by setting up
3939 a proper "initial" stack frame, if you happen to know what exactly has to
3940 be done, feel free to add this here.
3942 @b{Simple:} In your startup code - push 8 registers of zeros onto the
3943 stack before calling main(). What GDB is doing is ``climbing'' the run
3944 time stack by reading various values on the stack using the standard
3945 call frame for the target. GDB keeps going - until one of 2 things
3946 happen @b{#1} an invalid frame is found, or @b{#2} some huge number of
3947 stackframes have been processed. By pushing zeros on the stack, GDB
3950 @b{Debugging Interrupt Service Routines} - In your ISR before you call
3951 your C code, do the same - artifically push some zeros onto the stack,
3952 remember to pop them off when the ISR is done.
3954 @b{Also note:} If you have a multi-threaded operating system, they
3955 often do not @b{in the intrest of saving memory} waste these few
3959 @item @b{JTAG Reset Config} I get the following message in the OpenOCD console (or log file):
3960 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
3962 This warning doesn't indicate any serious problem, as long as you don't want to
3963 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
3964 trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
3965 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
3966 independently. With this setup, it's not possible to halt the core right out of
3967 reset, everything else should work fine.
3969 @item @b{USB Power} When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
3970 toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
3971 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
3972 quit with an error message. Is there a stability issue with OpenOCD?
3974 No, this is not a stability issue concerning OpenOCD. Most users have solved
3975 this issue by simply using a self-powered USB hub, which they connect their
3976 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
3977 supply stable enough for the Amontec JTAGkey to be operated.
3979 @b{Laptops running on battery have this problem too...}
3981 @item @b{USB Power} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
3982 following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
3983 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
3984 What does that mean and what might be the reason for this?
3986 First of all, the reason might be the USB power supply. Try using a self-powered
3987 hub instead of a direct connection to your computer. Secondly, the error code 4
3988 corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
3989 chip ran into some sort of error - this points us to a USB problem.
3991 @item @b{GDB Disconnects} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
3992 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
3993 What does that mean and what might be the reason for this?
3995 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
3996 has closed the connection to OpenOCD. This might be a GDB issue.
3998 @item @b{LPC2000 Flash} In the configuration file in the section where flash device configurations
3999 are described, there is a parameter for specifying the clock frequency
4000 for LPC2000 internal flash devices (e.g. @option{flash bank lpc2000
4001 0x0 0x40000 0 0 0 lpc2000_v1 14746 calc_checksum}), which must be
4002 specified in kilohertz. However, I do have a quartz crystal of a
4003 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz,
4004 i.e. 14,745.600 kHz). Is it possible to specify real numbers for the
4007 No. The clock frequency specified here must be given as an integral number.
4008 However, this clock frequency is used by the In-Application-Programming (IAP)
4009 routines of the LPC2000 family only, which seems to be very tolerant concerning
4010 the given clock frequency, so a slight difference between the specified clock
4011 frequency and the actual clock frequency will not cause any trouble.
4013 @item @b{Command Order} Do I have to keep a specific order for the commands in the configuration file?
4015 Well, yes and no. Commands can be given in arbitrary order, yet the
4016 devices listed for the JTAG scan chain must be given in the right
4017 order (jtag newdevice), with the device closest to the TDO-Pin being
4018 listed first. In general, whenever objects of the same type exist
4019 which require an index number, then these objects must be given in the
4020 right order (jtag newtap, targets and flash banks - a target
4021 references a jtag newtap and a flash bank references a target).
4023 You can use the ``scan_chain'' command to verify and display the tap order.
4025 Also, some commands can't execute until after @command{init} has been
4026 processed. Such commands include @command{nand probe} and everything
4027 else that needs to write to controller registers, perhaps for setting
4028 up DRAM and loading it with code.
4030 @item @b{JTAG Tap Order} JTAG tap order - command order
4032 Many newer devices have multiple JTAG taps. For example: ST
4033 Microsystems STM32 chips have two taps, a ``boundary scan tap'' and
4034 ``Cortex-M3'' tap. Example: The STM32 reference manual, Document ID:
4035 RM0008, Section 26.5, Figure 259, page 651/681, the ``TDI'' pin is
4036 connected to the boundary scan tap, which then connects to the
4037 Cortex-M3 tap, which then connects to the TDO pin.
4039 Thus, the proper order for the STM32 chip is: (1) The Cortex-M3, then
4040 (2) The boundary scan tap. If your board includes an additional JTAG
4041 chip in the scan chain (for example a Xilinx CPLD or FPGA) you could
4042 place it before or after the STM32 chip in the chain. For example:
4045 @item OpenOCD_TDI(output) -> STM32 TDI Pin (BS Input)
4046 @item STM32 BS TDO (output) -> STM32 Cortex-M3 TDI (input)
4047 @item STM32 Cortex-M3 TDO (output) -> SM32 TDO Pin
4048 @item STM32 TDO Pin (output) -> Xilinx TDI Pin (input)
4049 @item Xilinx TDO Pin -> OpenOCD TDO (input)
4052 The ``jtag device'' commands would thus be in the order shown below. Note:
4055 @item jtag newtap Xilinx tap -irlen ...
4056 @item jtag newtap stm32 cpu -irlen ...
4057 @item jtag newtap stm32 bs -irlen ...
4058 @item # Create the debug target and say where it is
4059 @item target create stm32.cpu -chain-position stm32.cpu ...
4063 @item @b{SYSCOMP} Sometimes my debugging session terminates with an error. When I look into the
4064 log file, I can see these error messages: Error: arm7_9_common.c:561
4065 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP
4071 @node Tcl Crash Course
4072 @chapter Tcl Crash Course
4075 Not everyone knows Tcl - this is not intended to be a replacement for
4076 learning Tcl, the intent of this chapter is to give you some idea of
4077 how the Tcl scripts work.
4079 This chapter is written with two audiences in mind. (1) OpenOCD users
4080 who need to understand a bit more of how JIM-Tcl works so they can do
4081 something useful, and (2) those that want to add a new command to
4084 @section Tcl Rule #1
4085 There is a famous joke, it goes like this:
4087 @item Rule #1: The wife is always correct
4088 @item Rule #2: If you think otherwise, See Rule #1
4091 The Tcl equal is this:
4094 @item Rule #1: Everything is a string
4095 @item Rule #2: If you think otherwise, See Rule #1
4098 As in the famous joke, the consequences of Rule #1 are profound. Once
4099 you understand Rule #1, you will understand Tcl.
4101 @section Tcl Rule #1b
4102 There is a second pair of rules.
4104 @item Rule #1: Control flow does not exist. Only commands
4105 @* For example: the classic FOR loop or IF statement is not a control
4106 flow item, they are commands, there is no such thing as control flow
4108 @item Rule #2: If you think otherwise, See Rule #1
4109 @* Actually what happens is this: There are commands that by
4110 convention, act like control flow key words in other languages. One of
4111 those commands is the word ``for'', another command is ``if''.
4114 @section Per Rule #1 - All Results are strings
4115 Every Tcl command results in a string. The word ``result'' is used
4116 deliberatly. No result is just an empty string. Remember: @i{Rule #1 -
4117 Everything is a string}
4119 @section Tcl Quoting Operators
4120 In life of a Tcl script, there are two important periods of time, the
4121 difference is subtle.
4124 @item Evaluation Time
4127 The two key items here are how ``quoted things'' work in Tcl. Tcl has
4128 three primary quoting constructs, the [square-brackets] the
4129 @{curly-braces@} and ``double-quotes''
4131 By now you should know $VARIABLES always start with a $DOLLAR
4132 sign. BTW: To set a variable, you actually use the command ``set'', as
4133 in ``set VARNAME VALUE'' much like the ancient BASIC langauge ``let x
4134 = 1'' statement, but without the equal sign.
4137 @item @b{[square-brackets]}
4138 @* @b{[square-brackets]} are command substitutions. It operates much
4139 like Unix Shell `back-ticks`. The result of a [square-bracket]
4140 operation is exactly 1 string. @i{Remember Rule #1 - Everything is a
4141 string}. These two statements are roughly identical:
4145 echo "The Date is: $X"
4148 puts "The Date is: $X"
4150 @item @b{``double-quoted-things''}
4151 @* @b{``double-quoted-things''} are just simply quoted
4152 text. $VARIABLES and [square-brackets] are expanded in place - the
4153 result however is exactly 1 string. @i{Remember Rule #1 - Everything
4157 puts "It is now \"[date]\", $x is in 1 hour"
4159 @item @b{@{Curly-Braces@}}
4160 @*@b{@{Curly-Braces@}} are magic: $VARIABLES and [square-brackets] are
4161 parsed, but are NOT expanded or executed. @{Curly-Braces@} are like
4162 'single-quote' operators in BASH shell scripts, with the added
4163 feature: @{curly-braces@} can be nested, single quotes can not. @{@{@{this is
4164 nested 3 times@}@}@} NOTE: [date] is perhaps a bad example, as of
4165 28/nov/2008, Jim/OpenOCD does not have a date command.
4168 @section Consequences of Rule 1/2/3/4
4170 The consequences of Rule 1 are profound.
4172 @subsection Tokenisation & Execution.
4174 Of course, whitespace, blank lines and #comment lines are handled in
4177 As a script is parsed, each (multi) line in the script file is
4178 tokenised and according to the quoting rules. After tokenisation, that
4179 line is immedatly executed.
4181 Multi line statements end with one or more ``still-open''
4182 @{curly-braces@} which - eventually - closes a few lines later.
4184 @subsection Command Execution
4186 Remember earlier: There are no ``control flow''
4187 statements in Tcl. Instead there are COMMANDS that simply act like
4188 control flow operators.
4190 Commands are executed like this:
4193 @item Parse the next line into (argc) and (argv[]).
4194 @item Look up (argv[0]) in a table and call its function.
4195 @item Repeat until End Of File.
4198 It sort of works like this:
4201 ReadAndParse( &argc, &argv );
4203 cmdPtr = LookupCommand( argv[0] );
4205 (*cmdPtr->Execute)( argc, argv );
4209 When the command ``proc'' is parsed (which creates a procedure
4210 function) it gets 3 parameters on the command line. @b{1} the name of
4211 the proc (function), @b{2} the list of parameters, and @b{3} the body
4212 of the function. Not the choice of words: LIST and BODY. The PROC
4213 command stores these items in a table somewhere so it can be found by
4216 @subsection The FOR command
4218 The most interesting command to look at is the FOR command. In Tcl,
4219 the FOR command is normally implemented in C. Remember, FOR is a
4220 command just like any other command.
4222 When the ascii text containing the FOR command is parsed, the parser
4223 produces 5 parameter strings, @i{(If in doubt: Refer to Rule #1)} they
4227 @item The ascii text 'for'
4228 @item The start text
4229 @item The test expression
4234 Sort of reminds you of ``main( int argc, char **argv )'' does it not?
4235 Remember @i{Rule #1 - Everything is a string.} The key point is this:
4236 Often many of those parameters are in @{curly-braces@} - thus the
4237 variables inside are not expanded or replaced until later.
4239 Remember that every Tcl command looks like the classic ``main( argc,
4240 argv )'' function in C. In JimTCL - they actually look like this:
4244 MyCommand( Jim_Interp *interp,
4246 Jim_Obj * const *argvs );
4249 Real Tcl is nearly identical. Although the newer versions have
4250 introduced a byte-code parser and intepreter, but at the core, it
4251 still operates in the same basic way.
4253 @subsection FOR command implementation
4255 To understand Tcl it is perhaps most helpful to see the FOR
4256 command. Remember, it is a COMMAND not a control flow structure.
4258 In Tcl there are two underlying C helper functions.
4260 Remember Rule #1 - You are a string.
4262 The @b{first} helper parses and executes commands found in an ascii
4263 string. Commands can be seperated by semicolons, or newlines. While
4264 parsing, variables are expanded via the quoting rules.
4266 The @b{second} helper evaluates an ascii string as a numerical
4267 expression and returns a value.
4269 Here is an example of how the @b{FOR} command could be
4270 implemented. The pseudo code below does not show error handling.
4272 void Execute_AsciiString( void *interp, const char *string );
4274 int Evaluate_AsciiExpression( void *interp, const char *string );
4277 MyForCommand( void *interp,
4282 SetResult( interp, "WRONG number of parameters");
4286 // argv[0] = the ascii string just like C
4288 // Execute the start statement.
4289 Execute_AsciiString( interp, argv[1] );
4293 i = Evaluate_AsciiExpression(interp, argv[2]);
4298 Execute_AsciiString( interp, argv[3] );
4300 // Execute the LOOP part
4301 Execute_AsciiString( interp, argv[4] );
4305 SetResult( interp, "" );
4310 Every other command IF, WHILE, FORMAT, PUTS, EXPR, everything works
4311 in the same basic way.
4313 @section OpenOCD Tcl Usage
4315 @subsection source and find commands
4316 @b{Where:} In many configuration files
4317 @* Example: @b{ source [find FILENAME] }
4318 @*Remember the parsing rules
4320 @item The FIND command is in square brackets.
4321 @* The FIND command is executed with the parameter FILENAME. It should
4322 find the full path to the named file. The RESULT is a string, which is
4323 substituted on the orginal command line.
4324 @item The command source is executed with the resulting filename.
4325 @* SOURCE reads a file and executes as a script.
4327 @subsection format command
4328 @b{Where:} Generally occurs in numerous places.
4329 @* Tcl has no command like @b{printf()}, instead it has @b{format}, which is really more like
4335 puts [format "The answer: %d" [expr $x * $y]]
4338 @item The SET command creates 2 variables, X and Y.
4339 @item The double [nested] EXPR command performs math
4340 @* The EXPR command produces numerical result as a string.
4342 @item The format command is executed, producing a single string
4343 @* Refer to Rule #1.
4344 @item The PUTS command outputs the text.
4346 @subsection Body or Inlined Text
4347 @b{Where:} Various TARGET scripts.
4350 proc someproc @{@} @{
4351 ... multiple lines of stuff ...
4353 $_TARGETNAME configure -event FOO someproc
4354 #2 Good - no variables
4355 $_TARGETNAME confgure -event foo "this ; that;"
4356 #3 Good Curly Braces
4357 $_TARGETNAME configure -event FOO @{
4360 #4 DANGER DANGER DANGER
4361 $_TARGETNAME configure -event foo "puts \"Time: [date]\""
4364 @item The $_TARGETNAME is an OpenOCD variable convention.
4365 @*@b{$_TARGETNAME} represents the last target created, the value changes
4366 each time a new target is created. Remember the parsing rules. When
4367 the ascii text is parsed, the @b{$_TARGETNAME} becomes a simple string,
4368 the name of the target which happens to be a TARGET (object)
4370 @item The 2nd parameter to the @option{-event} parameter is a TCBODY
4371 @*There are 4 examples:
4373 @item The TCLBODY is a simple string that happens to be a proc name
4374 @item The TCLBODY is several simple commands seperated by semicolons
4375 @item The TCLBODY is a multi-line @{curly-brace@} quoted string
4376 @item The TCLBODY is a string with variables that get expanded.
4379 In the end, when the target event FOO occurs the TCLBODY is
4380 evaluated. Method @b{#1} and @b{#2} are functionally identical. For
4381 Method @b{#3} and @b{#4} it is more interesting. What is the TCLBODY?
4383 Remember the parsing rules. In case #3, @{curly-braces@} mean the
4384 $VARS and [square-brackets] are expanded later, when the EVENT occurs,
4385 and the text is evaluated. In case #4, they are replaced before the
4386 ``Target Object Command'' is executed. This occurs at the same time
4387 $_TARGETNAME is replaced. In case #4 the date will never
4388 change. @{BTW: [date] is perhaps a bad example, as of 28/nov/2008,
4389 Jim/OpenOCD does not have a date command@}
4391 @subsection Global Variables
4392 @b{Where:} You might discover this when writing your own procs @* In
4393 simple terms: Inside a PROC, if you need to access a global variable
4394 you must say so. See also ``upvar''. Example:
4396 proc myproc @{ @} @{
4397 set y 0 #Local variable Y
4398 global x #Global variable X
4399 puts [format "X=%d, Y=%d" $x $y]
4402 @section Other Tcl Hacks
4403 @b{Dynamic variable creation}
4405 # Dynamically create a bunch of variables.
4406 for @{ set x 0 @} @{ $x < 32 @} @{ set x [expr $x + 1]@} @{
4408 set vn [format "BIT%d" $x]
4412 set $vn [expr (1 << $x)]
4415 @b{Dynamic proc/command creation}
4417 # One "X" function - 5 uart functions.
4418 foreach who @{A B C D E@}
4419 proc [format "show_uart%c" $who] @{ @} "show_UARTx $who"
4423 @node Target Library
4424 @chapter Target Library
4425 @cindex Target Library
4427 OpenOCD comes with a target configuration script library. These scripts can be
4428 used as-is or serve as a starting point.
4430 The target library is published together with the OpenOCD executable and
4431 the path to the target library is in the OpenOCD script search path.
4432 Similarly there are example scripts for configuring the JTAG interface.
4434 The command line below uses the example parport configuration script
4435 that ship with OpenOCD, then configures the str710.cfg target and
4436 finally issues the init and reset commands. The communication speed
4437 is set to 10kHz for reset and 8MHz for post reset.
4440 openocd -f interface/parport.cfg -f target/str710.cfg -c "init" -c "reset"
4443 To list the target scripts available:
4446 $ ls /usr/local/lib/openocd/target
4448 arm7_fast.cfg lm3s6965.cfg pxa255.cfg stm32.cfg xba_revA3.cfg
4449 at91eb40a.cfg lpc2148.cfg pxa255_sst.cfg str710.cfg zy1000.cfg
4450 at91r40008.cfg lpc2294.cfg sam7s256.cfg str912.cfg
4451 at91sam9260.cfg nslu2.cfg sam7x256.cfg wi-9c.cfg
4456 @node OpenOCD Concept Index
4457 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
4458 @comment case issue with ``Index.html'' and ``index.html''
4459 @comment Occurs when creating ``--html --no-split'' output
4460 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
4461 @unnumbered OpenOCD Concept Index
4465 @node OpenOCD Command Index
4466 @unnumbered OpenOCD Command Index