1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
7 * OpenOCD: (openocd). OpenOCD User's Guide
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009-2010 David Brownell
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
40 @titlefont{@emph{Open On-Chip Debugger:}}
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
47 @vskip 0pt plus 1filll
56 @top OpenOCD User's Guide
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About Jim-Tcl:: About Jim-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Daemon Configuration:: Daemon Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * Flash Programming:: Flash Programming
76 * PLD/FPGA Commands:: PLD/FPGA Commands
77 * General Commands:: General Commands
78 * Architecture and Core Commands:: Architecture and Core Commands
79 * JTAG Commands:: JTAG Commands
80 * Boundary Scan Commands:: Boundary Scan Commands
81 * Utility Commands:: Utility Commands
83 * GDB and OpenOCD:: Using GDB and OpenOCD
84 * Tcl Scripting API:: Tcl Scripting API
85 * FAQ:: Frequently Asked Questions
86 * Tcl Crash Course:: Tcl Crash Course
87 * License:: GNU Free Documentation License
89 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
90 @comment case issue with ``Index.html'' and ``index.html''
91 @comment Occurs when creating ``--html --no-split'' output
92 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
93 * OpenOCD Concept Index:: Concept Index
94 * Command and Driver Index:: Command and Driver Index
101 OpenOCD was created by Dominic Rath as part of a 2005 diploma thesis written
102 at the University of Applied Sciences Augsburg (@uref{http://www.hs-augsburg.de}).
103 Since that time, the project has grown into an active open-source project,
104 supported by a diverse community of software and hardware developers from
107 @section What is OpenOCD?
111 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
112 in-system programming and boundary-scan testing for embedded target
115 It does so with the assistance of a @dfn{debug adapter}, which is
116 a small hardware module which helps provide the right kind of
117 electrical signaling to the target being debugged. These are
118 required since the debug host (on which OpenOCD runs) won't
119 usually have native support for such signaling, or the connector
120 needed to hook up to the target.
122 Such debug adapters support one or more @dfn{transport} protocols,
123 each of which involves different electrical signaling (and uses
124 different messaging protocols on top of that signaling). There
125 are many types of debug adapter, and little uniformity in what
126 they are called. (There are also product naming differences.)
128 These adapters are sometimes packaged as discrete dongles, which
129 may generically be called @dfn{hardware interface dongles}.
130 Some development boards also integrate them directly, which may
131 let the development board connect directly to the debug
132 host over USB (and sometimes also to power it over USB).
134 For example, a @dfn{JTAG Adapter} supports JTAG
135 signaling, and is used to communicate
136 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
137 A @dfn{TAP} is a ``Test Access Port'', a module which processes
138 special instructions and data. TAPs are daisy-chained within and
139 between chips and boards. JTAG supports debugging and boundary
142 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
143 signaling to communicate with some newer ARM cores, as well as debug
144 adapters which support both JTAG and SWD transports. SWD supports only
145 debugging, whereas JTAG also supports boundary scan operations.
147 For some chips, there are also @dfn{Programming Adapters} supporting
148 special transports used only to write code to flash memory, without
149 support for on-chip debugging or boundary scan.
150 (At this writing, OpenOCD does not support such non-debug adapters.)
153 @b{Dongles:} OpenOCD currently supports many types of hardware dongles:
154 USB-based, parallel port-based, and other standalone boxes that run
155 OpenOCD internally. @xref{Debug Adapter Hardware}.
157 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
158 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x), Cortex-M3
159 (Stellaris LM3, ST STM32 and Energy Micro EFM32) and Intel Quark (x10xx)
160 based cores to be debugged via the GDB protocol.
162 @b{Flash Programming:} Flash writing is supported for external
163 CFI-compatible NOR flashes (Intel and AMD/Spansion command set) and several
164 internal flashes (LPC1700, LPC1800, LPC2000, LPC4300, AT91SAM7, AT91SAM3U,
165 STR7x, STR9x, LM3, STM32x and EFM32). Preliminary support for various NAND flash
166 controllers (LPC3180, Orion, S3C24xx, more) is included.
168 @section OpenOCD Web Site
170 The OpenOCD web site provides the latest public news from the community:
172 @uref{http://openocd.org/}
174 @section Latest User's Guide:
176 The user's guide you are now reading may not be the latest one
177 available. A version for more recent code may be available.
178 Its HTML form is published regularly at:
180 @uref{http://openocd.org/doc/html/index.html}
182 PDF form is likewise published at:
184 @uref{http://openocd.org/doc/pdf/openocd.pdf}
186 @section OpenOCD User's Forum
188 There is an OpenOCD forum (phpBB) hosted by SparkFun,
189 which might be helpful to you. Note that if you want
190 anything to come to the attention of developers, you
191 should post it to the OpenOCD Developer Mailing List
192 instead of this forum.
194 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
196 @section OpenOCD User's Mailing List
198 The OpenOCD User Mailing List provides the primary means of
199 communication between users:
201 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-user}
205 Support can also be found on irc:
206 @uref{irc://irc.freenode.net/openocd}
209 @chapter OpenOCD Developer Resources
212 If you are interested in improving the state of OpenOCD's debugging and
213 testing support, new contributions will be welcome. Motivated developers
214 can produce new target, flash or interface drivers, improve the
215 documentation, as well as more conventional bug fixes and enhancements.
217 The resources in this chapter are available for developers wishing to explore
218 or expand the OpenOCD source code.
220 @section OpenOCD Git Repository
222 During the 0.3.x release cycle, OpenOCD switched from Subversion to
223 a Git repository hosted at SourceForge. The repository URL is:
225 @uref{git://git.code.sf.net/p/openocd/code}
229 @uref{http://git.code.sf.net/p/openocd/code}
231 You may prefer to use a mirror and the HTTP protocol:
233 @uref{http://repo.or.cz/r/openocd.git}
235 With standard Git tools, use @command{git clone} to initialize
236 a local repository, and @command{git pull} to update it.
237 There are also gitweb pages letting you browse the repository
238 with a web browser, or download arbitrary snapshots without
239 needing a Git client:
241 @uref{http://repo.or.cz/w/openocd.git}
243 The @file{README} file contains the instructions for building the project
244 from the repository or a snapshot.
246 Developers that want to contribute patches to the OpenOCD system are
247 @b{strongly} encouraged to work against mainline.
248 Patches created against older versions may require additional
249 work from their submitter in order to be updated for newer releases.
251 @section Doxygen Developer Manual
253 During the 0.2.x release cycle, the OpenOCD project began
254 providing a Doxygen reference manual. This document contains more
255 technical information about the software internals, development
256 processes, and similar documentation:
258 @uref{http://openocd.org/doc/doxygen/html/index.html}
260 This document is a work-in-progress, but contributions would be welcome
261 to fill in the gaps. All of the source files are provided in-tree,
262 listed in the Doxyfile configuration at the top of the source tree.
264 @section Gerrit Review System
266 All changes in the OpenOCD Git repository go through the web-based Gerrit
269 @uref{http://openocd.zylin.com/}
271 After a one-time registration and repository setup, anyone can push commits
272 from their local Git repository directly into Gerrit.
273 All users and developers are encouraged to review, test, discuss and vote
274 for changes in Gerrit. The feedback provides the basis for a maintainer to
275 eventually submit the change to the main Git repository.
277 The @file{HACKING} file, also available as the Patch Guide in the Doxygen
278 Developer Manual, contains basic information about how to connect a
279 repository to Gerrit, prepare and push patches. Patch authors are expected to
280 maintain their changes while they're in Gerrit, respond to feedback and if
281 necessary rework and push improved versions of the change.
283 @section OpenOCD Developer Mailing List
285 The OpenOCD Developer Mailing List provides the primary means of
286 communication between developers:
288 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-devel}
290 @section OpenOCD Bug Tracker
292 The OpenOCD Bug Tracker is hosted on SourceForge:
294 @uref{http://bugs.openocd.org/}
297 @node Debug Adapter Hardware
298 @chapter Debug Adapter Hardware
307 Defined: @b{dongle}: A small device that plugs into a computer and serves as
308 an adapter .... [snip]
310 In the OpenOCD case, this generally refers to @b{a small adapter} that
311 attaches to your computer via USB or the parallel port. One
312 exception is the Ultimate Solutions ZY1000, packaged as a small box you
313 attach via an ethernet cable. The ZY1000 has the advantage that it does not
314 require any drivers to be installed on the developer PC. It also has
315 a built in web interface. It supports RTCK/RCLK or adaptive clocking
316 and has a built-in relay to power cycle targets remotely.
319 @section Choosing a Dongle
321 There are several things you should keep in mind when choosing a dongle.
324 @item @b{Transport} Does it support the kind of communication that you need?
325 OpenOCD focusses mostly on JTAG. Your version may also support
326 other ways to communicate with target devices.
327 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
328 Does your dongle support it? You might need a level converter.
329 @item @b{Pinout} What pinout does your target board use?
330 Does your dongle support it? You may be able to use jumper
331 wires, or an "octopus" connector, to convert pinouts.
332 @item @b{Connection} Does your computer have the USB, parallel, or
333 Ethernet port needed?
334 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
335 RTCK support (also known as ``adaptive clocking'')?
338 @section Stand-alone JTAG Probe
340 The ZY1000 from Ultimate Solutions is technically not a dongle but a
341 stand-alone JTAG probe that, unlike most dongles, doesn't require any drivers
342 running on the developer's host computer.
343 Once installed on a network using DHCP or a static IP assignment, users can
344 access the ZY1000 probe locally or remotely from any host with access to the
345 IP address assigned to the probe.
346 The ZY1000 provides an intuitive web interface with direct access to the
348 Users may also run a GDBSERVER directly on the ZY1000 to take full advantage
349 of GCC & GDB to debug any distribution of embedded Linux or NetBSD running on
351 The ZY1000 supports RTCK & RCLK or adaptive clocking and has a built-in relay
352 to power cycle the target remotely.
354 For more information, visit:
356 @b{ZY1000} See: @url{http://www.ultsol.com/index.php/component/content/article/8/210-zylin-zy1000-main}
358 @section USB FT2232 Based
360 There are many USB JTAG dongles on the market, many of them based
361 on a chip from ``Future Technology Devices International'' (FTDI)
362 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
363 See: @url{http://www.ftdichip.com} for more information.
364 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
365 chips started to become available in JTAG adapters. Around 2012, a new
366 variant appeared - FT232H - this is a single-channel version of FT2232H.
367 (Adapters using those high speed FT2232H or FT232H chips may support adaptive
370 The FT2232 chips are flexible enough to support some other
371 transport options, such as SWD or the SPI variants used to
372 program some chips. They have two communications channels,
373 and one can be used for a UART adapter at the same time the
374 other one is used to provide a debug adapter.
376 Also, some development boards integrate an FT2232 chip to serve as
377 a built-in low-cost debug adapter and USB-to-serial solution.
381 @* Link @url{http://elk.informatik.fh-augsburg.de/hhweb/doc/openocd/usbjtag/usbjtag.html}
383 @* See: @url{http://www.amontec.com/jtagkey.shtml}
385 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
387 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
389 @* See: @url{http://www.signalyzer.com}
390 @item @b{Stellaris Eval Boards}
391 @* See: @url{http://www.ti.com} - The Stellaris eval boards
392 bundle FT2232-based JTAG and SWD support, which can be used to debug
393 the Stellaris chips. Using separate JTAG adapters is optional.
394 These boards can also be used in a "pass through" mode as JTAG adapters
395 to other target boards, disabling the Stellaris chip.
396 @item @b{TI/Luminary ICDI}
397 @* See: @url{http://www.ti.com} - TI/Luminary In-Circuit Debug
398 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
399 Evaluation Kits. Like the non-detachable FT2232 support on the other
400 Stellaris eval boards, they can be used to debug other target boards.
401 @item @b{olimex-jtag}
402 @* See: @url{http://www.olimex.com}
403 @item @b{Flyswatter/Flyswatter2}
404 @* See: @url{http://www.tincantools.com}
405 @item @b{turtelizer2}
407 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
408 @url{http://www.ethernut.de}
410 @* Link: @url{http://www.hitex.com/index.php?id=383}
412 @* Link @url{http://www.hitex.com/stm32-stick}
413 @item @b{axm0432_jtag}
414 @* Axiom AXM-0432 Link @url{http://www.axman.com} - NOTE: This JTAG does not appear
415 to be available anymore as of April 2012.
417 @* Link @url{http://www.hitex.com/index.php?id=cortino}
418 @item @b{dlp-usb1232h}
419 @* Link @url{http://www.dlpdesign.com/usb/usb1232h.shtml}
420 @item @b{digilent-hs1}
421 @* Link @url{http://www.digilentinc.com/Products/Detail.cfm?Prod=JTAG-HS1}
423 @* Link @url{http://code.google.com/p/opendous/wiki/JTAG} FT2232H-based
425 @item @b{JTAG-lock-pick Tiny 2}
426 @* Link @url{http://www.distortec.com/jtag-lock-pick-tiny-2} FT232H-based
429 @* Link: @url{http://shop.gateworks.com/index.php?route=product/product&path=70_80&product_id=64}
433 @section USB-JTAG / Altera USB-Blaster compatibles
435 These devices also show up as FTDI devices, but are not
436 protocol-compatible with the FT2232 devices. They are, however,
437 protocol-compatible among themselves. USB-JTAG devices typically consist
438 of a FT245 followed by a CPLD that understands a particular protocol,
439 or emulates this protocol using some other hardware.
441 They may appear under different USB VID/PID depending on the particular
442 product. The driver can be configured to search for any VID/PID pair
443 (see the section on driver commands).
446 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
447 @* Link: @url{http://ixo-jtag.sourceforge.net/}
448 @item @b{Altera USB-Blaster}
449 @* Link: @url{http://www.altera.com/literature/ug/ug_usb_blstr.pdf}
452 @section USB J-Link based
453 There are several OEM versions of the SEGGER @b{J-Link} adapter. It is
454 an example of a microcontroller based JTAG adapter, it uses an
455 AT91SAM764 internally.
458 @item @b{SEGGER J-Link}
459 @* Link: @url{http://www.segger.com/jlink.html}
460 @item @b{Atmel SAM-ICE} (Only works with Atmel chips!)
461 @* Link: @url{http://www.atmel.com/tools/atmelsam-ice.aspx}
465 @section USB RLINK based
466 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer,
467 permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for
468 SWD and not JTAG, thus not supported.
471 @item @b{Raisonance RLink}
472 @* Link: @url{http://www.mcu-raisonance.com/~rlink-debugger-programmer__@/microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html}
473 @item @b{STM32 Primer}
474 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
475 @item @b{STM32 Primer2}
476 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
479 @section USB ST-LINK based
480 ST Micro has an adapter called @b{ST-LINK}.
481 They only work with ST Micro chips, notably STM32 and STM8.
485 @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
486 @* Link: @url{http://www.st.com/internet/evalboard/product/219866.jsp}
488 @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
489 @* Link: @url{http://www.st.com/internet/evalboard/product/251168.jsp}
492 For info the original ST-LINK enumerates using the mass storage usb class; however,
493 its implementation is completely broken. The result is this causes issues under Linux.
494 The simplest solution is to get Linux to ignore the ST-LINK using one of the following methods:
496 @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
497 @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
500 @section USB TI/Stellaris ICDI based
501 Texas Instruments has an adapter called @b{ICDI}.
502 It is not to be confused with the FTDI based adapters that were originally fitted to their
503 evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
505 @section USB CMSIS-DAP based
506 ARM has released a interface standard called CMSIS-DAP that simplifies connecting
507 debuggers to ARM Cortex based targets @url{http://www.keil.com/support/man/docs/dapdebug/dapdebug_introduction.htm}.
512 @* Link: @url{http://shop.embedded-projects.net/} - which uses an Atmel MEGA32 and a UBN9604
514 @item @b{USB - Presto}
515 @* Link: @url{http://tools.asix.net/prg_presto.htm}
517 @item @b{Versaloon-Link}
518 @* Link: @url{http://www.versaloon.com}
520 @item @b{ARM-JTAG-EW}
521 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
524 @* Link: @url{http://dangerousprototypes.com/bus-pirate-manual/}
527 @* Link: @url{http://code.google.com/p/opendous-jtag/} - which uses an AT90USB162
530 @* Link: @url{http://code.google.com/p/estick-jtag/}
532 @item @b{Keil ULINK v1}
533 @* Link: @url{http://www.keil.com/ulink1/}
536 @section IBM PC Parallel Printer Port Based
538 The two well-known ``JTAG Parallel Ports'' cables are the Xilinx DLC5
539 and the Macraigor Wiggler. There are many clones and variations of
542 Note that parallel ports are becoming much less common, so if you
543 have the choice you should probably avoid these adapters in favor
548 @item @b{Wiggler} - There are many clones of this.
549 @* Link: @url{http://www.macraigor.com/wiggler.htm}
551 @item @b{DLC5} - From XILINX - There are many clones of this
552 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
553 produced, PDF schematics are easily found and it is easy to make.
555 @item @b{Amontec - JTAG Accelerator}
556 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
559 @* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
561 @item @b{Wiggler_ntrst_inverted}
562 @* Yet another variation - See the source code, src/jtag/parport.c
564 @item @b{old_amt_wiggler}
565 @* Unknown - probably not on the market today
568 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
571 @* Link: @url{http://www.amontec.com/chameleon.shtml}
577 @* ispDownload from Lattice Semiconductor
578 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
581 @* From ST Microsystems;
582 @* Link: @url{http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATA_BRIEF/DM00039500.pdf}
590 @* An EP93xx based Linux machine using the GPIO pins directly.
593 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
595 @item @b{bcm2835gpio}
596 @* A BCM2835-based board (e.g. Raspberry Pi) using the GPIO pins of the expansion header.
599 @* A JTAG driver acting as a client for the JTAG VPI server interface.
600 @* Link: @url{http://github.com/fjullien/jtag_vpi}
605 @chapter About Jim-Tcl
609 OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
610 This programming language provides a simple and extensible
613 All commands presented in this Guide are extensions to Jim-Tcl.
614 You can use them as simple commands, without needing to learn
615 much of anything about Tcl.
616 Alternatively, you can write Tcl programs with them.
618 You can learn more about Jim at its website, @url{http://jim.tcl.tk}.
619 There is an active and responsive community, get on the mailing list
620 if you have any questions. Jim-Tcl maintainers also lurk on the
621 OpenOCD mailing list.
624 @item @b{Jim vs. Tcl}
625 @* Jim-Tcl is a stripped down version of the well known Tcl language,
626 which can be found here: @url{http://www.tcl.tk}. Jim-Tcl has far
627 fewer features. Jim-Tcl is several dozens of .C files and .H files and
628 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
629 4.2 MB .zip file containing 1540 files.
631 @item @b{Missing Features}
632 @* Our practice has been: Add/clone the real Tcl feature if/when
633 needed. We welcome Jim-Tcl improvements, not bloat. Also there
634 are a large number of optional Jim-Tcl features that are not
638 @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
639 command interpreter today is a mixture of (newer)
640 Jim-Tcl commands, and the (older) original command interpreter.
643 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
644 can type a Tcl for() loop, set variables, etc.
645 Some of the commands documented in this guide are implemented
646 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
648 @item @b{Historical Note}
649 @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
650 before OpenOCD 0.5 release, OpenOCD switched to using Jim-Tcl
651 as a Git submodule, which greatly simplified upgrading Jim-Tcl
652 to benefit from new features and bugfixes in Jim-Tcl.
654 @item @b{Need a crash course in Tcl?}
655 @*@xref{Tcl Crash Course}.
660 @cindex command line options
662 @cindex directory search
664 Properly installing OpenOCD sets up your operating system to grant it access
665 to the debug adapters. On Linux, this usually involves installing a file
666 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. An example rules file
667 that works for many common adapters is shipped with OpenOCD in the
668 @file{contrib} directory. MS-Windows needs
669 complex and confusing driver configuration for every peripheral. Such issues
670 are unique to each operating system, and are not detailed in this User's Guide.
672 Then later you will invoke the OpenOCD server, with various options to
673 tell it how each debug session should work.
674 The @option{--help} option shows:
678 --help | -h display this help
679 --version | -v display OpenOCD version
680 --file | -f use configuration file <name>
681 --search | -s dir to search for config files and scripts
682 --debug | -d set debug level <0-3>
683 --log_output | -l redirect log output to file <name>
684 --command | -c run <command>
687 If you don't give any @option{-f} or @option{-c} options,
688 OpenOCD tries to read the configuration file @file{openocd.cfg}.
689 To specify one or more different
690 configuration files, use @option{-f} options. For example:
693 openocd -f config1.cfg -f config2.cfg -f config3.cfg
696 Configuration files and scripts are searched for in
698 @item the current directory,
699 @item any search dir specified on the command line using the @option{-s} option,
700 @item any search dir specified using the @command{add_script_search_dir} command,
701 @item @file{$HOME/.openocd} (not on Windows),
702 @item a directory in the @env{OPENOCD_SCRIPTS} environment variable (if set),
703 @item the site wide script library @file{$pkgdatadir/site} and
704 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
706 The first found file with a matching file name will be used.
709 Don't try to use configuration script names or paths which
710 include the "#" character. That character begins Tcl comments.
713 @section Simple setup, no customization
715 In the best case, you can use two scripts from one of the script
716 libraries, hook up your JTAG adapter, and start the server ... and
717 your JTAG setup will just work "out of the box". Always try to
718 start by reusing those scripts, but assume you'll need more
719 customization even if this works. @xref{OpenOCD Project Setup}.
721 If you find a script for your JTAG adapter, and for your board or
722 target, you may be able to hook up your JTAG adapter then start
723 the server with some variation of one of the following:
726 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
727 openocd -f interface/ftdi/ADAPTER.cfg -f board/MYBOARD.cfg
730 You might also need to configure which reset signals are present,
731 using @option{-c 'reset_config trst_and_srst'} or something similar.
732 If all goes well you'll see output something like
735 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
736 For bug reports, read
737 http://openocd.org/doc/doxygen/bugs.html
738 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
739 (mfg: 0x23b, part: 0xba00, ver: 0x3)
742 Seeing that "tap/device found" message, and no warnings, means
743 the JTAG communication is working. That's a key milestone, but
744 you'll probably need more project-specific setup.
746 @section What OpenOCD does as it starts
748 OpenOCD starts by processing the configuration commands provided
749 on the command line or, if there were no @option{-c command} or
750 @option{-f file.cfg} options given, in @file{openocd.cfg}.
751 @xref{configurationstage,,Configuration Stage}.
752 At the end of the configuration stage it verifies the JTAG scan
753 chain defined using those commands; your configuration should
754 ensure that this always succeeds.
755 Normally, OpenOCD then starts running as a daemon.
756 Alternatively, commands may be used to terminate the configuration
757 stage early, perform work (such as updating some flash memory),
758 and then shut down without acting as a daemon.
760 Once OpenOCD starts running as a daemon, it waits for connections from
761 clients (Telnet, GDB, Other) and processes the commands issued through
764 If you are having problems, you can enable internal debug messages via
765 the @option{-d} option.
767 Also it is possible to interleave Jim-Tcl commands w/config scripts using the
768 @option{-c} command line switch.
770 To enable debug output (when reporting problems or working on OpenOCD
771 itself), use the @option{-d} command line switch. This sets the
772 @option{debug_level} to "3", outputting the most information,
773 including debug messages. The default setting is "2", outputting only
774 informational messages, warnings and errors. You can also change this
775 setting from within a telnet or gdb session using @command{debug_level<n>}
776 (@pxref{debuglevel,,debug_level}).
778 You can redirect all output from the daemon to a file using the
779 @option{-l <logfile>} switch.
781 Note! OpenOCD will launch the GDB & telnet server even if it can not
782 establish a connection with the target. In general, it is possible for
783 the JTAG controller to be unresponsive until the target is set up
784 correctly via e.g. GDB monitor commands in a GDB init script.
786 @node OpenOCD Project Setup
787 @chapter OpenOCD Project Setup
789 To use OpenOCD with your development projects, you need to do more than
790 just connect the JTAG adapter hardware (dongle) to your development board
791 and start the OpenOCD server.
792 You also need to configure your OpenOCD server so that it knows
793 about your adapter and board, and helps your work.
794 You may also want to connect OpenOCD to GDB, possibly
795 using Eclipse or some other GUI.
797 @section Hooking up the JTAG Adapter
799 Today's most common case is a dongle with a JTAG cable on one side
800 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
801 and a USB cable on the other.
802 Instead of USB, some cables use Ethernet;
803 older ones may use a PC parallel port, or even a serial port.
806 @item @emph{Start with power to your target board turned off},
807 and nothing connected to your JTAG adapter.
808 If you're particularly paranoid, unplug power to the board.
809 It's important to have the ground signal properly set up,
810 unless you are using a JTAG adapter which provides
811 galvanic isolation between the target board and the
814 @item @emph{Be sure it's the right kind of JTAG connector.}
815 If your dongle has a 20-pin ARM connector, you need some kind
816 of adapter (or octopus, see below) to hook it up to
817 boards using 14-pin or 10-pin connectors ... or to 20-pin
818 connectors which don't use ARM's pinout.
820 In the same vein, make sure the voltage levels are compatible.
821 Not all JTAG adapters have the level shifters needed to work
822 with 1.2 Volt boards.
824 @item @emph{Be certain the cable is properly oriented} or you might
825 damage your board. In most cases there are only two possible
826 ways to connect the cable.
827 Connect the JTAG cable from your adapter to the board.
828 Be sure it's firmly connected.
830 In the best case, the connector is keyed to physically
831 prevent you from inserting it wrong.
832 This is most often done using a slot on the board's male connector
833 housing, which must match a key on the JTAG cable's female connector.
834 If there's no housing, then you must look carefully and
835 make sure pin 1 on the cable hooks up to pin 1 on the board.
836 Ribbon cables are frequently all grey except for a wire on one
837 edge, which is red. The red wire is pin 1.
839 Sometimes dongles provide cables where one end is an ``octopus'' of
840 color coded single-wire connectors, instead of a connector block.
841 These are great when converting from one JTAG pinout to another,
842 but are tedious to set up.
843 Use these with connector pinout diagrams to help you match up the
844 adapter signals to the right board pins.
846 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
847 A USB, parallel, or serial port connector will go to the host which
848 you are using to run OpenOCD.
849 For Ethernet, consult the documentation and your network administrator.
851 For USB-based JTAG adapters you have an easy sanity check at this point:
852 does the host operating system see the JTAG adapter? If you're running
853 Linux, try the @command{lsusb} command. If that host is an
854 MS-Windows host, you'll need to install a driver before OpenOCD works.
856 @item @emph{Connect the adapter's power supply, if needed.}
857 This step is primarily for non-USB adapters,
858 but sometimes USB adapters need extra power.
860 @item @emph{Power up the target board.}
861 Unless you just let the magic smoke escape,
862 you're now ready to set up the OpenOCD server
863 so you can use JTAG to work with that board.
867 Talk with the OpenOCD server using
868 telnet (@code{telnet localhost 4444} on many systems) or GDB.
869 @xref{GDB and OpenOCD}.
871 @section Project Directory
873 There are many ways you can configure OpenOCD and start it up.
875 A simple way to organize them all involves keeping a
876 single directory for your work with a given board.
877 When you start OpenOCD from that directory,
878 it searches there first for configuration files, scripts,
879 files accessed through semihosting,
880 and for code you upload to the target board.
881 It is also the natural place to write files,
882 such as log files and data you download from the board.
884 @section Configuration Basics
886 There are two basic ways of configuring OpenOCD, and
887 a variety of ways you can mix them.
888 Think of the difference as just being how you start the server:
891 @item Many @option{-f file} or @option{-c command} options on the command line
892 @item No options, but a @dfn{user config file}
893 in the current directory named @file{openocd.cfg}
896 Here is an example @file{openocd.cfg} file for a setup
897 using a Signalyzer FT2232-based JTAG adapter to talk to
898 a board with an Atmel AT91SAM7X256 microcontroller:
901 source [find interface/signalyzer.cfg]
903 # GDB can also flash my flash!
904 gdb_memory_map enable
905 gdb_flash_program enable
907 source [find target/sam7x256.cfg]
910 Here is the command line equivalent of that configuration:
913 openocd -f interface/signalyzer.cfg \
914 -c "gdb_memory_map enable" \
915 -c "gdb_flash_program enable" \
916 -f target/sam7x256.cfg
919 You could wrap such long command lines in shell scripts,
920 each supporting a different development task.
921 One might re-flash the board with a specific firmware version.
922 Another might set up a particular debugging or run-time environment.
925 At this writing (October 2009) the command line method has
926 problems with how it treats variables.
927 For example, after @option{-c "set VAR value"}, or doing the
928 same in a script, the variable @var{VAR} will have no value
929 that can be tested in a later script.
932 Here we will focus on the simpler solution: one user config
933 file, including basic configuration plus any TCL procedures
934 to simplify your work.
936 @section User Config Files
937 @cindex config file, user
938 @cindex user config file
939 @cindex config file, overview
941 A user configuration file ties together all the parts of a project
943 One of the following will match your situation best:
946 @item Ideally almost everything comes from configuration files
947 provided by someone else.
948 For example, OpenOCD distributes a @file{scripts} directory
949 (probably in @file{/usr/share/openocd/scripts} on Linux).
950 Board and tool vendors can provide these too, as can individual
951 user sites; the @option{-s} command line option lets you say
952 where to find these files. (@xref{Running}.)
953 The AT91SAM7X256 example above works this way.
955 Three main types of non-user configuration file each have their
956 own subdirectory in the @file{scripts} directory:
959 @item @b{interface} -- one for each different debug adapter;
960 @item @b{board} -- one for each different board
961 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
964 Best case: include just two files, and they handle everything else.
965 The first is an interface config file.
966 The second is board-specific, and it sets up the JTAG TAPs and
967 their GDB targets (by deferring to some @file{target.cfg} file),
968 declares all flash memory, and leaves you nothing to do except
972 source [find interface/olimex-jtag-tiny.cfg]
973 source [find board/csb337.cfg]
976 Boards with a single microcontroller often won't need more
977 than the target config file, as in the AT91SAM7X256 example.
978 That's because there is no external memory (flash, DDR RAM), and
979 the board differences are encapsulated by application code.
981 @item Maybe you don't know yet what your board looks like to JTAG.
982 Once you know the @file{interface.cfg} file to use, you may
983 need help from OpenOCD to discover what's on the board.
984 Once you find the JTAG TAPs, you can just search for appropriate
986 configuration files ... or write your own, from the bottom up.
987 @xref{autoprobing,,Autoprobing}.
989 @item You can often reuse some standard config files but
990 need to write a few new ones, probably a @file{board.cfg} file.
991 You will be using commands described later in this User's Guide,
992 and working with the guidelines in the next chapter.
994 For example, there may be configuration files for your JTAG adapter
995 and target chip, but you need a new board-specific config file
996 giving access to your particular flash chips.
997 Or you might need to write another target chip configuration file
998 for a new chip built around the Cortex M3 core.
1001 When you write new configuration files, please submit
1002 them for inclusion in the next OpenOCD release.
1003 For example, a @file{board/newboard.cfg} file will help the
1004 next users of that board, and a @file{target/newcpu.cfg}
1005 will help support users of any board using that chip.
1009 You may may need to write some C code.
1010 It may be as simple as supporting a new FT2232 or parport
1011 based adapter; a bit more involved, like a NAND or NOR flash
1012 controller driver; or a big piece of work like supporting
1013 a new chip architecture.
1016 Reuse the existing config files when you can.
1017 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
1018 You may find a board configuration that's a good example to follow.
1020 When you write config files, separate the reusable parts
1021 (things every user of that interface, chip, or board needs)
1022 from ones specific to your environment and debugging approach.
1026 For example, a @code{gdb-attach} event handler that invokes
1027 the @command{reset init} command will interfere with debugging
1028 early boot code, which performs some of the same actions
1029 that the @code{reset-init} event handler does.
1032 Likewise, the @command{arm9 vector_catch} command (or
1033 @cindex vector_catch
1034 its siblings @command{xscale vector_catch}
1035 and @command{cortex_m vector_catch}) can be a timesaver
1036 during some debug sessions, but don't make everyone use that either.
1037 Keep those kinds of debugging aids in your user config file,
1038 along with messaging and tracing setup.
1039 (@xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.)
1042 You might need to override some defaults.
1043 For example, you might need to move, shrink, or back up the target's
1044 work area if your application needs much SRAM.
1047 TCP/IP port configuration is another example of something which
1048 is environment-specific, and should only appear in
1049 a user config file. @xref{tcpipports,,TCP/IP Ports}.
1052 @section Project-Specific Utilities
1054 A few project-specific utility
1055 routines may well speed up your work.
1056 Write them, and keep them in your project's user config file.
1058 For example, if you are making a boot loader work on a
1059 board, it's nice to be able to debug the ``after it's
1060 loaded to RAM'' parts separately from the finicky early
1061 code which sets up the DDR RAM controller and clocks.
1062 A script like this one, or a more GDB-aware sibling,
1066 proc ramboot @{ @} @{
1067 # Reset, running the target's "reset-init" scripts
1068 # to initialize clocks and the DDR RAM controller.
1069 # Leave the CPU halted.
1072 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
1073 load_image u-boot.bin 0x20000000
1080 Then once that code is working you will need to make it
1081 boot from NOR flash; a different utility would help.
1082 Alternatively, some developers write to flash using GDB.
1083 (You might use a similar script if you're working with a flash
1084 based microcontroller application instead of a boot loader.)
1087 proc newboot @{ @} @{
1088 # Reset, leaving the CPU halted. The "reset-init" event
1089 # proc gives faster access to the CPU and to NOR flash;
1090 # "reset halt" would be slower.
1093 # Write standard version of U-Boot into the first two
1094 # sectors of NOR flash ... the standard version should
1095 # do the same lowlevel init as "reset-init".
1096 flash protect 0 0 1 off
1097 flash erase_sector 0 0 1
1098 flash write_bank 0 u-boot.bin 0x0
1099 flash protect 0 0 1 on
1101 # Reboot from scratch using that new boot loader.
1106 You may need more complicated utility procedures when booting
1108 That often involves an extra bootloader stage,
1109 running from on-chip SRAM to perform DDR RAM setup so it can load
1110 the main bootloader code (which won't fit into that SRAM).
1112 Other helper scripts might be used to write production system images,
1113 involving considerably more than just a three stage bootloader.
1115 @section Target Software Changes
1117 Sometimes you may want to make some small changes to the software
1118 you're developing, to help make JTAG debugging work better.
1119 For example, in C or assembly language code you might
1120 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1121 handling issues like:
1125 @item @b{Watchdog Timers}...
1126 Watchog timers are typically used to automatically reset systems if
1127 some application task doesn't periodically reset the timer. (The
1128 assumption is that the system has locked up if the task can't run.)
1129 When a JTAG debugger halts the system, that task won't be able to run
1130 and reset the timer ... potentially causing resets in the middle of
1131 your debug sessions.
1133 It's rarely a good idea to disable such watchdogs, since their usage
1134 needs to be debugged just like all other parts of your firmware.
1135 That might however be your only option.
1137 Look instead for chip-specific ways to stop the watchdog from counting
1138 while the system is in a debug halt state. It may be simplest to set
1139 that non-counting mode in your debugger startup scripts. You may however
1140 need a different approach when, for example, a motor could be physically
1141 damaged by firmware remaining inactive in a debug halt state. That might
1142 involve a type of firmware mode where that "non-counting" mode is disabled
1143 at the beginning then re-enabled at the end; a watchdog reset might fire
1144 and complicate the debug session, but hardware (or people) would be
1145 protected.@footnote{Note that many systems support a "monitor mode" debug
1146 that is a somewhat cleaner way to address such issues. You can think of
1147 it as only halting part of the system, maybe just one task,
1148 instead of the whole thing.
1149 At this writing, January 2010, OpenOCD based debugging does not support
1150 monitor mode debug, only "halt mode" debug.}
1152 @item @b{ARM Semihosting}...
1153 @cindex ARM semihosting
1154 When linked with a special runtime library provided with many
1155 toolchains@footnote{See chapter 8 "Semihosting" in
1156 @uref{http://infocenter.arm.com/help/topic/com.arm.doc.dui0203i/DUI0203I_rvct_developer_guide.pdf,
1157 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1158 The CodeSourcery EABI toolchain also includes a semihosting library.},
1159 your target code can use I/O facilities on the debug host. That library
1160 provides a small set of system calls which are handled by OpenOCD.
1161 It can let the debugger provide your system console and a file system,
1162 helping with early debugging or providing a more capable environment
1163 for sometimes-complex tasks like installing system firmware onto
1166 @item @b{ARM Wait-For-Interrupt}...
1167 Many ARM chips synchronize the JTAG clock using the core clock.
1168 Low power states which stop that core clock thus prevent JTAG access.
1169 Idle loops in tasking environments often enter those low power states
1170 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1172 You may want to @emph{disable that instruction} in source code,
1173 or otherwise prevent using that state,
1174 to ensure you can get JTAG access at any time.@footnote{As a more
1175 polite alternative, some processors have special debug-oriented
1176 registers which can be used to change various features including
1177 how the low power states are clocked while debugging.
1178 The STM32 DBGMCU_CR register is an example; at the cost of extra
1179 power consumption, JTAG can be used during low power states.}
1180 For example, the OpenOCD @command{halt} command may not
1181 work for an idle processor otherwise.
1183 @item @b{Delay after reset}...
1184 Not all chips have good support for debugger access
1185 right after reset; many LPC2xxx chips have issues here.
1186 Similarly, applications that reconfigure pins used for
1187 JTAG access as they start will also block debugger access.
1189 To work with boards like this, @emph{enable a short delay loop}
1190 the first thing after reset, before "real" startup activities.
1191 For example, one second's delay is usually more than enough
1192 time for a JTAG debugger to attach, so that
1193 early code execution can be debugged
1194 or firmware can be replaced.
1196 @item @b{Debug Communications Channel (DCC)}...
1197 Some processors include mechanisms to send messages over JTAG.
1198 Many ARM cores support these, as do some cores from other vendors.
1199 (OpenOCD may be able to use this DCC internally, speeding up some
1200 operations like writing to memory.)
1202 Your application may want to deliver various debugging messages
1203 over JTAG, by @emph{linking with a small library of code}
1204 provided with OpenOCD and using the utilities there to send
1205 various kinds of message.
1206 @xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.
1210 @section Target Hardware Setup
1212 Chip vendors often provide software development boards which
1213 are highly configurable, so that they can support all options
1214 that product boards may require. @emph{Make sure that any
1215 jumpers or switches match the system configuration you are
1218 Common issues include:
1222 @item @b{JTAG setup} ...
1223 Boards may support more than one JTAG configuration.
1224 Examples include jumpers controlling pullups versus pulldowns
1225 on the nTRST and/or nSRST signals, and choice of connectors
1226 (e.g. which of two headers on the base board,
1227 or one from a daughtercard).
1228 For some Texas Instruments boards, you may need to jumper the
1229 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1231 @item @b{Boot Modes} ...
1232 Complex chips often support multiple boot modes, controlled
1233 by external jumpers. Make sure this is set up correctly.
1234 For example many i.MX boards from NXP need to be jumpered
1235 to "ATX mode" to start booting using the on-chip ROM, when
1236 using second stage bootloader code stored in a NAND flash chip.
1238 Such explicit configuration is common, and not limited to
1239 booting from NAND. You might also need to set jumpers to
1240 start booting using code loaded from an MMC/SD card; external
1241 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1242 flash; some external host; or various other sources.
1245 @item @b{Memory Addressing} ...
1246 Boards which support multiple boot modes may also have jumpers
1247 to configure memory addressing. One board, for example, jumpers
1248 external chipselect 0 (used for booting) to address either
1249 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1250 or NAND flash. When it's jumpered to address NAND flash, that
1251 board must also be told to start booting from on-chip ROM.
1253 Your @file{board.cfg} file may also need to be told this jumper
1254 configuration, so that it can know whether to declare NOR flash
1255 using @command{flash bank} or instead declare NAND flash with
1256 @command{nand device}; and likewise which probe to perform in
1257 its @code{reset-init} handler.
1259 A closely related issue is bus width. Jumpers might need to
1260 distinguish between 8 bit or 16 bit bus access for the flash
1261 used to start booting.
1263 @item @b{Peripheral Access} ...
1264 Development boards generally provide access to every peripheral
1265 on the chip, sometimes in multiple modes (such as by providing
1266 multiple audio codec chips).
1267 This interacts with software
1268 configuration of pin multiplexing, where for example a
1269 given pin may be routed either to the MMC/SD controller
1270 or the GPIO controller. It also often interacts with
1271 configuration jumpers. One jumper may be used to route
1272 signals to an MMC/SD card slot or an expansion bus (which
1273 might in turn affect booting); others might control which
1274 audio or video codecs are used.
1278 Plus you should of course have @code{reset-init} event handlers
1279 which set up the hardware to match that jumper configuration.
1280 That includes in particular any oscillator or PLL used to clock
1281 the CPU, and any memory controllers needed to access external
1282 memory and peripherals. Without such handlers, you won't be
1283 able to access those resources without working target firmware
1284 which can do that setup ... this can be awkward when you're
1285 trying to debug that target firmware. Even if there's a ROM
1286 bootloader which handles a few issues, it rarely provides full
1287 access to all board-specific capabilities.
1290 @node Config File Guidelines
1291 @chapter Config File Guidelines
1293 This chapter is aimed at any user who needs to write a config file,
1294 including developers and integrators of OpenOCD and any user who
1295 needs to get a new board working smoothly.
1296 It provides guidelines for creating those files.
1298 You should find the following directories under
1299 @t{$(INSTALLDIR)/scripts}, with config files maintained upstream. Use
1300 them as-is where you can; or as models for new files.
1302 @item @file{interface} ...
1303 These are for debug adapters. Files that specify configuration to use
1304 specific JTAG, SWD and other adapters go here.
1305 @item @file{board} ...
1306 Think Circuit Board, PWA, PCB, they go by many names. Board files
1307 contain initialization items that are specific to a board.
1309 They reuse target configuration files, since the same
1310 microprocessor chips are used on many boards,
1311 but support for external parts varies widely. For
1312 example, the SDRAM initialization sequence for the board, or the type
1313 of external flash and what address it uses. Any initialization
1314 sequence to enable that external flash or SDRAM should be found in the
1315 board file. Boards may also contain multiple targets: two CPUs; or
1317 @item @file{target} ...
1318 Think chip. The ``target'' directory represents the JTAG TAPs
1320 which OpenOCD should control, not a board. Two common types of targets
1321 are ARM chips and FPGA or CPLD chips.
1322 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1323 the target config file defines all of them.
1324 @item @emph{more} ... browse for other library files which may be useful.
1325 For example, there are various generic and CPU-specific utilities.
1328 The @file{openocd.cfg} user config
1329 file may override features in any of the above files by
1330 setting variables before sourcing the target file, or by adding
1331 commands specific to their situation.
1333 @section Interface Config Files
1335 The user config file
1336 should be able to source one of these files with a command like this:
1339 source [find interface/FOOBAR.cfg]
1342 A preconfigured interface file should exist for every debug adapter
1343 in use today with OpenOCD.
1344 That said, perhaps some of these config files
1345 have only been used by the developer who created it.
1347 A separate chapter gives information about how to set these up.
1348 @xref{Debug Adapter Configuration}.
1349 Read the OpenOCD source code (and Developer's Guide)
1350 if you have a new kind of hardware interface
1351 and need to provide a driver for it.
1353 @section Board Config Files
1354 @cindex config file, board
1355 @cindex board config file
1357 The user config file
1358 should be able to source one of these files with a command like this:
1361 source [find board/FOOBAR.cfg]
1364 The point of a board config file is to package everything
1365 about a given board that user config files need to know.
1366 In summary the board files should contain (if present)
1369 @item One or more @command{source [find target/...cfg]} statements
1370 @item NOR flash configuration (@pxref{norconfiguration,,NOR Configuration})
1371 @item NAND flash configuration (@pxref{nandconfiguration,,NAND Configuration})
1372 @item Target @code{reset} handlers for SDRAM and I/O configuration
1373 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1374 @item All things that are not ``inside a chip''
1377 Generic things inside target chips belong in target config files,
1378 not board config files. So for example a @code{reset-init} event
1379 handler should know board-specific oscillator and PLL parameters,
1380 which it passes to target-specific utility code.
1382 The most complex task of a board config file is creating such a
1383 @code{reset-init} event handler.
1384 Define those handlers last, after you verify the rest of the board
1385 configuration works.
1387 @subsection Communication Between Config files
1389 In addition to target-specific utility code, another way that
1390 board and target config files communicate is by following a
1391 convention on how to use certain variables.
1393 The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
1394 Thus the rule we follow in OpenOCD is this: Variables that begin with
1395 a leading underscore are temporary in nature, and can be modified and
1396 used at will within a target configuration file.
1398 Complex board config files can do the things like this,
1399 for a board with three chips:
1402 # Chip #1: PXA270 for network side, big endian
1403 set CHIPNAME network
1405 source [find target/pxa270.cfg]
1406 # on return: _TARGETNAME = network.cpu
1407 # other commands can refer to the "network.cpu" target.
1408 $_TARGETNAME configure .... events for this CPU..
1410 # Chip #2: PXA270 for video side, little endian
1413 source [find target/pxa270.cfg]
1414 # on return: _TARGETNAME = video.cpu
1415 # other commands can refer to the "video.cpu" target.
1416 $_TARGETNAME configure .... events for this CPU..
1418 # Chip #3: Xilinx FPGA for glue logic
1421 source [find target/spartan3.cfg]
1424 That example is oversimplified because it doesn't show any flash memory,
1425 or the @code{reset-init} event handlers to initialize external DRAM
1426 or (assuming it needs it) load a configuration into the FPGA.
1427 Such features are usually needed for low-level work with many boards,
1428 where ``low level'' implies that the board initialization software may
1429 not be working. (That's a common reason to need JTAG tools. Another
1430 is to enable working with microcontroller-based systems, which often
1431 have no debugging support except a JTAG connector.)
1433 Target config files may also export utility functions to board and user
1434 config files. Such functions should use name prefixes, to help avoid
1437 Board files could also accept input variables from user config files.
1438 For example, there might be a @code{J4_JUMPER} setting used to identify
1439 what kind of flash memory a development board is using, or how to set
1440 up other clocks and peripherals.
1442 @subsection Variable Naming Convention
1443 @cindex variable names
1445 Most boards have only one instance of a chip.
1446 However, it should be easy to create a board with more than
1447 one such chip (as shown above).
1448 Accordingly, we encourage these conventions for naming
1449 variables associated with different @file{target.cfg} files,
1450 to promote consistency and
1451 so that board files can override target defaults.
1453 Inputs to target config files include:
1456 @item @code{CHIPNAME} ...
1457 This gives a name to the overall chip, and is used as part of
1458 tap identifier dotted names.
1459 While the default is normally provided by the chip manufacturer,
1460 board files may need to distinguish between instances of a chip.
1461 @item @code{ENDIAN} ...
1462 By default @option{little} - although chips may hard-wire @option{big}.
1463 Chips that can't change endianness don't need to use this variable.
1464 @item @code{CPUTAPID} ...
1465 When OpenOCD examines the JTAG chain, it can be told verify the
1466 chips against the JTAG IDCODE register.
1467 The target file will hold one or more defaults, but sometimes the
1468 chip in a board will use a different ID (perhaps a newer revision).
1471 Outputs from target config files include:
1474 @item @code{_TARGETNAME} ...
1475 By convention, this variable is created by the target configuration
1476 script. The board configuration file may make use of this variable to
1477 configure things like a ``reset init'' script, or other things
1478 specific to that board and that target.
1479 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1480 @code{_TARGETNAME1}, ... etc.
1483 @subsection The reset-init Event Handler
1484 @cindex event, reset-init
1485 @cindex reset-init handler
1487 Board config files run in the OpenOCD configuration stage;
1488 they can't use TAPs or targets, since they haven't been
1490 This means you can't write memory or access chip registers;
1491 you can't even verify that a flash chip is present.
1492 That's done later in event handlers, of which the target @code{reset-init}
1493 handler is one of the most important.
1495 Except on microcontrollers, the basic job of @code{reset-init} event
1496 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1497 Microcontrollers rarely use boot loaders; they run right out of their
1498 on-chip flash and SRAM memory. But they may want to use one of these
1499 handlers too, if just for developer convenience.
1502 Because this is so very board-specific, and chip-specific, no examples
1504 Instead, look at the board config files distributed with OpenOCD.
1505 If you have a boot loader, its source code will help; so will
1506 configuration files for other JTAG tools
1507 (@pxref{translatingconfigurationfiles,,Translating Configuration Files}).
1510 Some of this code could probably be shared between different boards.
1511 For example, setting up a DRAM controller often doesn't differ by
1512 much except the bus width (16 bits or 32?) and memory timings, so a
1513 reusable TCL procedure loaded by the @file{target.cfg} file might take
1514 those as parameters.
1515 Similarly with oscillator, PLL, and clock setup;
1516 and disabling the watchdog.
1517 Structure the code cleanly, and provide comments to help
1518 the next developer doing such work.
1519 (@emph{You might be that next person} trying to reuse init code!)
1521 The last thing normally done in a @code{reset-init} handler is probing
1522 whatever flash memory was configured. For most chips that needs to be
1523 done while the associated target is halted, either because JTAG memory
1524 access uses the CPU or to prevent conflicting CPU access.
1526 @subsection JTAG Clock Rate
1528 Before your @code{reset-init} handler has set up
1529 the PLLs and clocking, you may need to run with
1530 a low JTAG clock rate.
1531 @xref{jtagspeed,,JTAG Speed}.
1532 Then you'd increase that rate after your handler has
1533 made it possible to use the faster JTAG clock.
1534 When the initial low speed is board-specific, for example
1535 because it depends on a board-specific oscillator speed, then
1536 you should probably set it up in the board config file;
1537 if it's target-specific, it belongs in the target config file.
1539 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1540 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1541 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1542 Consult chip documentation to determine the peak JTAG clock rate,
1543 which might be less than that.
1546 On most ARMs, JTAG clock detection is coupled to the core clock, so
1547 software using a @option{wait for interrupt} operation blocks JTAG access.
1548 Adaptive clocking provides a partial workaround, but a more complete
1549 solution just avoids using that instruction with JTAG debuggers.
1552 If both the chip and the board support adaptive clocking,
1553 use the @command{jtag_rclk}
1554 command, in case your board is used with JTAG adapter which
1555 also supports it. Otherwise use @command{adapter_khz}.
1556 Set the slow rate at the beginning of the reset sequence,
1557 and the faster rate as soon as the clocks are at full speed.
1559 @anchor{theinitboardprocedure}
1560 @subsection The init_board procedure
1561 @cindex init_board procedure
1563 The concept of @code{init_board} procedure is very similar to @code{init_targets}
1564 (@xref{theinittargetsprocedure,,The init_targets procedure}.) - it's a replacement of ``linear''
1565 configuration scripts. This procedure is meant to be executed when OpenOCD enters run stage
1566 (@xref{enteringtherunstage,,Entering the Run Stage},) after @code{init_targets}. The idea to have
1567 separate @code{init_targets} and @code{init_board} procedures is to allow the first one to configure
1568 everything target specific (internal flash, internal RAM, etc.) and the second one to configure
1569 everything board specific (reset signals, chip frequency, reset-init event handler, external memory, etc.).
1570 Additionally ``linear'' board config file will most likely fail when target config file uses
1571 @code{init_targets} scheme (``linear'' script is executed before @code{init} and @code{init_targets} - after),
1572 so separating these two configuration stages is very convenient, as the easiest way to overcome this
1573 problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
1574 need to override @code{init_targets} defined in target config files when they only need to add some specifics.
1576 Just as @code{init_targets}, the @code{init_board} procedure can be overridden by ``next level'' script (which sources
1577 the original), allowing greater code reuse.
1580 ### board_file.cfg ###
1582 # source target file that does most of the config in init_targets
1583 source [find target/target.cfg]
1585 proc enable_fast_clock @{@} @{
1586 # enables fast on-board clock source
1587 # configures the chip to use it
1590 # initialize only board specifics - reset, clock, adapter frequency
1591 proc init_board @{@} @{
1592 reset_config trst_and_srst trst_pulls_srst
1594 $_TARGETNAME configure -event reset-init @{
1602 @section Target Config Files
1603 @cindex config file, target
1604 @cindex target config file
1606 Board config files communicate with target config files using
1607 naming conventions as described above, and may source one or
1608 more target config files like this:
1611 source [find target/FOOBAR.cfg]
1614 The point of a target config file is to package everything
1615 about a given chip that board config files need to know.
1616 In summary the target files should contain
1620 @item Add TAPs to the scan chain
1621 @item Add CPU targets (includes GDB support)
1622 @item CPU/Chip/CPU-Core specific features
1626 As a rule of thumb, a target file sets up only one chip.
1627 For a microcontroller, that will often include a single TAP,
1628 which is a CPU needing a GDB target, and its on-chip flash.
1630 More complex chips may include multiple TAPs, and the target
1631 config file may need to define them all before OpenOCD
1632 can talk to the chip.
1633 For example, some phone chips have JTAG scan chains that include
1634 an ARM core for operating system use, a DSP,
1635 another ARM core embedded in an image processing engine,
1636 and other processing engines.
1638 @subsection Default Value Boiler Plate Code
1640 All target configuration files should start with code like this,
1641 letting board config files express environment-specific
1642 differences in how things should be set up.
1645 # Boards may override chip names, perhaps based on role,
1646 # but the default should match what the vendor uses
1647 if @{ [info exists CHIPNAME] @} @{
1648 set _CHIPNAME $CHIPNAME
1650 set _CHIPNAME sam7x256
1653 # ONLY use ENDIAN with targets that can change it.
1654 if @{ [info exists ENDIAN] @} @{
1660 # TAP identifiers may change as chips mature, for example with
1661 # new revision fields (the "3" here). Pick a good default; you
1662 # can pass several such identifiers to the "jtag newtap" command.
1663 if @{ [info exists CPUTAPID ] @} @{
1664 set _CPUTAPID $CPUTAPID
1666 set _CPUTAPID 0x3f0f0f0f
1669 @c but 0x3f0f0f0f is for an str73x part ...
1671 @emph{Remember:} Board config files may include multiple target
1672 config files, or the same target file multiple times
1673 (changing at least @code{CHIPNAME}).
1675 Likewise, the target configuration file should define
1676 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1677 use it later on when defining debug targets:
1680 set _TARGETNAME $_CHIPNAME.cpu
1681 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1684 @subsection Adding TAPs to the Scan Chain
1685 After the ``defaults'' are set up,
1686 add the TAPs on each chip to the JTAG scan chain.
1687 @xref{TAP Declaration}, and the naming convention
1690 In the simplest case the chip has only one TAP,
1691 probably for a CPU or FPGA.
1692 The config file for the Atmel AT91SAM7X256
1693 looks (in part) like this:
1696 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1699 A board with two such at91sam7 chips would be able
1700 to source such a config file twice, with different
1701 values for @code{CHIPNAME}, so
1702 it adds a different TAP each time.
1704 If there are nonzero @option{-expected-id} values,
1705 OpenOCD attempts to verify the actual tap id against those values.
1706 It will issue error messages if there is mismatch, which
1707 can help to pinpoint problems in OpenOCD configurations.
1710 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1711 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1712 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1713 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1714 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1717 There are more complex examples too, with chips that have
1718 multiple TAPs. Ones worth looking at include:
1721 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1722 plus a JRC to enable them
1723 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1724 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1725 is not currently used)
1728 @subsection Add CPU targets
1730 After adding a TAP for a CPU, you should set it up so that
1731 GDB and other commands can use it.
1732 @xref{CPU Configuration}.
1733 For the at91sam7 example above, the command can look like this;
1734 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1735 to little endian, and this chip doesn't support changing that.
1738 set _TARGETNAME $_CHIPNAME.cpu
1739 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1742 Work areas are small RAM areas associated with CPU targets.
1743 They are used by OpenOCD to speed up downloads,
1744 and to download small snippets of code to program flash chips.
1745 If the chip includes a form of ``on-chip-ram'' - and many do - define
1746 a work area if you can.
1747 Again using the at91sam7 as an example, this can look like:
1750 $_TARGETNAME configure -work-area-phys 0x00200000 \
1751 -work-area-size 0x4000 -work-area-backup 0
1754 @anchor{definecputargetsworkinginsmp}
1755 @subsection Define CPU targets working in SMP
1757 After setting targets, you can define a list of targets working in SMP.
1760 set _TARGETNAME_1 $_CHIPNAME.cpu1
1761 set _TARGETNAME_2 $_CHIPNAME.cpu2
1762 target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap \
1763 -coreid 0 -dbgbase $_DAP_DBG1
1764 target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap \
1765 -coreid 1 -dbgbase $_DAP_DBG2
1766 #define 2 targets working in smp.
1767 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
1769 In the above example on cortex_a, 2 cpus are working in SMP.
1770 In SMP only one GDB instance is created and :
1772 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
1773 @item halt command triggers the halt of all targets in the list.
1774 @item resume command triggers the write context and the restart of all targets in the list.
1775 @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
1776 @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
1777 displayed by the GDB session @pxref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.
1780 The SMP behaviour can be disabled/enabled dynamically. On cortex_a following
1781 command have been implemented.
1783 @item cortex_a smp_on : enable SMP mode, behaviour is as described above.
1784 @item cortex_a smp_off : disable SMP mode, the current target is the one
1785 displayed in the GDB session, only this target is now controlled by GDB
1786 session. This behaviour is useful during system boot up.
1787 @item cortex_a smp_gdb : display/fix the core id displayed in GDB session see
1794 #0 : coreid 0 is displayed to GDB ,
1795 #-> -1 : next resume triggers a real resume
1796 > cortex_a smp_gdb 1
1798 #0 :coreid 0 is displayed to GDB ,
1799 #->1 : next resume displays coreid 1 to GDB
1803 #1 :coreid 1 is displayed to GDB ,
1804 #->1 : next resume displays coreid 1 to GDB
1805 > cortex_a smp_gdb -1
1807 #1 :coreid 1 is displayed to GDB,
1808 #->-1 : next resume triggers a real resume
1812 @subsection Chip Reset Setup
1814 As a rule, you should put the @command{reset_config} command
1815 into the board file. Most things you think you know about a
1816 chip can be tweaked by the board.
1818 Some chips have specific ways the TRST and SRST signals are
1819 managed. In the unusual case that these are @emph{chip specific}
1820 and can never be changed by board wiring, they could go here.
1821 For example, some chips can't support JTAG debugging without
1824 Provide a @code{reset-assert} event handler if you can.
1825 Such a handler uses JTAG operations to reset the target,
1826 letting this target config be used in systems which don't
1827 provide the optional SRST signal, or on systems where you
1828 don't want to reset all targets at once.
1829 Such a handler might write to chip registers to force a reset,
1830 use a JRC to do that (preferable -- the target may be wedged!),
1831 or force a watchdog timer to trigger.
1832 (For Cortex-M targets, this is not necessary. The target
1833 driver knows how to use trigger an NVIC reset when SRST is
1836 Some chips need special attention during reset handling if
1837 they're going to be used with JTAG.
1838 An example might be needing to send some commands right
1839 after the target's TAP has been reset, providing a
1840 @code{reset-deassert-post} event handler that writes a chip
1841 register to report that JTAG debugging is being done.
1842 Another would be reconfiguring the watchdog so that it stops
1843 counting while the core is halted in the debugger.
1845 JTAG clocking constraints often change during reset, and in
1846 some cases target config files (rather than board config files)
1847 are the right places to handle some of those issues.
1848 For example, immediately after reset most chips run using a
1849 slower clock than they will use later.
1850 That means that after reset (and potentially, as OpenOCD
1851 first starts up) they must use a slower JTAG clock rate
1852 than they will use later.
1853 @xref{jtagspeed,,JTAG Speed}.
1855 @quotation Important
1856 When you are debugging code that runs right after chip
1857 reset, getting these issues right is critical.
1858 In particular, if you see intermittent failures when
1859 OpenOCD verifies the scan chain after reset,
1860 look at how you are setting up JTAG clocking.
1863 @anchor{theinittargetsprocedure}
1864 @subsection The init_targets procedure
1865 @cindex init_targets procedure
1867 Target config files can either be ``linear'' (script executed line-by-line when parsed in
1868 configuration stage, @xref{configurationstage,,Configuration Stage},) or they can contain a special
1869 procedure called @code{init_targets}, which will be executed when entering run stage
1870 (after parsing all config files or after @code{init} command, @xref{enteringtherunstage,,Entering the Run Stage}.)
1871 Such procedure can be overriden by ``next level'' script (which sources the original).
1872 This concept faciliates code reuse when basic target config files provide generic configuration
1873 procedures and @code{init_targets} procedure, which can then be sourced and enchanced or changed in
1874 a ``more specific'' target config file. This is not possible with ``linear'' config scripts,
1875 because sourcing them executes every initialization commands they provide.
1878 ### generic_file.cfg ###
1880 proc setup_my_chip @{chip_name flash_size ram_size@} @{
1881 # basic initialization procedure ...
1884 proc init_targets @{@} @{
1885 # initializes generic chip with 4kB of flash and 1kB of RAM
1886 setup_my_chip MY_GENERIC_CHIP 4096 1024
1889 ### specific_file.cfg ###
1891 source [find target/generic_file.cfg]
1893 proc init_targets @{@} @{
1894 # initializes specific chip with 128kB of flash and 64kB of RAM
1895 setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
1899 The easiest way to convert ``linear'' config files to @code{init_targets} version is to
1900 enclose every line of ``code'' (i.e. not @code{source} commands, procedures, etc.) in this procedure.
1902 For an example of this scheme see LPC2000 target config files.
1904 The @code{init_boards} procedure is a similar concept concerning board config files
1905 (@xref{theinitboardprocedure,,The init_board procedure}.)
1907 @anchor{theinittargeteventsprocedure}
1908 @subsection The init_target_events procedure
1909 @cindex init_target_events procedure
1911 A special procedure called @code{init_target_events} is run just after
1912 @code{init_targets} (@xref{theinittargetsprocedure,,The init_targets
1913 procedure}.) and before @code{init_board}
1914 (@xref{theinitboardprocedure,,The init_board procedure}.) It is used
1915 to set up default target events for the targets that do not have those
1916 events already assigned.
1918 @subsection ARM Core Specific Hacks
1920 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1921 special high speed download features - enable it.
1923 If present, the MMU, the MPU and the CACHE should be disabled.
1925 Some ARM cores are equipped with trace support, which permits
1926 examination of the instruction and data bus activity. Trace
1927 activity is controlled through an ``Embedded Trace Module'' (ETM)
1928 on one of the core's scan chains. The ETM emits voluminous data
1929 through a ``trace port''. (@xref{armhardwaretracing,,ARM Hardware Tracing}.)
1930 If you are using an external trace port,
1931 configure it in your board config file.
1932 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
1933 configure it in your target config file.
1936 etm config $_TARGETNAME 16 normal full etb
1937 etb config $_TARGETNAME $_CHIPNAME.etb
1940 @subsection Internal Flash Configuration
1942 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1944 @b{Never ever} in the ``target configuration file'' define any type of
1945 flash that is external to the chip. (For example a BOOT flash on
1946 Chip Select 0.) Such flash information goes in a board file - not
1947 the TARGET (chip) file.
1951 @item at91sam7x256 - has 256K flash YES enable it.
1952 @item str912 - has flash internal YES enable it.
1953 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1954 @item pxa270 - again - CS0 flash - it goes in the board file.
1957 @anchor{translatingconfigurationfiles}
1958 @section Translating Configuration Files
1960 If you have a configuration file for another hardware debugger
1961 or toolset (Abatron, BDI2000, BDI3000, CCS,
1962 Lauterbach, SEGGER, Macraigor, etc.), translating
1963 it into OpenOCD syntax is often quite straightforward. The most tricky
1964 part of creating a configuration script is oftentimes the reset init
1965 sequence where e.g. PLLs, DRAM and the like is set up.
1967 One trick that you can use when translating is to write small
1968 Tcl procedures to translate the syntax into OpenOCD syntax. This
1969 can avoid manual translation errors and make it easier to
1970 convert other scripts later on.
1972 Example of transforming quirky arguments to a simple search and
1976 # Lauterbach syntax(?)
1978 # Data.Set c15:0x042f %long 0x40000015
1980 # OpenOCD syntax when using procedure below.
1982 # setc15 0x01 0x00050078
1984 proc setc15 @{regs value@} @{
1987 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
1989 arm mcr 15 [expr ($regs>>12)&0x7] \
1990 [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
1991 [expr ($regs>>8)&0x7] $value
1997 @node Daemon Configuration
1998 @chapter Daemon Configuration
1999 @cindex initialization
2000 The commands here are commonly found in the openocd.cfg file and are
2001 used to specify what TCP/IP ports are used, and how GDB should be
2004 @anchor{configurationstage}
2005 @section Configuration Stage
2006 @cindex configuration stage
2007 @cindex config command
2009 When the OpenOCD server process starts up, it enters a
2010 @emph{configuration stage} which is the only time that
2011 certain commands, @emph{configuration commands}, may be issued.
2012 Normally, configuration commands are only available
2013 inside startup scripts.
2015 In this manual, the definition of a configuration command is
2016 presented as a @emph{Config Command}, not as a @emph{Command}
2017 which may be issued interactively.
2018 The runtime @command{help} command also highlights configuration
2019 commands, and those which may be issued at any time.
2021 Those configuration commands include declaration of TAPs,
2023 the interface used for JTAG communication,
2024 and other basic setup.
2025 The server must leave the configuration stage before it
2026 may access or activate TAPs.
2027 After it leaves this stage, configuration commands may no
2030 @anchor{enteringtherunstage}
2031 @section Entering the Run Stage
2033 The first thing OpenOCD does after leaving the configuration
2034 stage is to verify that it can talk to the scan chain
2035 (list of TAPs) which has been configured.
2036 It will warn if it doesn't find TAPs it expects to find,
2037 or finds TAPs that aren't supposed to be there.
2038 You should see no errors at this point.
2039 If you see errors, resolve them by correcting the
2040 commands you used to configure the server.
2041 Common errors include using an initial JTAG speed that's too
2042 fast, and not providing the right IDCODE values for the TAPs
2045 Once OpenOCD has entered the run stage, a number of commands
2047 A number of these relate to the debug targets you may have declared.
2048 For example, the @command{mww} command will not be available until
2049 a target has been successfuly instantiated.
2050 If you want to use those commands, you may need to force
2051 entry to the run stage.
2053 @deffn {Config Command} init
2054 This command terminates the configuration stage and
2055 enters the run stage. This helps when you need to have
2056 the startup scripts manage tasks such as resetting the target,
2057 programming flash, etc. To reset the CPU upon startup, add "init" and
2058 "reset" at the end of the config script or at the end of the OpenOCD
2059 command line using the @option{-c} command line switch.
2061 If this command does not appear in any startup/configuration file
2062 OpenOCD executes the command for you after processing all
2063 configuration files and/or command line options.
2065 @b{NOTE:} This command normally occurs at or near the end of your
2066 openocd.cfg file to force OpenOCD to ``initialize'' and make the
2067 targets ready. For example: If your openocd.cfg file needs to
2068 read/write memory on your target, @command{init} must occur before
2069 the memory read/write commands. This includes @command{nand probe}.
2072 @deffn {Overridable Procedure} jtag_init
2073 This is invoked at server startup to verify that it can talk
2074 to the scan chain (list of TAPs) which has been configured.
2076 The default implementation first tries @command{jtag arp_init},
2077 which uses only a lightweight JTAG reset before examining the
2079 If that fails, it tries again, using a harder reset
2080 from the overridable procedure @command{init_reset}.
2082 Implementations must have verified the JTAG scan chain before
2084 This is done by calling @command{jtag arp_init}
2085 (or @command{jtag arp_init-reset}).
2089 @section TCP/IP Ports
2094 The OpenOCD server accepts remote commands in several syntaxes.
2095 Each syntax uses a different TCP/IP port, which you may specify
2096 only during configuration (before those ports are opened).
2098 For reasons including security, you may wish to prevent remote
2099 access using one or more of these ports.
2100 In such cases, just specify the relevant port number as zero.
2101 If you disable all access through TCP/IP, you will need to
2102 use the command line @option{-pipe} option.
2104 @deffn {Command} gdb_port [number]
2106 Normally gdb listens to a TCP/IP port, but GDB can also
2107 communicate via pipes(stdin/out or named pipes). The name
2108 "gdb_port" stuck because it covers probably more than 90% of
2109 the normal use cases.
2111 No arguments reports GDB port. "pipe" means listen to stdin
2112 output to stdout, an integer is base port number, "disable"
2113 disables the gdb server.
2115 When using "pipe", also use log_output to redirect the log
2116 output to a file so as not to flood the stdin/out pipes.
2118 The -p/--pipe option is deprecated and a warning is printed
2119 as it is equivalent to passing in -c "gdb_port pipe; log_output openocd.log".
2121 Any other string is interpreted as named pipe to listen to.
2122 Output pipe is the same name as input pipe, but with 'o' appended,
2123 e.g. /var/gdb, /var/gdbo.
2125 The GDB port for the first target will be the base port, the
2126 second target will listen on gdb_port + 1, and so on.
2127 When not specified during the configuration stage,
2128 the port @var{number} defaults to 3333.
2130 Note: when using "gdb_port pipe", increasing the default remote timeout in
2131 gdb (with 'set remotetimeout') is recommended. An insufficient timeout may
2132 cause initialization to fail with "Unknown remote qXfer reply: OK".
2136 @deffn {Command} tcl_port [number]
2137 Specify or query the port used for a simplified RPC
2138 connection that can be used by clients to issue TCL commands and get the
2139 output from the Tcl engine.
2140 Intended as a machine interface.
2141 When not specified during the configuration stage,
2142 the port @var{number} defaults to 6666.
2146 @deffn {Command} telnet_port [number]
2147 Specify or query the
2148 port on which to listen for incoming telnet connections.
2149 This port is intended for interaction with one human through TCL commands.
2150 When not specified during the configuration stage,
2151 the port @var{number} defaults to 4444.
2152 When specified as zero, this port is not activated.
2155 @anchor{gdbconfiguration}
2156 @section GDB Configuration
2158 @cindex GDB configuration
2159 You can reconfigure some GDB behaviors if needed.
2160 The ones listed here are static and global.
2161 @xref{targetconfiguration,,Target Configuration}, about configuring individual targets.
2162 @xref{targetevents,,Target Events}, about configuring target-specific event handling.
2164 @anchor{gdbbreakpointoverride}
2165 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
2166 Force breakpoint type for gdb @command{break} commands.
2167 This option supports GDB GUIs which don't
2168 distinguish hard versus soft breakpoints, if the default OpenOCD and
2169 GDB behaviour is not sufficient. GDB normally uses hardware
2170 breakpoints if the memory map has been set up for flash regions.
2173 @anchor{gdbflashprogram}
2174 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
2175 Set to @option{enable} to cause OpenOCD to program the flash memory when a
2176 vFlash packet is received.
2177 The default behaviour is @option{enable}.
2180 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
2181 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
2182 requested. GDB will then know when to set hardware breakpoints, and program flash
2183 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
2184 for flash programming to work.
2185 Default behaviour is @option{enable}.
2186 @xref{gdbflashprogram,,gdb_flash_program}.
2189 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
2190 Specifies whether data aborts cause an error to be reported
2191 by GDB memory read packets.
2192 The default behaviour is @option{disable};
2193 use @option{enable} see these errors reported.
2196 @deffn {Config Command} gdb_target_description (@option{enable}|@option{disable})
2197 Set to @option{enable} to cause OpenOCD to send the target descriptions to gdb via qXfer:features:read packet.
2198 The default behaviour is @option{enable}.
2201 @deffn {Command} gdb_save_tdesc
2202 Saves the target descripton file to the local file system.
2204 The file name is @i{target_name}.xml.
2207 @anchor{eventpolling}
2208 @section Event Polling
2210 Hardware debuggers are parts of asynchronous systems,
2211 where significant events can happen at any time.
2212 The OpenOCD server needs to detect some of these events,
2213 so it can report them to through TCL command line
2216 Examples of such events include:
2219 @item One of the targets can stop running ... maybe it triggers
2220 a code breakpoint or data watchpoint, or halts itself.
2221 @item Messages may be sent over ``debug message'' channels ... many
2222 targets support such messages sent over JTAG,
2223 for receipt by the person debugging or tools.
2224 @item Loss of power ... some adapters can detect these events.
2225 @item Resets not issued through JTAG ... such reset sources
2226 can include button presses or other system hardware, sometimes
2227 including the target itself (perhaps through a watchdog).
2228 @item Debug instrumentation sometimes supports event triggering
2229 such as ``trace buffer full'' (so it can quickly be emptied)
2230 or other signals (to correlate with code behavior).
2233 None of those events are signaled through standard JTAG signals.
2234 However, most conventions for JTAG connectors include voltage
2235 level and system reset (SRST) signal detection.
2236 Some connectors also include instrumentation signals, which
2237 can imply events when those signals are inputs.
2239 In general, OpenOCD needs to periodically check for those events,
2240 either by looking at the status of signals on the JTAG connector
2241 or by sending synchronous ``tell me your status'' JTAG requests
2242 to the various active targets.
2243 There is a command to manage and monitor that polling,
2244 which is normally done in the background.
2246 @deffn Command poll [@option{on}|@option{off}]
2247 Poll the current target for its current state.
2248 (Also, @pxref{targetcurstate,,target curstate}.)
2249 If that target is in debug mode, architecture
2250 specific information about the current state is printed.
2251 An optional parameter
2252 allows background polling to be enabled and disabled.
2254 You could use this from the TCL command shell, or
2255 from GDB using @command{monitor poll} command.
2256 Leave background polling enabled while you're using GDB.
2259 background polling: on
2260 target state: halted
2261 target halted in ARM state due to debug-request, \
2262 current mode: Supervisor
2263 cpsr: 0x800000d3 pc: 0x11081bfc
2264 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2269 @node Debug Adapter Configuration
2270 @chapter Debug Adapter Configuration
2271 @cindex config file, interface
2272 @cindex interface config file
2274 Correctly installing OpenOCD includes making your operating system give
2275 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2276 are used to select which one is used, and to configure how it is used.
2279 Because OpenOCD started out with a focus purely on JTAG, you may find
2280 places where it wrongly presumes JTAG is the only transport protocol
2281 in use. Be aware that recent versions of OpenOCD are removing that
2282 limitation. JTAG remains more functional than most other transports.
2283 Other transports do not support boundary scan operations, or may be
2284 specific to a given chip vendor. Some might be usable only for
2285 programming flash memory, instead of also for debugging.
2288 Debug Adapters/Interfaces/Dongles are normally configured
2289 through commands in an interface configuration
2290 file which is sourced by your @file{openocd.cfg} file, or
2291 through a command line @option{-f interface/....cfg} option.
2294 source [find interface/olimex-jtag-tiny.cfg]
2298 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2299 A few cases are so simple that you only need to say what driver to use:
2306 Most adapters need a bit more configuration than that.
2309 @section Interface Configuration
2311 The interface command tells OpenOCD what type of debug adapter you are
2312 using. Depending on the type of adapter, you may need to use one or
2313 more additional commands to further identify or configure the adapter.
2315 @deffn {Config Command} {interface} name
2316 Use the interface driver @var{name} to connect to the
2320 @deffn Command {interface_list}
2321 List the debug adapter drivers that have been built into
2322 the running copy of OpenOCD.
2324 @deffn Command {interface transports} transport_name+
2325 Specifies the transports supported by this debug adapter.
2326 The adapter driver builds-in similar knowledge; use this only
2327 when external configuration (such as jumpering) changes what
2328 the hardware can support.
2333 @deffn Command {adapter_name}
2334 Returns the name of the debug adapter driver being used.
2337 @section Interface Drivers
2339 Each of the interface drivers listed here must be explicitly
2340 enabled when OpenOCD is configured, in order to be made
2341 available at run time.
2343 @deffn {Interface Driver} {amt_jtagaccel}
2344 Amontec Chameleon in its JTAG Accelerator configuration,
2345 connected to a PC's EPP mode parallel port.
2346 This defines some driver-specific commands:
2348 @deffn {Config Command} {parport_port} number
2349 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2350 the number of the @file{/dev/parport} device.
2353 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
2354 Displays status of RTCK option.
2355 Optionally sets that option first.
2359 @deffn {Interface Driver} {arm-jtag-ew}
2360 Olimex ARM-JTAG-EW USB adapter
2361 This has one driver-specific command:
2363 @deffn Command {armjtagew_info}
2368 @deffn {Interface Driver} {at91rm9200}
2369 Supports bitbanged JTAG from the local system,
2370 presuming that system is an Atmel AT91rm9200
2371 and a specific set of GPIOs is used.
2372 @c command: at91rm9200_device NAME
2373 @c chooses among list of bit configs ... only one option
2376 @deffn {Interface Driver} {cmsis-dap}
2377 ARM CMSIS-DAP compliant based adapter.
2379 @deffn {Config Command} {cmsis_dap_vid_pid} [vid pid]+
2380 The vendor ID and product ID of the CMSIS-DAP device. If not specified
2381 the driver will attempt to auto detect the CMSIS-DAP device.
2382 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2384 cmsis_dap_vid_pid 0xc251 0xf001 0x0d28 0x0204
2388 @deffn {Config Command} {cmsis_dap_serial} [serial]
2389 Specifies the @var{serial} of the CMSIS-DAP device to use.
2390 If not specified, serial numbers are not considered.
2393 @deffn {Command} {cmsis-dap info}
2394 Display various device information, like hardware version, firmware version, current bus status.
2398 @deffn {Interface Driver} {dummy}
2399 A dummy software-only driver for debugging.
2402 @deffn {Interface Driver} {ep93xx}
2403 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2406 @deffn {Interface Driver} {ft2232}
2407 FTDI FT2232 (USB) based devices over one of the userspace libraries.
2409 Note that this driver has several flaws and the @command{ftdi} driver is
2410 recommended as its replacement.
2412 These interfaces have several commands, used to configure the driver
2413 before initializing the JTAG scan chain:
2415 @deffn {Config Command} {ft2232_device_desc} description
2416 Provides the USB device description (the @emph{iProduct string})
2417 of the FTDI FT2232 device. If not
2418 specified, the FTDI default value is used. This setting is only valid
2419 if compiled with FTD2XX support.
2422 @deffn {Config Command} {ft2232_serial} serial-number
2423 Specifies the @var{serial-number} of the FTDI FT2232 device to use,
2424 in case the vendor provides unique IDs and more than one FT2232 device
2425 is connected to the host.
2426 If not specified, serial numbers are not considered.
2427 (Note that USB serial numbers can be arbitrary Unicode strings,
2428 and are not restricted to containing only decimal digits.)
2431 @deffn {Config Command} {ft2232_layout} name
2432 Each vendor's FT2232 device can use different GPIO signals
2433 to control output-enables, reset signals, and LEDs.
2434 Currently valid layout @var{name} values include:
2436 @item @b{axm0432_jtag} Axiom AXM-0432
2437 @item @b{comstick} Hitex STR9 comstick
2438 @item @b{cortino} Hitex Cortino JTAG interface
2439 @item @b{evb_lm3s811} TI/Luminary Micro EVB_LM3S811 as a JTAG interface,
2440 either for the local Cortex-M3 (SRST only)
2441 or in a passthrough mode (neither SRST nor TRST)
2442 This layout can not support the SWO trace mechanism, and should be
2443 used only for older boards (before rev C).
2444 @item @b{luminary_icdi} This layout should be used with most TI/Luminary
2445 eval boards, including Rev C LM3S811 eval boards and the eponymous
2446 ICDI boards, to debug either the local Cortex-M3 or in passthrough mode
2447 to debug some other target. It can support the SWO trace mechanism.
2448 @item @b{flyswatter} Tin Can Tools Flyswatter
2449 @item @b{icebear} ICEbear JTAG adapter from Section 5
2450 @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
2451 @item @b{jtagkey2} Amontec JTAGkey2 (and compatibles)
2452 @item @b{m5960} American Microsystems M5960
2453 @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
2454 @item @b{oocdlink} OOCDLink
2455 @c oocdlink ~= jtagkey_prototype_v1
2456 @item @b{redbee-econotag} Integrated with a Redbee development board.
2457 @item @b{redbee-usb} Integrated with a Redbee USB-stick development board.
2458 @item @b{sheevaplug} Marvell Sheevaplug development kit
2459 @item @b{signalyzer} Xverve Signalyzer
2460 @item @b{stm32stick} Hitex STM32 Performance Stick
2461 @item @b{turtelizer2} egnite Software turtelizer2
2462 @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
2466 @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
2467 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
2468 default values are used.
2469 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2471 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2475 @deffn {Config Command} {ft2232_latency} ms
2476 On some systems using FT2232 based JTAG interfaces the FT_Read function call in
2477 ft2232_read() fails to return the expected number of bytes. This can be caused by
2478 USB communication delays and has proved hard to reproduce and debug. Setting the
2479 FT2232 latency timer to a larger value increases delays for short USB packets but it
2480 also reduces the risk of timeouts before receiving the expected number of bytes.
2481 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
2484 @deffn {Config Command} {ft2232_channel} channel
2485 Used to select the channel of the ft2232 chip to use (between 1 and 4).
2486 The default value is 1.
2489 For example, the interface config file for a
2490 Turtelizer JTAG Adapter looks something like this:
2494 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
2495 ft2232_layout turtelizer2
2496 ft2232_vid_pid 0x0403 0xbdc8
2500 @deffn {Interface Driver} {ftdi}
2501 This driver is for adapters using the MPSSE (Multi-Protocol Synchronous Serial
2502 Engine) mode built into many FTDI chips, such as the FT2232, FT4232 and FT232H.
2503 It is a complete rewrite to address a large number of problems with the ft2232
2506 The driver is using libusb-1.0 in asynchronous mode to talk to the FTDI device,
2507 bypassing intermediate libraries like libftdi of D2XX. Performance-wise it is
2508 consistently faster than the ft2232 driver, sometimes several times faster.
2510 A major improvement of this driver is that support for new FTDI based adapters
2511 can be added competely through configuration files, without the need to patch
2512 and rebuild OpenOCD.
2514 The driver uses a signal abstraction to enable Tcl configuration files to
2515 define outputs for one or several FTDI GPIO. These outputs can then be
2516 controlled using the @command{ftdi_set_signal} command. Special signal names
2517 are reserved for nTRST, nSRST and LED (for blink) so that they, if defined,
2518 will be used for their customary purpose.
2520 Depending on the type of buffer attached to the FTDI GPIO, the outputs have to
2521 be controlled differently. In order to support tristateable signals such as
2522 nSRST, both a data GPIO and an output-enable GPIO can be specified for each
2523 signal. The following output buffer configurations are supported:
2526 @item Push-pull with one FTDI output as (non-)inverted data line
2527 @item Open drain with one FTDI output as (non-)inverted output-enable
2528 @item Tristate with one FTDI output as (non-)inverted data line and another
2529 FTDI output as (non-)inverted output-enable
2530 @item Unbuffered, using the FTDI GPIO as a tristate output directly by
2531 switching data and direction as necessary
2534 These interfaces have several commands, used to configure the driver
2535 before initializing the JTAG scan chain:
2537 @deffn {Config Command} {ftdi_vid_pid} [vid pid]+
2538 The vendor ID and product ID of the adapter. If not specified, the FTDI
2539 default values are used.
2540 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2542 ftdi_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2546 @deffn {Config Command} {ftdi_device_desc} description
2547 Provides the USB device description (the @emph{iProduct string})
2548 of the adapter. If not specified, the device description is ignored
2549 during device selection.
2552 @deffn {Config Command} {ftdi_serial} serial-number
2553 Specifies the @var{serial-number} of the adapter to use,
2554 in case the vendor provides unique IDs and more than one adapter
2555 is connected to the host.
2556 If not specified, serial numbers are not considered.
2557 (Note that USB serial numbers can be arbitrary Unicode strings,
2558 and are not restricted to containing only decimal digits.)
2561 @deffn {Config Command} {ftdi_location} <bus>:<port>[,<port>]...
2562 Specifies the physical USB port of the adapter to use. The path
2563 roots at @var{bus} and walks down the physical ports, with each
2564 @var{port} option specifying a deeper level in the bus topology, the last
2565 @var{port} denoting where the target adapter is actually plugged.
2566 The USB bus topology can be queried with the command @emph{lsusb -t}.
2568 This command is only available if your libusb1 is at least version 1.0.16.
2571 @deffn {Config Command} {ftdi_channel} channel
2572 Selects the channel of the FTDI device to use for MPSSE operations. Most
2573 adapters use the default, channel 0, but there are exceptions.
2576 @deffn {Config Command} {ftdi_layout_init} data direction
2577 Specifies the initial values of the FTDI GPIO data and direction registers.
2578 Each value is a 16-bit number corresponding to the concatenation of the high
2579 and low FTDI GPIO registers. The values should be selected based on the
2580 schematics of the adapter, such that all signals are set to safe levels with
2581 minimal impact on the target system. Avoid floating inputs, conflicting outputs
2582 and initially asserted reset signals.
2585 @deffn {Config Command} {ftdi_layout_signal} name [@option{-data}|@option{-ndata} data_mask] [@option{-oe}|@option{-noe} oe_mask] [@option{-alias}|@option{-nalias} name]
2586 Creates a signal with the specified @var{name}, controlled by one or more FTDI
2587 GPIO pins via a range of possible buffer connections. The masks are FTDI GPIO
2588 register bitmasks to tell the driver the connection and type of the output
2589 buffer driving the respective signal. @var{data_mask} is the bitmask for the
2590 pin(s) connected to the data input of the output buffer. @option{-ndata} is
2591 used with inverting data inputs and @option{-data} with non-inverting inputs.
2592 The @option{-oe} (or @option{-noe}) option tells where the output-enable (or
2593 not-output-enable) input to the output buffer is connected.
2595 Both @var{data_mask} and @var{oe_mask} need not be specified. For example, a
2596 simple open-collector transistor driver would be specified with @option{-oe}
2597 only. In that case the signal can only be set to drive low or to Hi-Z and the
2598 driver will complain if the signal is set to drive high. Which means that if
2599 it's a reset signal, @command{reset_config} must be specified as
2600 @option{srst_open_drain}, not @option{srst_push_pull}.
2602 A special case is provided when @option{-data} and @option{-oe} is set to the
2603 same bitmask. Then the FTDI pin is considered being connected straight to the
2604 target without any buffer. The FTDI pin is then switched between output and
2605 input as necessary to provide the full set of low, high and Hi-Z
2606 characteristics. In all other cases, the pins specified in a signal definition
2607 are always driven by the FTDI.
2609 If @option{-alias} or @option{-nalias} is used, the signal is created
2610 identical (or with data inverted) to an already specified signal
2614 @deffn {Command} {ftdi_set_signal} name @option{0}|@option{1}|@option{z}
2615 Set a previously defined signal to the specified level.
2617 @item @option{0}, drive low
2618 @item @option{1}, drive high
2619 @item @option{z}, set to high-impedance
2623 @deffn {Command} {ftdi_tdo_sample_edge} @option{rising}|@option{falling}
2624 Configure TCK edge at which the adapter samples the value of the TDO signal
2626 Due to signal propagation delays, sampling TDO on rising TCK can become quite
2627 peculiar at high JTAG clock speeds. However, FTDI chips offer a possiblity to sample
2628 TDO on falling edge of TCK. With some board/adapter configurations, this may increase
2629 stability at higher JTAG clocks.
2631 @item @option{rising}, sample TDO on rising edge of TCK - this is the default
2632 @item @option{falling}, sample TDO on falling edge of TCK
2636 For example adapter definitions, see the configuration files shipped in the
2637 @file{interface/ftdi} directory.
2641 @deffn {Interface Driver} {remote_bitbang}
2642 Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
2643 with a remote process and sends ASCII encoded bitbang requests to that process
2644 instead of directly driving JTAG.
2646 The remote_bitbang driver is useful for debugging software running on
2647 processors which are being simulated.
2649 @deffn {Config Command} {remote_bitbang_port} number
2650 Specifies the TCP port of the remote process to connect to or 0 to use UNIX
2651 sockets instead of TCP.
2654 @deffn {Config Command} {remote_bitbang_host} hostname
2655 Specifies the hostname of the remote process to connect to using TCP, or the
2656 name of the UNIX socket to use if remote_bitbang_port is 0.
2659 For example, to connect remotely via TCP to the host foobar you might have
2663 interface remote_bitbang
2664 remote_bitbang_port 3335
2665 remote_bitbang_host foobar
2668 To connect to another process running locally via UNIX sockets with socket
2672 interface remote_bitbang
2673 remote_bitbang_port 0
2674 remote_bitbang_host mysocket
2678 @deffn {Interface Driver} {usb_blaster}
2679 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2680 for FTDI chips. These interfaces have several commands, used to
2681 configure the driver before initializing the JTAG scan chain:
2683 @deffn {Config Command} {usb_blaster_device_desc} description
2684 Provides the USB device description (the @emph{iProduct string})
2685 of the FTDI FT245 device. If not
2686 specified, the FTDI default value is used. This setting is only valid
2687 if compiled with FTD2XX support.
2690 @deffn {Config Command} {usb_blaster_vid_pid} vid pid
2691 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2692 default values are used.
2693 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2694 Altera USB-Blaster (default):
2696 usb_blaster_vid_pid 0x09FB 0x6001
2698 The following VID/PID is for Kolja Waschk's USB JTAG:
2700 usb_blaster_vid_pid 0x16C0 0x06AD
2704 @deffn {Command} {usb_blaster_pin} (@option{pin6}|@option{pin8}) (@option{0}|@option{1}|@option{s}|@option{t})
2705 Sets the state or function of the unused GPIO pins on USB-Blasters
2706 (pins 6 and 8 on the female JTAG header). These pins can be used as
2707 SRST and/or TRST provided the appropriate connections are made on the
2710 For example, to use pin 6 as SRST:
2712 usb_blaster_pin pin6 s
2713 reset_config srst_only
2717 @deffn {Command} {usb_blaster_lowlevel_driver} (@option{ftdi}|@option{ftd2xx}|@option{ublast2})
2718 Chooses the low level access method for the adapter. If not specified,
2719 @option{ftdi} is selected unless it wasn't enabled during the
2720 configure stage. USB-Blaster II needs @option{ublast2}.
2723 @deffn {Command} {usb_blaster_firmware} @var{path}
2724 This command specifies @var{path} to access USB-Blaster II firmware
2725 image. To be used with USB-Blaster II only.
2730 @deffn {Interface Driver} {gw16012}
2731 Gateworks GW16012 JTAG programmer.
2732 This has one driver-specific command:
2734 @deffn {Config Command} {parport_port} [port_number]
2735 Display either the address of the I/O port
2736 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2737 If a parameter is provided, first switch to use that port.
2738 This is a write-once setting.
2742 @deffn {Interface Driver} {jlink}
2743 SEGGER J-Link family of USB adapters. It currently supports JTAG and SWD
2746 @quotation Compatibility Note
2747 SEGGER released many firmware versions for the many harware versions they
2748 produced. OpenOCD was extensively tested and intended to run on all of them,
2749 but some combinations were reported as incompatible. As a general
2750 recommendation, it is advisable to use the latest firmware version
2751 available for each hardware version. However the current V8 is a moving
2752 target, and SEGGER firmware versions released after the OpenOCD was
2753 released may not be compatible. In such cases it is recommended to
2754 revert to the last known functional version. For 0.5.0, this is from
2755 "Feb 8 2012 14:30:39", packed with 4.42c. For 0.6.0, the last known
2756 version is from "May 3 2012 18:36:22", packed with 4.46f.
2759 @deffn {Command} {jlink hwstatus}
2760 Display various hardware related information, for example target voltage and pin
2763 @deffn {Command} {jlink freemem}
2764 Display free device internal memory.
2766 @deffn {Command} {jlink jtag} [@option{2}|@option{3}]
2767 Set the JTAG command version to be used. Without argument, show the actual JTAG
2770 @deffn {Command} {jlink config}
2771 Display the device configuration.
2773 @deffn {Command} {jlink config targetpower} [@option{on}|@option{off}]
2774 Set the target power state on JTAG-pin 19. Without argument, show the target
2777 @deffn {Command} {jlink config mac} [@option{ff:ff:ff:ff:ff:ff}]
2778 Set the MAC address of the device. Without argument, show the MAC address.
2780 @deffn {Command} {jlink config ip} [@option{A.B.C.D}(@option{/E}|@option{F.G.H.I})]
2781 Set the IP configuration of the device, where A.B.C.D is the IP address, E the
2782 bit of the subnet mask and F.G.H.I the subnet mask. Without arguments, show the
2785 @deffn {Command} {jlink config usb} [@option{0} to @option{3}]
2786 Set the USB address of the device. This will also change the USB Product ID
2787 (PID) of the device. Without argument, show the USB address.
2789 @deffn {Command} {jlink config reset}
2790 Reset the current configuration.
2792 @deffn {Command} {jlink config write}
2793 Write the current configuration to the internal persistent storage.
2795 @deffn {Config} {jlink usb} <@option{0} to @option{3}>
2796 Set the USB address of the interface, in case more than one adapter is connected
2797 to the host. If not specified, USB addresses are not considered. Device
2798 selection via USB address is deprecated and the serial number should be used
2801 As a configuration command, it can be used only before 'init'.
2803 @deffn {Config} {jlink serial} <serial number>
2804 Set the serial number of the interface, in case more than one adapter is
2805 connected to the host. If not specified, serial numbers are not considered.
2807 As a configuration command, it can be used only before 'init'.
2811 @deffn {Interface Driver} {parport}
2812 Supports PC parallel port bit-banging cables:
2813 Wigglers, PLD download cable, and more.
2814 These interfaces have several commands, used to configure the driver
2815 before initializing the JTAG scan chain:
2817 @deffn {Config Command} {parport_cable} name
2818 Set the layout of the parallel port cable used to connect to the target.
2819 This is a write-once setting.
2820 Currently valid cable @var{name} values include:
2823 @item @b{altium} Altium Universal JTAG cable.
2824 @item @b{arm-jtag} Same as original wiggler except SRST and
2825 TRST connections reversed and TRST is also inverted.
2826 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
2827 in configuration mode. This is only used to
2828 program the Chameleon itself, not a connected target.
2829 @item @b{dlc5} The Xilinx Parallel cable III.
2830 @item @b{flashlink} The ST Parallel cable.
2831 @item @b{lattice} Lattice ispDOWNLOAD Cable
2832 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
2834 Amontec's Chameleon Programmer. The new version available from
2835 the website uses the original Wiggler layout ('@var{wiggler}')
2836 @item @b{triton} The parallel port adapter found on the
2837 ``Karo Triton 1 Development Board''.
2838 This is also the layout used by the HollyGates design
2839 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
2840 @item @b{wiggler} The original Wiggler layout, also supported by
2841 several clones, such as the Olimex ARM-JTAG
2842 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
2843 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
2847 @deffn {Config Command} {parport_port} [port_number]
2848 Display either the address of the I/O port
2849 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2850 If a parameter is provided, first switch to use that port.
2851 This is a write-once setting.
2853 When using PPDEV to access the parallel port, use the number of the parallel port:
2854 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
2855 you may encounter a problem.
2858 @deffn Command {parport_toggling_time} [nanoseconds]
2859 Displays how many nanoseconds the hardware needs to toggle TCK;
2860 the parport driver uses this value to obey the
2861 @command{adapter_khz} configuration.
2862 When the optional @var{nanoseconds} parameter is given,
2863 that setting is changed before displaying the current value.
2865 The default setting should work reasonably well on commodity PC hardware.
2866 However, you may want to calibrate for your specific hardware.
2868 To measure the toggling time with a logic analyzer or a digital storage
2869 oscilloscope, follow the procedure below:
2871 > parport_toggling_time 1000
2874 This sets the maximum JTAG clock speed of the hardware, but
2875 the actual speed probably deviates from the requested 500 kHz.
2876 Now, measure the time between the two closest spaced TCK transitions.
2877 You can use @command{runtest 1000} or something similar to generate a
2878 large set of samples.
2879 Update the setting to match your measurement:
2881 > parport_toggling_time <measured nanoseconds>
2883 Now the clock speed will be a better match for @command{adapter_khz rate}
2884 commands given in OpenOCD scripts and event handlers.
2886 You can do something similar with many digital multimeters, but note
2887 that you'll probably need to run the clock continuously for several
2888 seconds before it decides what clock rate to show. Adjust the
2889 toggling time up or down until the measured clock rate is a good
2890 match for the adapter_khz rate you specified; be conservative.
2894 @deffn {Config Command} {parport_write_on_exit} (@option{on}|@option{off})
2895 This will configure the parallel driver to write a known
2896 cable-specific value to the parallel interface on exiting OpenOCD.
2899 For example, the interface configuration file for a
2900 classic ``Wiggler'' cable on LPT2 might look something like this:
2905 parport_cable wiggler
2909 @deffn {Interface Driver} {presto}
2910 ASIX PRESTO USB JTAG programmer.
2911 @deffn {Config Command} {presto_serial} serial_string
2912 Configures the USB serial number of the Presto device to use.
2916 @deffn {Interface Driver} {rlink}
2917 Raisonance RLink USB adapter
2920 @deffn {Interface Driver} {usbprog}
2921 usbprog is a freely programmable USB adapter.
2924 @deffn {Interface Driver} {vsllink}
2925 vsllink is part of Versaloon which is a versatile USB programmer.
2928 This defines quite a few driver-specific commands,
2929 which are not currently documented here.
2933 @anchor{hla_interface}
2934 @deffn {Interface Driver} {hla}
2935 This is a driver that supports multiple High Level Adapters.
2936 This type of adapter does not expose some of the lower level api's
2937 that OpenOCD would normally use to access the target.
2939 Currently supported adapters include the ST STLINK and TI ICDI.
2940 STLINK firmware version >= V2.J21.S4 recommended due to issues with earlier
2941 versions of firmware where serial number is reset after first use. Suggest
2942 using ST firmware update utility to upgrade STLINK firmware even if current
2943 version reported is V2.J21.S4.
2945 @deffn {Config Command} {hla_device_desc} description
2946 Currently Not Supported.
2949 @deffn {Config Command} {hla_serial} serial
2950 Specifies the serial number of the adapter.
2953 @deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi})
2954 Specifies the adapter layout to use.
2957 @deffn {Config Command} {hla_vid_pid} vid pid
2958 The vendor ID and product ID of the device.
2961 @deffn {Command} {hla_command} command
2962 Execute a custom adapter-specific command. The @var{command} string is
2963 passed as is to the underlying adapter layout handler.
2967 @deffn {Interface Driver} {opendous}
2968 opendous-jtag is a freely programmable USB adapter.
2971 @deffn {Interface Driver} {ulink}
2972 This is the Keil ULINK v1 JTAG debugger.
2975 @deffn {Interface Driver} {ZY1000}
2976 This is the Zylin ZY1000 JTAG debugger.
2980 This defines some driver-specific commands,
2981 which are not currently documented here.
2984 @deffn Command power [@option{on}|@option{off}]
2985 Turn power switch to target on/off.
2986 No arguments: print status.
2989 @deffn {Interface Driver} {bcm2835gpio}
2990 This SoC is present in Raspberry Pi which is a cheap single-board computer
2991 exposing some GPIOs on its expansion header.
2993 The driver accesses memory-mapped GPIO peripheral registers directly
2994 for maximum performance, but the only possible race condition is for
2995 the pins' modes/muxing (which is highly unlikely), so it should be
2996 able to coexist nicely with both sysfs bitbanging and various
2997 peripherals' kernel drivers. The driver restores the previous
2998 configuration on exit.
3000 See @file{interface/raspberrypi-native.cfg} for a sample config and
3005 @section Transport Configuration
3007 As noted earlier, depending on the version of OpenOCD you use,
3008 and the debug adapter you are using,
3009 several transports may be available to
3010 communicate with debug targets (or perhaps to program flash memory).
3011 @deffn Command {transport list}
3012 displays the names of the transports supported by this
3016 @deffn Command {transport select} @option{transport_name}
3017 Select which of the supported transports to use in this OpenOCD session.
3019 When invoked with @option{transport_name}, attempts to select the named
3020 transport. The transport must be supported by the debug adapter
3021 hardware and by the version of OpenOCD you are using (including the
3024 If no transport has been selected and no @option{transport_name} is
3025 provided, @command{transport select} auto-selects the first transport
3026 supported by the debug adapter.
3028 @command{transport select} always returns the name of the session's selected
3032 @subsection JTAG Transport
3034 JTAG is the original transport supported by OpenOCD, and most
3035 of the OpenOCD commands support it.
3036 JTAG transports expose a chain of one or more Test Access Points (TAPs),
3037 each of which must be explicitly declared.
3038 JTAG supports both debugging and boundary scan testing.
3039 Flash programming support is built on top of debug support.
3041 JTAG transport is selected with the command @command{transport select
3042 jtag}. Unless your adapter uses @ref{hla_interface,the hla interface
3043 driver}, in which case the command is @command{transport select
3046 @subsection SWD Transport
3048 @cindex Serial Wire Debug
3049 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
3050 Debug Access Point (DAP, which must be explicitly declared.
3051 (SWD uses fewer signal wires than JTAG.)
3052 SWD is debug-oriented, and does not support boundary scan testing.
3053 Flash programming support is built on top of debug support.
3054 (Some processors support both JTAG and SWD.)
3056 SWD transport is selected with the command @command{transport select
3057 swd}. Unless your adapter uses @ref{hla_interface,the hla interface
3058 driver}, in which case the command is @command{transport select
3061 @deffn Command {swd newdap} ...
3062 Declares a single DAP which uses SWD transport.
3063 Parameters are currently the same as "jtag newtap" but this is
3066 @deffn Command {swd wcr trn prescale}
3067 Updates TRN (turnaraound delay) and prescaling.fields of the
3068 Wire Control Register (WCR).
3069 No parameters: displays current settings.
3072 @subsection SPI Transport
3074 @cindex Serial Peripheral Interface
3075 The Serial Peripheral Interface (SPI) is a general purpose transport
3076 which uses four wire signaling. Some processors use it as part of a
3077 solution for flash programming.
3081 JTAG clock setup is part of system setup.
3082 It @emph{does not belong with interface setup} since any interface
3083 only knows a few of the constraints for the JTAG clock speed.
3084 Sometimes the JTAG speed is
3085 changed during the target initialization process: (1) slow at
3086 reset, (2) program the CPU clocks, (3) run fast.
3087 Both the "slow" and "fast" clock rates are functions of the
3088 oscillators used, the chip, the board design, and sometimes
3089 power management software that may be active.
3091 The speed used during reset, and the scan chain verification which
3092 follows reset, can be adjusted using a @code{reset-start}
3093 target event handler.
3094 It can then be reconfigured to a faster speed by a
3095 @code{reset-init} target event handler after it reprograms those
3096 CPU clocks, or manually (if something else, such as a boot loader,
3097 sets up those clocks).
3098 @xref{targetevents,,Target Events}.
3099 When the initial low JTAG speed is a chip characteristic, perhaps
3100 because of a required oscillator speed, provide such a handler
3101 in the target config file.
3102 When that speed is a function of a board-specific characteristic
3103 such as which speed oscillator is used, it belongs in the board
3104 config file instead.
3105 In both cases it's safest to also set the initial JTAG clock rate
3106 to that same slow speed, so that OpenOCD never starts up using a
3107 clock speed that's faster than the scan chain can support.
3111 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
3114 If your system supports adaptive clocking (RTCK), configuring
3115 JTAG to use that is probably the most robust approach.
3116 However, it introduces delays to synchronize clocks; so it
3117 may not be the fastest solution.
3119 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
3120 instead of @command{adapter_khz}, but only for (ARM) cores and boards
3121 which support adaptive clocking.
3123 @deffn {Command} adapter_khz max_speed_kHz
3124 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
3125 JTAG interfaces usually support a limited number of
3126 speeds. The speed actually used won't be faster
3127 than the speed specified.
3129 Chip data sheets generally include a top JTAG clock rate.
3130 The actual rate is often a function of a CPU core clock,
3131 and is normally less than that peak rate.
3132 For example, most ARM cores accept at most one sixth of the CPU clock.
3134 Speed 0 (khz) selects RTCK method.
3135 @xref{faqrtck,,FAQ RTCK}.
3136 If your system uses RTCK, you won't need to change the
3137 JTAG clocking after setup.
3138 Not all interfaces, boards, or targets support ``rtck''.
3139 If the interface device can not
3140 support it, an error is returned when you try to use RTCK.
3143 @defun jtag_rclk fallback_speed_kHz
3144 @cindex adaptive clocking
3146 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
3147 If that fails (maybe the interface, board, or target doesn't
3148 support it), falls back to the specified frequency.
3150 # Fall back to 3mhz if RTCK is not supported
3155 @node Reset Configuration
3156 @chapter Reset Configuration
3157 @cindex Reset Configuration
3159 Every system configuration may require a different reset
3160 configuration. This can also be quite confusing.
3161 Resets also interact with @var{reset-init} event handlers,
3162 which do things like setting up clocks and DRAM, and
3163 JTAG clock rates. (@xref{jtagspeed,,JTAG Speed}.)
3164 They can also interact with JTAG routers.
3165 Please see the various board files for examples.
3168 To maintainers and integrators:
3169 Reset configuration touches several things at once.
3170 Normally the board configuration file
3171 should define it and assume that the JTAG adapter supports
3172 everything that's wired up to the board's JTAG connector.
3174 However, the target configuration file could also make note
3175 of something the silicon vendor has done inside the chip,
3176 which will be true for most (or all) boards using that chip.
3177 And when the JTAG adapter doesn't support everything, the
3178 user configuration file will need to override parts of
3179 the reset configuration provided by other files.
3182 @section Types of Reset
3184 There are many kinds of reset possible through JTAG, but
3185 they may not all work with a given board and adapter.
3186 That's part of why reset configuration can be error prone.
3190 @emph{System Reset} ... the @emph{SRST} hardware signal
3191 resets all chips connected to the JTAG adapter, such as processors,
3192 power management chips, and I/O controllers. Normally resets triggered
3193 with this signal behave exactly like pressing a RESET button.
3195 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
3196 just the TAP controllers connected to the JTAG adapter.
3197 Such resets should not be visible to the rest of the system; resetting a
3198 device's TAP controller just puts that controller into a known state.
3200 @emph{Emulation Reset} ... many devices can be reset through JTAG
3201 commands. These resets are often distinguishable from system
3202 resets, either explicitly (a "reset reason" register says so)
3203 or implicitly (not all parts of the chip get reset).
3205 @emph{Other Resets} ... system-on-chip devices often support
3206 several other types of reset.
3207 You may need to arrange that a watchdog timer stops
3208 while debugging, preventing a watchdog reset.
3209 There may be individual module resets.
3212 In the best case, OpenOCD can hold SRST, then reset
3213 the TAPs via TRST and send commands through JTAG to halt the
3214 CPU at the reset vector before the 1st instruction is executed.
3215 Then when it finally releases the SRST signal, the system is
3216 halted under debugger control before any code has executed.
3217 This is the behavior required to support the @command{reset halt}
3218 and @command{reset init} commands; after @command{reset init} a
3219 board-specific script might do things like setting up DRAM.
3220 (@xref{resetcommand,,Reset Command}.)
3222 @anchor{srstandtrstissues}
3223 @section SRST and TRST Issues
3225 Because SRST and TRST are hardware signals, they can have a
3226 variety of system-specific constraints. Some of the most
3231 @item @emph{Signal not available} ... Some boards don't wire
3232 SRST or TRST to the JTAG connector. Some JTAG adapters don't
3233 support such signals even if they are wired up.
3234 Use the @command{reset_config} @var{signals} options to say
3235 when either of those signals is not connected.
3236 When SRST is not available, your code might not be able to rely
3237 on controllers having been fully reset during code startup.
3238 Missing TRST is not a problem, since JTAG-level resets can
3239 be triggered using with TMS signaling.
3241 @item @emph{Signals shorted} ... Sometimes a chip, board, or
3242 adapter will connect SRST to TRST, instead of keeping them separate.
3243 Use the @command{reset_config} @var{combination} options to say
3244 when those signals aren't properly independent.
3246 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
3247 delay circuit, reset supervisor, or on-chip features can extend
3248 the effect of a JTAG adapter's reset for some time after the adapter
3249 stops issuing the reset. For example, there may be chip or board
3250 requirements that all reset pulses last for at least a
3251 certain amount of time; and reset buttons commonly have
3252 hardware debouncing.
3253 Use the @command{adapter_nsrst_delay} and @command{jtag_ntrst_delay}
3254 commands to say when extra delays are needed.
3256 @item @emph{Drive type} ... Reset lines often have a pullup
3257 resistor, letting the JTAG interface treat them as open-drain
3258 signals. But that's not a requirement, so the adapter may need
3259 to use push/pull output drivers.
3260 Also, with weak pullups it may be advisable to drive
3261 signals to both levels (push/pull) to minimize rise times.
3262 Use the @command{reset_config} @var{trst_type} and
3263 @var{srst_type} parameters to say how to drive reset signals.
3265 @item @emph{Special initialization} ... Targets sometimes need
3266 special JTAG initialization sequences to handle chip-specific
3267 issues (not limited to errata).
3268 For example, certain JTAG commands might need to be issued while
3269 the system as a whole is in a reset state (SRST active)
3270 but the JTAG scan chain is usable (TRST inactive).
3271 Many systems treat combined assertion of SRST and TRST as a
3272 trigger for a harder reset than SRST alone.
3273 Such custom reset handling is discussed later in this chapter.
3276 There can also be other issues.
3277 Some devices don't fully conform to the JTAG specifications.
3278 Trivial system-specific differences are common, such as
3279 SRST and TRST using slightly different names.
3280 There are also vendors who distribute key JTAG documentation for
3281 their chips only to developers who have signed a Non-Disclosure
3284 Sometimes there are chip-specific extensions like a requirement to use
3285 the normally-optional TRST signal (precluding use of JTAG adapters which
3286 don't pass TRST through), or needing extra steps to complete a TAP reset.
3288 In short, SRST and especially TRST handling may be very finicky,
3289 needing to cope with both architecture and board specific constraints.
3291 @section Commands for Handling Resets
3293 @deffn {Command} adapter_nsrst_assert_width milliseconds
3294 Minimum amount of time (in milliseconds) OpenOCD should wait
3295 after asserting nSRST (active-low system reset) before
3296 allowing it to be deasserted.
3299 @deffn {Command} adapter_nsrst_delay milliseconds
3300 How long (in milliseconds) OpenOCD should wait after deasserting
3301 nSRST (active-low system reset) before starting new JTAG operations.
3302 When a board has a reset button connected to SRST line it will
3303 probably have hardware debouncing, implying you should use this.
3306 @deffn {Command} jtag_ntrst_assert_width milliseconds
3307 Minimum amount of time (in milliseconds) OpenOCD should wait
3308 after asserting nTRST (active-low JTAG TAP reset) before
3309 allowing it to be deasserted.
3312 @deffn {Command} jtag_ntrst_delay milliseconds
3313 How long (in milliseconds) OpenOCD should wait after deasserting
3314 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
3317 @deffn {Command} reset_config mode_flag ...
3318 This command displays or modifies the reset configuration
3319 of your combination of JTAG board and target in target
3320 configuration scripts.
3322 Information earlier in this section describes the kind of problems
3323 the command is intended to address (@pxref{srstandtrstissues,,SRST and TRST Issues}).
3324 As a rule this command belongs only in board config files,
3325 describing issues like @emph{board doesn't connect TRST};
3326 or in user config files, addressing limitations derived
3327 from a particular combination of interface and board.
3328 (An unlikely example would be using a TRST-only adapter
3329 with a board that only wires up SRST.)
3331 The @var{mode_flag} options can be specified in any order, but only one
3332 of each type -- @var{signals}, @var{combination}, @var{gates},
3333 @var{trst_type}, @var{srst_type} and @var{connect_type}
3334 -- may be specified at a time.
3335 If you don't provide a new value for a given type, its previous
3336 value (perhaps the default) is unchanged.
3337 For example, this means that you don't need to say anything at all about
3338 TRST just to declare that if the JTAG adapter should want to drive SRST,
3339 it must explicitly be driven high (@option{srst_push_pull}).
3343 @var{signals} can specify which of the reset signals are connected.
3344 For example, If the JTAG interface provides SRST, but the board doesn't
3345 connect that signal properly, then OpenOCD can't use it.
3346 Possible values are @option{none} (the default), @option{trst_only},
3347 @option{srst_only} and @option{trst_and_srst}.
3350 If your board provides SRST and/or TRST through the JTAG connector,
3351 you must declare that so those signals can be used.
3355 The @var{combination} is an optional value specifying broken reset
3356 signal implementations.
3357 The default behaviour if no option given is @option{separate},
3358 indicating everything behaves normally.
3359 @option{srst_pulls_trst} states that the
3360 test logic is reset together with the reset of the system (e.g. NXP
3361 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
3362 the system is reset together with the test logic (only hypothetical, I
3363 haven't seen hardware with such a bug, and can be worked around).
3364 @option{combined} implies both @option{srst_pulls_trst} and
3365 @option{trst_pulls_srst}.
3368 The @var{gates} tokens control flags that describe some cases where
3369 JTAG may be unvailable during reset.
3370 @option{srst_gates_jtag} (default)
3371 indicates that asserting SRST gates the
3372 JTAG clock. This means that no communication can happen on JTAG
3373 while SRST is asserted.
3374 Its converse is @option{srst_nogate}, indicating that JTAG commands
3375 can safely be issued while SRST is active.
3378 The @var{connect_type} tokens control flags that describe some cases where
3379 SRST is asserted while connecting to the target. @option{srst_nogate}
3380 is required to use this option.
3381 @option{connect_deassert_srst} (default)
3382 indicates that SRST will not be asserted while connecting to the target.
3383 Its converse is @option{connect_assert_srst}, indicating that SRST will
3384 be asserted before any target connection.
3385 Only some targets support this feature, STM32 and STR9 are examples.
3386 This feature is useful if you are unable to connect to your target due
3387 to incorrect options byte config or illegal program execution.
3390 The optional @var{trst_type} and @var{srst_type} parameters allow the
3391 driver mode of each reset line to be specified. These values only affect
3392 JTAG interfaces with support for different driver modes, like the Amontec
3393 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
3394 relevant signal (TRST or SRST) is not connected.
3398 Possible @var{trst_type} driver modes for the test reset signal (TRST)
3399 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
3400 Most boards connect this signal to a pulldown, so the JTAG TAPs
3401 never leave reset unless they are hooked up to a JTAG adapter.
3404 Possible @var{srst_type} driver modes for the system reset signal (SRST)
3405 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
3406 Most boards connect this signal to a pullup, and allow the
3407 signal to be pulled low by various events including system
3408 powerup and pressing a reset button.
3412 @section Custom Reset Handling
3415 OpenOCD has several ways to help support the various reset
3416 mechanisms provided by chip and board vendors.
3417 The commands shown in the previous section give standard parameters.
3418 There are also @emph{event handlers} associated with TAPs or Targets.
3419 Those handlers are Tcl procedures you can provide, which are invoked
3420 at particular points in the reset sequence.
3422 @emph{When SRST is not an option} you must set
3423 up a @code{reset-assert} event handler for your target.
3424 For example, some JTAG adapters don't include the SRST signal;
3425 and some boards have multiple targets, and you won't always
3426 want to reset everything at once.
3428 After configuring those mechanisms, you might still
3429 find your board doesn't start up or reset correctly.
3430 For example, maybe it needs a slightly different sequence
3431 of SRST and/or TRST manipulations, because of quirks that
3432 the @command{reset_config} mechanism doesn't address;
3433 or asserting both might trigger a stronger reset, which
3434 needs special attention.
3436 Experiment with lower level operations, such as @command{jtag_reset}
3437 and the @command{jtag arp_*} operations shown here,
3438 to find a sequence of operations that works.
3439 @xref{JTAG Commands}.
3440 When you find a working sequence, it can be used to override
3441 @command{jtag_init}, which fires during OpenOCD startup
3442 (@pxref{configurationstage,,Configuration Stage});
3443 or @command{init_reset}, which fires during reset processing.
3445 You might also want to provide some project-specific reset
3446 schemes. For example, on a multi-target board the standard
3447 @command{reset} command would reset all targets, but you
3448 may need the ability to reset only one target at time and
3449 thus want to avoid using the board-wide SRST signal.
3451 @deffn {Overridable Procedure} init_reset mode
3452 This is invoked near the beginning of the @command{reset} command,
3453 usually to provide as much of a cold (power-up) reset as practical.
3454 By default it is also invoked from @command{jtag_init} if
3455 the scan chain does not respond to pure JTAG operations.
3456 The @var{mode} parameter is the parameter given to the
3457 low level reset command (@option{halt},
3458 @option{init}, or @option{run}), @option{setup},
3459 or potentially some other value.
3461 The default implementation just invokes @command{jtag arp_init-reset}.
3462 Replacements will normally build on low level JTAG
3463 operations such as @command{jtag_reset}.
3464 Operations here must not address individual TAPs
3465 (or their associated targets)
3466 until the JTAG scan chain has first been verified to work.
3468 Implementations must have verified the JTAG scan chain before
3470 This is done by calling @command{jtag arp_init}
3471 (or @command{jtag arp_init-reset}).
3474 @deffn Command {jtag arp_init}
3475 This validates the scan chain using just the four
3476 standard JTAG signals (TMS, TCK, TDI, TDO).
3477 It starts by issuing a JTAG-only reset.
3478 Then it performs checks to verify that the scan chain configuration
3479 matches the TAPs it can observe.
3480 Those checks include checking IDCODE values for each active TAP,
3481 and verifying the length of their instruction registers using
3482 TAP @code{-ircapture} and @code{-irmask} values.
3483 If these tests all pass, TAP @code{setup} events are
3484 issued to all TAPs with handlers for that event.
3487 @deffn Command {jtag arp_init-reset}
3488 This uses TRST and SRST to try resetting
3489 everything on the JTAG scan chain
3490 (and anything else connected to SRST).
3491 It then invokes the logic of @command{jtag arp_init}.
3495 @node TAP Declaration
3496 @chapter TAP Declaration
3497 @cindex TAP declaration
3498 @cindex TAP configuration
3500 @emph{Test Access Ports} (TAPs) are the core of JTAG.
3501 TAPs serve many roles, including:
3504 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target.
3505 @item @b{Flash Programming} Some chips program the flash directly via JTAG.
3506 Others do it indirectly, making a CPU do it.
3507 @item @b{Program Download} Using the same CPU support GDB uses,
3508 you can initialize a DRAM controller, download code to DRAM, and then
3509 start running that code.
3510 @item @b{Boundary Scan} Most chips support boundary scan, which
3511 helps test for board assembly problems like solder bridges
3512 and missing connections.
3515 OpenOCD must know about the active TAPs on your board(s).
3516 Setting up the TAPs is the core task of your configuration files.
3517 Once those TAPs are set up, you can pass their names to code
3518 which sets up CPUs and exports them as GDB targets,
3519 probes flash memory, performs low-level JTAG operations, and more.
3521 @section Scan Chains
3524 TAPs are part of a hardware @dfn{scan chain},
3525 which is a daisy chain of TAPs.
3526 They also need to be added to
3527 OpenOCD's software mirror of that hardware list,
3528 giving each member a name and associating other data with it.
3529 Simple scan chains, with a single TAP, are common in
3530 systems with a single microcontroller or microprocessor.
3531 More complex chips may have several TAPs internally.
3532 Very complex scan chains might have a dozen or more TAPs:
3533 several in one chip, more in the next, and connecting
3534 to other boards with their own chips and TAPs.
3536 You can display the list with the @command{scan_chain} command.
3537 (Don't confuse this with the list displayed by the @command{targets}
3538 command, presented in the next chapter.
3539 That only displays TAPs for CPUs which are configured as
3541 Here's what the scan chain might look like for a chip more than one TAP:
3544 TapName Enabled IdCode Expected IrLen IrCap IrMask
3545 -- ------------------ ------- ---------- ---------- ----- ----- ------
3546 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
3547 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
3548 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
3551 OpenOCD can detect some of that information, but not all
3552 of it. @xref{autoprobing,,Autoprobing}.
3553 Unfortunately, those TAPs can't always be autoconfigured,
3554 because not all devices provide good support for that.
3555 JTAG doesn't require supporting IDCODE instructions, and
3556 chips with JTAG routers may not link TAPs into the chain
3557 until they are told to do so.
3559 The configuration mechanism currently supported by OpenOCD
3560 requires explicit configuration of all TAP devices using
3561 @command{jtag newtap} commands, as detailed later in this chapter.
3562 A command like this would declare one tap and name it @code{chip1.cpu}:
3565 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
3568 Each target configuration file lists the TAPs provided
3570 Board configuration files combine all the targets on a board,
3572 Note that @emph{the order in which TAPs are declared is very important.}
3573 That declaration order must match the order in the JTAG scan chain,
3574 both inside a single chip and between them.
3575 @xref{faqtaporder,,FAQ TAP Order}.
3577 For example, the ST Microsystems STR912 chip has
3578 three separate TAPs@footnote{See the ST
3579 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
3580 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
3581 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
3582 To configure those taps, @file{target/str912.cfg}
3583 includes commands something like this:
3586 jtag newtap str912 flash ... params ...
3587 jtag newtap str912 cpu ... params ...
3588 jtag newtap str912 bs ... params ...
3591 Actual config files typically use a variable such as @code{$_CHIPNAME}
3592 instead of literals like @option{str912}, to support more than one chip
3593 of each type. @xref{Config File Guidelines}.
3595 @deffn Command {jtag names}
3596 Returns the names of all current TAPs in the scan chain.
3597 Use @command{jtag cget} or @command{jtag tapisenabled}
3598 to examine attributes and state of each TAP.
3600 foreach t [jtag names] @{
3601 puts [format "TAP: %s\n" $t]
3606 @deffn Command {scan_chain}
3607 Displays the TAPs in the scan chain configuration,
3609 The set of TAPs listed by this command is fixed by
3610 exiting the OpenOCD configuration stage,
3611 but systems with a JTAG router can
3612 enable or disable TAPs dynamically.
3615 @c FIXME! "jtag cget" should be able to return all TAP
3616 @c attributes, like "$target_name cget" does for targets.
3618 @c Probably want "jtag eventlist", and a "tap-reset" event
3619 @c (on entry to RESET state).
3624 When TAP objects are declared with @command{jtag newtap},
3625 a @dfn{dotted.name} is created for the TAP, combining the
3626 name of a module (usually a chip) and a label for the TAP.
3627 For example: @code{xilinx.tap}, @code{str912.flash},
3628 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
3629 Many other commands use that dotted.name to manipulate or
3630 refer to the TAP. For example, CPU configuration uses the
3631 name, as does declaration of NAND or NOR flash banks.
3633 The components of a dotted name should follow ``C'' symbol
3634 name rules: start with an alphabetic character, then numbers
3635 and underscores are OK; while others (including dots!) are not.
3637 @section TAP Declaration Commands
3639 @c shouldn't this be(come) a {Config Command}?
3640 @deffn Command {jtag newtap} chipname tapname configparams...
3641 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
3642 and configured according to the various @var{configparams}.
3644 The @var{chipname} is a symbolic name for the chip.
3645 Conventionally target config files use @code{$_CHIPNAME},
3646 defaulting to the model name given by the chip vendor but
3649 @cindex TAP naming convention
3650 The @var{tapname} reflects the role of that TAP,
3651 and should follow this convention:
3654 @item @code{bs} -- For boundary scan if this is a separate TAP;
3655 @item @code{cpu} -- The main CPU of the chip, alternatively
3656 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
3657 @code{arm1} and @code{arm2} on chips with two ARMs, and so forth;
3658 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
3659 @item @code{flash} -- If the chip has a flash TAP, like the str912;
3660 @item @code{jrc} -- For JTAG route controller (example: the ICEPick modules
3661 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
3662 @item @code{tap} -- Should be used only for FPGA- or CPLD-like devices
3664 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
3665 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
3666 For example, the Freescale i.MX31 has a SDMA (Smart DMA) with
3667 a JTAG TAP; that TAP should be named @code{sdma}.
3670 Every TAP requires at least the following @var{configparams}:
3673 @item @code{-irlen} @var{NUMBER}
3674 @*The length in bits of the
3675 instruction register, such as 4 or 5 bits.
3678 A TAP may also provide optional @var{configparams}:
3681 @item @code{-disable} (or @code{-enable})
3682 @*Use the @code{-disable} parameter to flag a TAP which is not
3683 linked into the scan chain after a reset using either TRST
3684 or the JTAG state machine's @sc{reset} state.
3685 You may use @code{-enable} to highlight the default state
3686 (the TAP is linked in).
3687 @xref{enablinganddisablingtaps,,Enabling and Disabling TAPs}.
3688 @item @code{-expected-id} @var{NUMBER}
3689 @*A non-zero @var{number} represents a 32-bit IDCODE
3690 which you expect to find when the scan chain is examined.
3691 These codes are not required by all JTAG devices.
3692 @emph{Repeat the option} as many times as required if more than one
3693 ID code could appear (for example, multiple versions).
3694 Specify @var{number} as zero to suppress warnings about IDCODE
3695 values that were found but not included in the list.
3697 Provide this value if at all possible, since it lets OpenOCD
3698 tell when the scan chain it sees isn't right. These values
3699 are provided in vendors' chip documentation, usually a technical
3700 reference manual. Sometimes you may need to probe the JTAG
3701 hardware to find these values.
3702 @xref{autoprobing,,Autoprobing}.
3703 @item @code{-ignore-version}
3704 @*Specify this to ignore the JTAG version field in the @code{-expected-id}
3705 option. When vendors put out multiple versions of a chip, or use the same
3706 JTAG-level ID for several largely-compatible chips, it may be more practical
3707 to ignore the version field than to update config files to handle all of
3708 the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
3709 @item @code{-ircapture} @var{NUMBER}
3710 @*The bit pattern loaded by the TAP into the JTAG shift register
3711 on entry to the @sc{ircapture} state, such as 0x01.
3712 JTAG requires the two LSBs of this value to be 01.
3713 By default, @code{-ircapture} and @code{-irmask} are set
3714 up to verify that two-bit value. You may provide
3715 additional bits if you know them, or indicate that
3716 a TAP doesn't conform to the JTAG specification.
3717 @item @code{-irmask} @var{NUMBER}
3718 @*A mask used with @code{-ircapture}
3719 to verify that instruction scans work correctly.
3720 Such scans are not used by OpenOCD except to verify that
3721 there seems to be no problems with JTAG scan chain operations.
3725 @section Other TAP commands
3727 @deffn Command {jtag cget} dotted.name @option{-event} event_name
3728 @deffnx Command {jtag configure} dotted.name @option{-event} event_name handler
3729 At this writing this TAP attribute
3730 mechanism is used only for event handling.
3731 (It is not a direct analogue of the @code{cget}/@code{configure}
3732 mechanism for debugger targets.)
3733 See the next section for information about the available events.
3735 The @code{configure} subcommand assigns an event handler,
3736 a TCL string which is evaluated when the event is triggered.
3737 The @code{cget} subcommand returns that handler.
3744 OpenOCD includes two event mechanisms.
3745 The one presented here applies to all JTAG TAPs.
3746 The other applies to debugger targets,
3747 which are associated with certain TAPs.
3749 The TAP events currently defined are:
3752 @item @b{post-reset}
3753 @* The TAP has just completed a JTAG reset.
3754 The tap may still be in the JTAG @sc{reset} state.
3755 Handlers for these events might perform initialization sequences
3756 such as issuing TCK cycles, TMS sequences to ensure
3757 exit from the ARM SWD mode, and more.
3759 Because the scan chain has not yet been verified, handlers for these events
3760 @emph{should not issue commands which scan the JTAG IR or DR registers}
3761 of any particular target.
3762 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
3764 @* The scan chain has been reset and verified.
3765 This handler may enable TAPs as needed.
3766 @item @b{tap-disable}
3767 @* The TAP needs to be disabled. This handler should
3768 implement @command{jtag tapdisable}
3769 by issuing the relevant JTAG commands.
3770 @item @b{tap-enable}
3771 @* The TAP needs to be enabled. This handler should
3772 implement @command{jtag tapenable}
3773 by issuing the relevant JTAG commands.
3776 If you need some action after each JTAG reset which isn't actually
3777 specific to any TAP (since you can't yet trust the scan chain's
3778 contents to be accurate), you might:
3781 jtag configure CHIP.jrc -event post-reset @{
3782 echo "JTAG Reset done"
3783 ... non-scan jtag operations to be done after reset
3788 @anchor{enablinganddisablingtaps}
3789 @section Enabling and Disabling TAPs
3790 @cindex JTAG Route Controller
3793 In some systems, a @dfn{JTAG Route Controller} (JRC)
3794 is used to enable and/or disable specific JTAG TAPs.
3795 Many ARM-based chips from Texas Instruments include
3796 an ``ICEPick'' module, which is a JRC.
3797 Such chips include DaVinci and OMAP3 processors.
3799 A given TAP may not be visible until the JRC has been
3800 told to link it into the scan chain; and if the JRC
3801 has been told to unlink that TAP, it will no longer
3803 Such routers address problems that JTAG ``bypass mode''
3807 @item The scan chain can only go as fast as its slowest TAP.
3808 @item Having many TAPs slows instruction scans, since all
3809 TAPs receive new instructions.
3810 @item TAPs in the scan chain must be powered up, which wastes
3811 power and prevents debugging some power management mechanisms.
3814 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
3815 as implied by the existence of JTAG routers.
3816 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
3817 does include a kind of JTAG router functionality.
3819 @c (a) currently the event handlers don't seem to be able to
3820 @c fail in a way that could lead to no-change-of-state.
3822 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
3823 shown below, and is implemented using TAP event handlers.
3824 So for example, when defining a TAP for a CPU connected to
3825 a JTAG router, your @file{target.cfg} file
3826 should define TAP event handlers using
3827 code that looks something like this:
3830 jtag configure CHIP.cpu -event tap-enable @{
3831 ... jtag operations using CHIP.jrc
3833 jtag configure CHIP.cpu -event tap-disable @{
3834 ... jtag operations using CHIP.jrc
3838 Then you might want that CPU's TAP enabled almost all the time:
3841 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
3844 Note how that particular setup event handler declaration
3845 uses quotes to evaluate @code{$CHIP} when the event is configured.
3846 Using brackets @{ @} would cause it to be evaluated later,
3847 at runtime, when it might have a different value.
3849 @deffn Command {jtag tapdisable} dotted.name
3850 If necessary, disables the tap
3851 by sending it a @option{tap-disable} event.
3852 Returns the string "1" if the tap
3853 specified by @var{dotted.name} is enabled,
3854 and "0" if it is disabled.
3857 @deffn Command {jtag tapenable} dotted.name
3858 If necessary, enables the tap
3859 by sending it a @option{tap-enable} event.
3860 Returns the string "1" if the tap
3861 specified by @var{dotted.name} is enabled,
3862 and "0" if it is disabled.
3865 @deffn Command {jtag tapisenabled} dotted.name
3866 Returns the string "1" if the tap
3867 specified by @var{dotted.name} is enabled,
3868 and "0" if it is disabled.
3871 Humans will find the @command{scan_chain} command more helpful
3872 for querying the state of the JTAG taps.
3876 @anchor{autoprobing}
3877 @section Autoprobing
3879 @cindex JTAG autoprobe
3881 TAP configuration is the first thing that needs to be done
3882 after interface and reset configuration. Sometimes it's
3883 hard finding out what TAPs exist, or how they are identified.
3884 Vendor documentation is not always easy to find and use.
3886 To help you get past such problems, OpenOCD has a limited
3887 @emph{autoprobing} ability to look at the scan chain, doing
3888 a @dfn{blind interrogation} and then reporting the TAPs it finds.
3889 To use this mechanism, start the OpenOCD server with only data
3890 that configures your JTAG interface, and arranges to come up
3891 with a slow clock (many devices don't support fast JTAG clocks
3892 right when they come out of reset).
3894 For example, your @file{openocd.cfg} file might have:
3897 source [find interface/olimex-arm-usb-tiny-h.cfg]
3898 reset_config trst_and_srst
3902 When you start the server without any TAPs configured, it will
3903 attempt to autoconfigure the TAPs. There are two parts to this:
3906 @item @emph{TAP discovery} ...
3907 After a JTAG reset (sometimes a system reset may be needed too),
3908 each TAP's data registers will hold the contents of either the
3909 IDCODE or BYPASS register.
3910 If JTAG communication is working, OpenOCD will see each TAP,
3911 and report what @option{-expected-id} to use with it.
3912 @item @emph{IR Length discovery} ...
3913 Unfortunately JTAG does not provide a reliable way to find out
3914 the value of the @option{-irlen} parameter to use with a TAP
3916 If OpenOCD can discover the length of a TAP's instruction
3917 register, it will report it.
3918 Otherwise you may need to consult vendor documentation, such
3919 as chip data sheets or BSDL files.
3922 In many cases your board will have a simple scan chain with just
3923 a single device. Here's what OpenOCD reported with one board
3924 that's a bit more complex:
3928 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
3929 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
3930 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
3931 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
3932 AUTO auto0.tap - use "... -irlen 4"
3933 AUTO auto1.tap - use "... -irlen 4"
3934 AUTO auto2.tap - use "... -irlen 6"
3935 no gdb ports allocated as no target has been specified
3938 Given that information, you should be able to either find some existing
3939 config files to use, or create your own. If you create your own, you
3940 would configure from the bottom up: first a @file{target.cfg} file
3941 with these TAPs, any targets associated with them, and any on-chip
3942 resources; then a @file{board.cfg} with off-chip resources, clocking,
3945 @node CPU Configuration
3946 @chapter CPU Configuration
3949 This chapter discusses how to set up GDB debug targets for CPUs.
3950 You can also access these targets without GDB
3951 (@pxref{Architecture and Core Commands},
3952 and @ref{targetstatehandling,,Target State handling}) and
3953 through various kinds of NAND and NOR flash commands.
3954 If you have multiple CPUs you can have multiple such targets.
3956 We'll start by looking at how to examine the targets you have,
3957 then look at how to add one more target and how to configure it.
3959 @section Target List
3960 @cindex target, current
3961 @cindex target, list
3963 All targets that have been set up are part of a list,
3964 where each member has a name.
3965 That name should normally be the same as the TAP name.
3966 You can display the list with the @command{targets}
3968 This display often has only one CPU; here's what it might
3969 look like with more than one:
3971 TargetName Type Endian TapName State
3972 -- ------------------ ---------- ------ ------------------ ------------
3973 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
3974 1 MyTarget cortex_m little mychip.foo tap-disabled
3977 One member of that list is the @dfn{current target}, which
3978 is implicitly referenced by many commands.
3979 It's the one marked with a @code{*} near the target name.
3980 In particular, memory addresses often refer to the address
3981 space seen by that current target.
3982 Commands like @command{mdw} (memory display words)
3983 and @command{flash erase_address} (erase NOR flash blocks)
3984 are examples; and there are many more.
3986 Several commands let you examine the list of targets:
3988 @deffn Command {target current}
3989 Returns the name of the current target.
3992 @deffn Command {target names}
3993 Lists the names of all current targets in the list.
3995 foreach t [target names] @{
3996 puts [format "Target: %s\n" $t]
4001 @c yep, "target list" would have been better.
4002 @c plus maybe "target setdefault".
4004 @deffn Command targets [name]
4005 @emph{Note: the name of this command is plural. Other target
4006 command names are singular.}
4008 With no parameter, this command displays a table of all known
4009 targets in a user friendly form.
4011 With a parameter, this command sets the current target to
4012 the given target with the given @var{name}; this is
4013 only relevant on boards which have more than one target.
4016 @section Target CPU Types
4020 Each target has a @dfn{CPU type}, as shown in the output of
4021 the @command{targets} command. You need to specify that type
4022 when calling @command{target create}.
4023 The CPU type indicates more than just the instruction set.
4024 It also indicates how that instruction set is implemented,
4025 what kind of debug support it integrates,
4026 whether it has an MMU (and if so, what kind),
4027 what core-specific commands may be available
4028 (@pxref{Architecture and Core Commands}),
4031 It's easy to see what target types are supported,
4032 since there's a command to list them.
4034 @anchor{targettypes}
4035 @deffn Command {target types}
4036 Lists all supported target types.
4037 At this writing, the supported CPU types are:
4040 @item @code{arm11} -- this is a generation of ARMv6 cores
4041 @item @code{arm720t} -- this is an ARMv4 core with an MMU
4042 @item @code{arm7tdmi} -- this is an ARMv4 core
4043 @item @code{arm920t} -- this is an ARMv4 core with an MMU
4044 @item @code{arm926ejs} -- this is an ARMv5 core with an MMU
4045 @item @code{arm966e} -- this is an ARMv5 core
4046 @item @code{arm9tdmi} -- this is an ARMv4 core
4047 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
4048 (Support for this is preliminary and incomplete.)
4049 @item @code{cortex_a} -- this is an ARMv7 core with an MMU
4050 @item @code{cortex_m} -- this is an ARMv7 core, supporting only the
4051 compact Thumb2 instruction set.
4052 @item @code{dragonite} -- resembles arm966e
4053 @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
4054 (Support for this is still incomplete.)
4055 @item @code{fa526} -- resembles arm920 (w/o Thumb)
4056 @item @code{feroceon} -- resembles arm926
4057 @item @code{mips_m4k} -- a MIPS core
4058 @item @code{xscale} -- this is actually an architecture,
4059 not a CPU type. It is based on the ARMv5 architecture.
4060 @item @code{openrisc} -- this is an OpenRISC 1000 core.
4061 The current implementation supports three JTAG TAP cores:
4063 @item @code{OpenCores TAP} (See: @url{http://opencores.org/project,jtag})
4064 @item @code{Altera Virtual JTAG TAP} (See: @url{http://www.altera.com/literature/ug/ug_virtualjtag.pdf})
4065 @item @code{Xilinx BSCAN_* virtual JTAG interface} (See: @url{http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/spartan6_hdl.pdf})
4067 And two debug interfaces cores:
4069 @item @code{Advanced debug interface} (See: @url{http://opencores.org/project,adv_debug_sys})
4070 @item @code{SoC Debug Interface} (See: @url{http://opencores.org/project,dbg_interface})
4075 To avoid being confused by the variety of ARM based cores, remember
4076 this key point: @emph{ARM is a technology licencing company}.
4077 (See: @url{http://www.arm.com}.)
4078 The CPU name used by OpenOCD will reflect the CPU design that was
4079 licenced, not a vendor brand which incorporates that design.
4080 Name prefixes like arm7, arm9, arm11, and cortex
4081 reflect design generations;
4082 while names like ARMv4, ARMv5, ARMv6, and ARMv7
4083 reflect an architecture version implemented by a CPU design.
4085 @anchor{targetconfiguration}
4086 @section Target Configuration
4088 Before creating a ``target'', you must have added its TAP to the scan chain.
4089 When you've added that TAP, you will have a @code{dotted.name}
4090 which is used to set up the CPU support.
4091 The chip-specific configuration file will normally configure its CPU(s)
4092 right after it adds all of the chip's TAPs to the scan chain.
4094 Although you can set up a target in one step, it's often clearer if you
4095 use shorter commands and do it in two steps: create it, then configure
4097 All operations on the target after it's created will use a new
4098 command, created as part of target creation.
4100 The two main things to configure after target creation are
4101 a work area, which usually has target-specific defaults even
4102 if the board setup code overrides them later;
4103 and event handlers (@pxref{targetevents,,Target Events}), which tend
4104 to be much more board-specific.
4105 The key steps you use might look something like this
4108 target create MyTarget cortex_m -chain-position mychip.cpu
4109 $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
4110 $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
4111 $MyTarget configure -event reset-init @{ myboard_reinit @}
4114 You should specify a working area if you can; typically it uses some
4116 Such a working area can speed up many things, including bulk
4117 writes to target memory;
4118 flash operations like checking to see if memory needs to be erased;
4119 GDB memory checksumming;
4123 On more complex chips, the work area can become
4124 inaccessible when application code
4125 (such as an operating system)
4126 enables or disables the MMU.
4127 For example, the particular MMU context used to acess the virtual
4128 address will probably matter ... and that context might not have
4129 easy access to other addresses needed.
4130 At this writing, OpenOCD doesn't have much MMU intelligence.
4133 It's often very useful to define a @code{reset-init} event handler.
4134 For systems that are normally used with a boot loader,
4135 common tasks include updating clocks and initializing memory
4137 That may be needed to let you write the boot loader into flash,
4138 in order to ``de-brick'' your board; or to load programs into
4139 external DDR memory without having run the boot loader.
4141 @deffn Command {target create} target_name type configparams...
4142 This command creates a GDB debug target that refers to a specific JTAG tap.
4143 It enters that target into a list, and creates a new
4144 command (@command{@var{target_name}}) which is used for various
4145 purposes including additional configuration.
4148 @item @var{target_name} ... is the name of the debug target.
4149 By convention this should be the same as the @emph{dotted.name}
4150 of the TAP associated with this target, which must be specified here
4151 using the @code{-chain-position @var{dotted.name}} configparam.
4153 This name is also used to create the target object command,
4154 referred to here as @command{$target_name},
4155 and in other places the target needs to be identified.
4156 @item @var{type} ... specifies the target type. @xref{targettypes,,target types}.
4157 @item @var{configparams} ... all parameters accepted by
4158 @command{$target_name configure} are permitted.
4159 If the target is big-endian, set it here with @code{-endian big}.
4161 You @emph{must} set the @code{-chain-position @var{dotted.name}} here.
4165 @deffn Command {$target_name configure} configparams...
4166 The options accepted by this command may also be
4167 specified as parameters to @command{target create}.
4168 Their values can later be queried one at a time by
4169 using the @command{$target_name cget} command.
4171 @emph{Warning:} changing some of these after setup is dangerous.
4172 For example, moving a target from one TAP to another;
4173 and changing its endianness.
4177 @item @code{-chain-position} @var{dotted.name} -- names the TAP
4178 used to access this target.
4180 @item @code{-endian} (@option{big}|@option{little}) -- specifies
4181 whether the CPU uses big or little endian conventions
4183 @item @code{-event} @var{event_name} @var{event_body} --
4184 @xref{targetevents,,Target Events}.
4185 Note that this updates a list of named event handlers.
4186 Calling this twice with two different event names assigns
4187 two different handlers, but calling it twice with the
4188 same event name assigns only one handler.
4190 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
4191 whether the work area gets backed up; by default,
4192 @emph{it is not backed up.}
4193 When possible, use a working_area that doesn't need to be backed up,
4194 since performing a backup slows down operations.
4195 For example, the beginning of an SRAM block is likely to
4196 be used by most build systems, but the end is often unused.
4198 @item @code{-work-area-size} @var{size} -- specify work are size,
4199 in bytes. The same size applies regardless of whether its physical
4200 or virtual address is being used.
4202 @item @code{-work-area-phys} @var{address} -- set the work area
4203 base @var{address} to be used when no MMU is active.
4205 @item @code{-work-area-virt} @var{address} -- set the work area
4206 base @var{address} to be used when an MMU is active.
4207 @emph{Do not specify a value for this except on targets with an MMU.}
4208 The value should normally correspond to a static mapping for the
4209 @code{-work-area-phys} address, set up by the current operating system.
4212 @item @code{-rtos} @var{rtos_type} -- enable rtos support for target,
4213 @var{rtos_type} can be one of @option{auto}|@option{eCos}|@option{ThreadX}|
4214 @option{FreeRTOS}|@option{linux}|@option{ChibiOS}|@option{embKernel}|@option{mqx}
4215 @xref{gdbrtossupport,,RTOS Support}.
4220 @section Other $target_name Commands
4221 @cindex object command
4223 The Tcl/Tk language has the concept of object commands,
4224 and OpenOCD adopts that same model for targets.
4226 A good Tk example is a on screen button.
4227 Once a button is created a button
4228 has a name (a path in Tk terms) and that name is useable as a first
4229 class command. For example in Tk, one can create a button and later
4230 configure it like this:
4234 button .foobar -background red -command @{ foo @}
4236 .foobar configure -foreground blue
4238 set x [.foobar cget -background]
4240 puts [format "The button is %s" $x]
4243 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
4244 button, and its object commands are invoked the same way.
4247 str912.cpu mww 0x1234 0x42
4248 omap3530.cpu mww 0x5555 123
4251 The commands supported by OpenOCD target objects are:
4253 @deffn Command {$target_name arp_examine}
4254 @deffnx Command {$target_name arp_halt}
4255 @deffnx Command {$target_name arp_poll}
4256 @deffnx Command {$target_name arp_reset}
4257 @deffnx Command {$target_name arp_waitstate}
4258 Internal OpenOCD scripts (most notably @file{startup.tcl})
4259 use these to deal with specific reset cases.
4260 They are not otherwise documented here.
4263 @deffn Command {$target_name array2mem} arrayname width address count
4264 @deffnx Command {$target_name mem2array} arrayname width address count
4265 These provide an efficient script-oriented interface to memory.
4266 The @code{array2mem} primitive writes bytes, halfwords, or words;
4267 while @code{mem2array} reads them.
4268 In both cases, the TCL side uses an array, and
4269 the target side uses raw memory.
4271 The efficiency comes from enabling the use of
4272 bulk JTAG data transfer operations.
4273 The script orientation comes from working with data
4274 values that are packaged for use by TCL scripts;
4275 @command{mdw} type primitives only print data they retrieve,
4276 and neither store nor return those values.
4279 @item @var{arrayname} ... is the name of an array variable
4280 @item @var{width} ... is 8/16/32 - indicating the memory access size
4281 @item @var{address} ... is the target memory address
4282 @item @var{count} ... is the number of elements to process
4286 @deffn Command {$target_name cget} queryparm
4287 Each configuration parameter accepted by
4288 @command{$target_name configure}
4289 can be individually queried, to return its current value.
4290 The @var{queryparm} is a parameter name
4291 accepted by that command, such as @code{-work-area-phys}.
4292 There are a few special cases:
4295 @item @code{-event} @var{event_name} -- returns the handler for the
4296 event named @var{event_name}.
4297 This is a special case because setting a handler requires
4299 @item @code{-type} -- returns the target type.
4300 This is a special case because this is set using
4301 @command{target create} and can't be changed
4302 using @command{$target_name configure}.
4305 For example, if you wanted to summarize information about
4306 all the targets you might use something like this:
4309 foreach name [target names] @{
4310 set y [$name cget -endian]
4311 set z [$name cget -type]
4312 puts [format "Chip %d is %s, Endian: %s, type: %s" \
4318 @anchor{targetcurstate}
4319 @deffn Command {$target_name curstate}
4320 Displays the current target state:
4321 @code{debug-running},
4324 @code{running}, or @code{unknown}.
4325 (Also, @pxref{eventpolling,,Event Polling}.)
4328 @deffn Command {$target_name eventlist}
4329 Displays a table listing all event handlers
4330 currently associated with this target.
4331 @xref{targetevents,,Target Events}.
4334 @deffn Command {$target_name invoke-event} event_name
4335 Invokes the handler for the event named @var{event_name}.
4336 (This is primarily intended for use by OpenOCD framework
4337 code, for example by the reset code in @file{startup.tcl}.)
4340 @deffn Command {$target_name mdw} addr [count]
4341 @deffnx Command {$target_name mdh} addr [count]
4342 @deffnx Command {$target_name mdb} addr [count]
4343 Display contents of address @var{addr}, as
4344 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
4345 or 8-bit bytes (@command{mdb}).
4346 If @var{count} is specified, displays that many units.
4347 (If you want to manipulate the data instead of displaying it,
4348 see the @code{mem2array} primitives.)
4351 @deffn Command {$target_name mww} addr word
4352 @deffnx Command {$target_name mwh} addr halfword
4353 @deffnx Command {$target_name mwb} addr byte
4354 Writes the specified @var{word} (32 bits),
4355 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4356 at the specified address @var{addr}.
4359 @anchor{targetevents}
4360 @section Target Events
4361 @cindex target events
4363 At various times, certain things can happen, or you want them to happen.
4366 @item What should happen when GDB connects? Should your target reset?
4367 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
4368 @item Is using SRST appropriate (and possible) on your system?
4369 Or instead of that, do you need to issue JTAG commands to trigger reset?
4370 SRST usually resets everything on the scan chain, which can be inappropriate.
4371 @item During reset, do you need to write to certain memory locations
4372 to set up system clocks or
4373 to reconfigure the SDRAM?
4374 How about configuring the watchdog timer, or other peripherals,
4375 to stop running while you hold the core stopped for debugging?
4378 All of the above items can be addressed by target event handlers.
4379 These are set up by @command{$target_name configure -event} or
4380 @command{target create ... -event}.
4382 The programmer's model matches the @code{-command} option used in Tcl/Tk
4383 buttons and events. The two examples below act the same, but one creates
4384 and invokes a small procedure while the other inlines it.
4387 proc my_attach_proc @{ @} @{
4391 mychip.cpu configure -event gdb-attach my_attach_proc
4392 mychip.cpu configure -event gdb-attach @{
4394 # To make flash probe and gdb load to flash work
4395 # we need a reset init.
4400 The following target events are defined:
4403 @item @b{debug-halted}
4404 @* The target has halted for debug reasons (i.e.: breakpoint)
4405 @item @b{debug-resumed}
4406 @* The target has resumed (i.e.: gdb said run)
4407 @item @b{early-halted}
4408 @* Occurs early in the halt process
4409 @item @b{examine-start}
4410 @* Before target examine is called.
4411 @item @b{examine-end}
4412 @* After target examine is called with no errors.
4413 @item @b{gdb-attach}
4414 @* When GDB connects. This is before any communication with the target, so this
4415 can be used to set up the target so it is possible to probe flash. Probing flash
4416 is necessary during gdb connect if gdb load is to write the image to flash. Another
4417 use of the flash memory map is for GDB to automatically hardware/software breakpoints
4418 depending on whether the breakpoint is in RAM or read only memory.
4419 @item @b{gdb-detach}
4420 @* When GDB disconnects
4422 @* When the target has halted and GDB is not doing anything (see early halt)
4423 @item @b{gdb-flash-erase-start}
4424 @* Before the GDB flash process tries to erase the flash (default is
4426 @item @b{gdb-flash-erase-end}
4427 @* After the GDB flash process has finished erasing the flash
4428 @item @b{gdb-flash-write-start}
4429 @* Before GDB writes to the flash
4430 @item @b{gdb-flash-write-end}
4431 @* After GDB writes to the flash (default is @code{reset halt})
4433 @* Before the target steps, gdb is trying to start/resume the target
4435 @* The target has halted
4436 @item @b{reset-assert-pre}
4437 @* Issued as part of @command{reset} processing
4438 after @command{reset_init} was triggered
4439 but before either SRST alone is re-asserted on the scan chain,
4440 or @code{reset-assert} is triggered.
4441 @item @b{reset-assert}
4442 @* Issued as part of @command{reset} processing
4443 after @command{reset-assert-pre} was triggered.
4444 When such a handler is present, cores which support this event will use
4445 it instead of asserting SRST.
4446 This support is essential for debugging with JTAG interfaces which
4447 don't include an SRST line (JTAG doesn't require SRST), and for
4448 selective reset on scan chains that have multiple targets.
4449 @item @b{reset-assert-post}
4450 @* Issued as part of @command{reset} processing
4451 after @code{reset-assert} has been triggered.
4452 or the target asserted SRST on the entire scan chain.
4453 @item @b{reset-deassert-pre}
4454 @* Issued as part of @command{reset} processing
4455 after @code{reset-assert-post} has been triggered.
4456 @item @b{reset-deassert-post}
4457 @* Issued as part of @command{reset} processing
4458 after @code{reset-deassert-pre} has been triggered
4459 and (if the target is using it) after SRST has been
4460 released on the scan chain.
4462 @* Issued as the final step in @command{reset} processing.
4464 @item @b{reset-halt-post}
4465 @* Currently not used
4466 @item @b{reset-halt-pre}
4467 @* Currently not used
4469 @item @b{reset-init}
4470 @* Used by @b{reset init} command for board-specific initialization.
4471 This event fires after @emph{reset-deassert-post}.
4473 This is where you would configure PLLs and clocking, set up DRAM so
4474 you can download programs that don't fit in on-chip SRAM, set up pin
4475 multiplexing, and so on.
4476 (You may be able to switch to a fast JTAG clock rate here, after
4477 the target clocks are fully set up.)
4478 @item @b{reset-start}
4479 @* Issued as part of @command{reset} processing
4480 before @command{reset_init} is called.
4482 This is the most robust place to use @command{jtag_rclk}
4483 or @command{adapter_khz} to switch to a low JTAG clock rate,
4484 when reset disables PLLs needed to use a fast clock.
4486 @item @b{reset-wait-pos}
4487 @* Currently not used
4488 @item @b{reset-wait-pre}
4489 @* Currently not used
4491 @item @b{resume-start}
4492 @* Before any target is resumed
4493 @item @b{resume-end}
4494 @* After all targets have resumed
4496 @* Target has resumed
4497 @item @b{trace-config}
4498 @* After target hardware trace configuration was changed
4501 @node Flash Commands
4502 @chapter Flash Commands
4504 OpenOCD has different commands for NOR and NAND flash;
4505 the ``flash'' command works with NOR flash, while
4506 the ``nand'' command works with NAND flash.
4507 This partially reflects different hardware technologies:
4508 NOR flash usually supports direct CPU instruction and data bus access,
4509 while data from a NAND flash must be copied to memory before it can be
4510 used. (SPI flash must also be copied to memory before use.)
4511 However, the documentation also uses ``flash'' as a generic term;
4512 for example, ``Put flash configuration in board-specific files''.
4516 @item Configure via the command @command{flash bank}
4517 @* Do this in a board-specific configuration file,
4518 passing parameters as needed by the driver.
4519 @item Operate on the flash via @command{flash subcommand}
4520 @* Often commands to manipulate the flash are typed by a human, or run
4521 via a script in some automated way. Common tasks include writing a
4522 boot loader, operating system, or other data.
4524 @* Flashing via GDB requires the flash be configured via ``flash
4525 bank'', and the GDB flash features be enabled.
4526 @xref{gdbconfiguration,,GDB Configuration}.
4529 Many CPUs have the ablity to ``boot'' from the first flash bank.
4530 This means that misprogramming that bank can ``brick'' a system,
4531 so that it can't boot.
4532 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
4533 board by (re)installing working boot firmware.
4535 @anchor{norconfiguration}
4536 @section Flash Configuration Commands
4537 @cindex flash configuration
4539 @deffn {Config Command} {flash bank} name driver base size chip_width bus_width target [driver_options]
4540 Configures a flash bank which provides persistent storage
4541 for addresses from @math{base} to @math{base + size - 1}.
4542 These banks will often be visible to GDB through the target's memory map.
4543 In some cases, configuring a flash bank will activate extra commands;
4544 see the driver-specific documentation.
4547 @item @var{name} ... may be used to reference the flash bank
4548 in other flash commands. A number is also available.
4549 @item @var{driver} ... identifies the controller driver
4550 associated with the flash bank being declared.
4551 This is usually @code{cfi} for external flash, or else
4552 the name of a microcontroller with embedded flash memory.
4553 @xref{flashdriverlist,,Flash Driver List}.
4554 @item @var{base} ... Base address of the flash chip.
4555 @item @var{size} ... Size of the chip, in bytes.
4556 For some drivers, this value is detected from the hardware.
4557 @item @var{chip_width} ... Width of the flash chip, in bytes;
4558 ignored for most microcontroller drivers.
4559 @item @var{bus_width} ... Width of the data bus used to access the
4560 chip, in bytes; ignored for most microcontroller drivers.
4561 @item @var{target} ... Names the target used to issue
4562 commands to the flash controller.
4563 @comment Actually, it's currently a controller-specific parameter...
4564 @item @var{driver_options} ... drivers may support, or require,
4565 additional parameters. See the driver-specific documentation
4566 for more information.
4569 This command is not available after OpenOCD initialization has completed.
4570 Use it in board specific configuration files, not interactively.
4574 @comment the REAL name for this command is "ocd_flash_banks"
4575 @comment less confusing would be: "flash list" (like "nand list")
4576 @deffn Command {flash banks}
4577 Prints a one-line summary of each device that was
4578 declared using @command{flash bank}, numbered from zero.
4579 Note that this is the @emph{plural} form;
4580 the @emph{singular} form is a very different command.
4583 @deffn Command {flash list}
4584 Retrieves a list of associative arrays for each device that was
4585 declared using @command{flash bank}, numbered from zero.
4586 This returned list can be manipulated easily from within scripts.
4589 @deffn Command {flash probe} num
4590 Identify the flash, or validate the parameters of the configured flash. Operation
4591 depends on the flash type.
4592 The @var{num} parameter is a value shown by @command{flash banks}.
4593 Most flash commands will implicitly @emph{autoprobe} the bank;
4594 flash drivers can distinguish between probing and autoprobing,
4595 but most don't bother.
4598 @section Erasing, Reading, Writing to Flash
4599 @cindex flash erasing
4600 @cindex flash reading
4601 @cindex flash writing
4602 @cindex flash programming
4603 @anchor{flashprogrammingcommands}
4605 One feature distinguishing NOR flash from NAND or serial flash technologies
4606 is that for read access, it acts exactly like any other addressible memory.
4607 This means you can use normal memory read commands like @command{mdw} or
4608 @command{dump_image} with it, with no special @command{flash} subcommands.
4609 @xref{memoryaccess,,Memory access}, and @ref{imageaccess,,Image access}.
4611 Write access works differently. Flash memory normally needs to be erased
4612 before it's written. Erasing a sector turns all of its bits to ones, and
4613 writing can turn ones into zeroes. This is why there are special commands
4614 for interactive erasing and writing, and why GDB needs to know which parts
4615 of the address space hold NOR flash memory.
4618 Most of these erase and write commands leverage the fact that NOR flash
4619 chips consume target address space. They implicitly refer to the current
4620 JTAG target, and map from an address in that target's address space
4621 back to a flash bank.
4622 @comment In May 2009, those mappings may fail if any bank associated
4623 @comment with that target doesn't succesfuly autoprobe ... bug worth fixing?
4624 A few commands use abstract addressing based on bank and sector numbers,
4625 and don't depend on searching the current target and its address space.
4626 Avoid confusing the two command models.
4629 Some flash chips implement software protection against accidental writes,
4630 since such buggy writes could in some cases ``brick'' a system.
4631 For such systems, erasing and writing may require sector protection to be
4633 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
4634 and AT91SAM7 on-chip flash.
4635 @xref{flashprotect,,flash protect}.
4637 @deffn Command {flash erase_sector} num first last
4638 Erase sectors in bank @var{num}, starting at sector @var{first}
4639 up to and including @var{last}.
4640 Sector numbering starts at 0.
4641 Providing a @var{last} sector of @option{last}
4642 specifies "to the end of the flash bank".
4643 The @var{num} parameter is a value shown by @command{flash banks}.
4646 @deffn Command {flash erase_address} [@option{pad}] [@option{unlock}] address length
4647 Erase sectors starting at @var{address} for @var{length} bytes.
4648 Unless @option{pad} is specified, @math{address} must begin a
4649 flash sector, and @math{address + length - 1} must end a sector.
4650 Specifying @option{pad} erases extra data at the beginning and/or
4651 end of the specified region, as needed to erase only full sectors.
4652 The flash bank to use is inferred from the @var{address}, and
4653 the specified length must stay within that bank.
4654 As a special case, when @var{length} is zero and @var{address} is
4655 the start of the bank, the whole flash is erased.
4656 If @option{unlock} is specified, then the flash is unprotected
4657 before erase starts.
4660 @deffn Command {flash fillw} address word length
4661 @deffnx Command {flash fillh} address halfword length
4662 @deffnx Command {flash fillb} address byte length
4663 Fills flash memory with the specified @var{word} (32 bits),
4664 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4665 starting at @var{address} and continuing
4666 for @var{length} units (word/halfword/byte).
4667 No erasure is done before writing; when needed, that must be done
4668 before issuing this command.
4669 Writes are done in blocks of up to 1024 bytes, and each write is
4670 verified by reading back the data and comparing it to what was written.
4671 The flash bank to use is inferred from the @var{address} of
4672 each block, and the specified length must stay within that bank.
4674 @comment no current checks for errors if fill blocks touch multiple banks!
4676 @deffn Command {flash write_bank} num filename offset
4677 Write the binary @file{filename} to flash bank @var{num},
4678 starting at @var{offset} bytes from the beginning of the bank.
4679 The @var{num} parameter is a value shown by @command{flash banks}.
4682 @deffn Command {flash read_bank} num filename offset length
4683 Read @var{length} bytes from the flash bank @var{num} starting at @var{offset}
4684 and write the contents to the binary @file{filename}.
4685 The @var{num} parameter is a value shown by @command{flash banks}.
4688 @deffn Command {flash verify_bank} num filename offset
4689 Compare the contents of the binary file @var{filename} with the contents of the
4690 flash @var{num} starting at @var{offset}. Fails if the contents do not match.
4691 The @var{num} parameter is a value shown by @command{flash banks}.
4694 @deffn Command {flash write_image} [erase] [unlock] filename [offset] [type]
4695 Write the image @file{filename} to the current target's flash bank(s).
4696 Only loadable sections from the image are written.
4697 A relocation @var{offset} may be specified, in which case it is added
4698 to the base address for each section in the image.
4699 The file [@var{type}] can be specified
4700 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
4701 @option{elf} (ELF file), @option{s19} (Motorola s19).
4702 @option{mem}, or @option{builder}.
4703 The relevant flash sectors will be erased prior to programming
4704 if the @option{erase} parameter is given. If @option{unlock} is
4705 provided, then the flash banks are unlocked before erase and
4706 program. The flash bank to use is inferred from the address of
4710 Be careful using the @option{erase} flag when the flash is holding
4711 data you want to preserve.
4712 Portions of the flash outside those described in the image's
4713 sections might be erased with no notice.
4716 When a section of the image being written does not fill out all the
4717 sectors it uses, the unwritten parts of those sectors are necessarily
4718 also erased, because sectors can't be partially erased.
4720 Data stored in sector "holes" between image sections are also affected.
4721 For example, "@command{flash write_image erase ...}" of an image with
4722 one byte at the beginning of a flash bank and one byte at the end
4723 erases the entire bank -- not just the two sectors being written.
4725 Also, when flash protection is important, you must re-apply it after
4726 it has been removed by the @option{unlock} flag.
4731 @section Other Flash commands
4732 @cindex flash protection
4734 @deffn Command {flash erase_check} num
4735 Check erase state of sectors in flash bank @var{num},
4736 and display that status.
4737 The @var{num} parameter is a value shown by @command{flash banks}.
4740 @deffn Command {flash info} num
4741 Print info about flash bank @var{num}
4742 The @var{num} parameter is a value shown by @command{flash banks}.
4743 This command will first query the hardware, it does not print cached
4744 and possibly stale information.
4747 @anchor{flashprotect}
4748 @deffn Command {flash protect} num first last (@option{on}|@option{off})
4749 Enable (@option{on}) or disable (@option{off}) protection of flash sectors
4750 in flash bank @var{num}, starting at sector @var{first}
4751 and continuing up to and including @var{last}.
4752 Providing a @var{last} sector of @option{last}
4753 specifies "to the end of the flash bank".
4754 The @var{num} parameter is a value shown by @command{flash banks}.
4757 @deffn Command {flash padded_value} num value
4758 Sets the default value used for padding any image sections, This should
4759 normally match the flash bank erased value. If not specified by this
4760 comamnd or the flash driver then it defaults to 0xff.
4764 @deffn Command {program} filename [verify] [reset] [exit] [offset]
4765 This is a helper script that simplifies using OpenOCD as a standalone
4766 programmer. The only required parameter is @option{filename}, the others are optional.
4767 @xref{Flash Programming}.
4770 @anchor{flashdriverlist}
4771 @section Flash Driver List
4772 As noted above, the @command{flash bank} command requires a driver name,
4773 and allows driver-specific options and behaviors.
4774 Some drivers also activate driver-specific commands.
4776 @deffn {Flash Driver} virtual
4777 This is a special driver that maps a previously defined bank to another
4778 address. All bank settings will be copied from the master physical bank.
4780 The @var{virtual} driver defines one mandatory parameters,
4783 @item @var{master_bank} The bank that this virtual address refers to.
4786 So in the following example addresses 0xbfc00000 and 0x9fc00000 refer to
4787 the flash bank defined at address 0x1fc00000. Any cmds executed on
4788 the virtual banks are actually performed on the physical banks.
4790 flash bank $_FLASHNAME pic32mx 0x1fc00000 0 0 0 $_TARGETNAME
4791 flash bank vbank0 virtual 0xbfc00000 0 0 0 $_TARGETNAME $_FLASHNAME
4792 flash bank vbank1 virtual 0x9fc00000 0 0 0 $_TARGETNAME $_FLASHNAME
4796 @subsection External Flash
4798 @deffn {Flash Driver} cfi
4799 @cindex Common Flash Interface
4801 The ``Common Flash Interface'' (CFI) is the main standard for
4802 external NOR flash chips, each of which connects to a
4803 specific external chip select on the CPU.
4804 Frequently the first such chip is used to boot the system.
4805 Your board's @code{reset-init} handler might need to
4806 configure additional chip selects using other commands (like: @command{mww} to
4807 configure a bus and its timings), or
4808 perhaps configure a GPIO pin that controls the ``write protect'' pin
4810 The CFI driver can use a target-specific working area to significantly
4813 The CFI driver can accept the following optional parameters, in any order:
4816 @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
4817 like AM29LV010 and similar types.
4818 @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
4819 @item @var{bus_swap} ... when data bytes in a 16-bit flash needs to be swapped.
4822 To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
4823 wide on a sixteen bit bus:
4826 flash bank $_FLASHNAME cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
4827 flash bank $_FLASHNAME cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
4830 To configure one bank of 32 MBytes
4831 built from two sixteen bit (two byte) wide parts wired in parallel
4832 to create a thirty-two bit (four byte) bus with doubled throughput:
4835 flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
4838 @c "cfi part_id" disabled
4841 @deffn {Flash Driver} jtagspi
4842 @cindex Generic JTAG2SPI driver
4846 Several FPGAs and CPLDs can retrieve their configuration (bitstream) from a
4847 SPI flash connected to them. To access this flash from the host, the device
4848 is first programmed with a special proxy bitstream that
4849 exposes the SPI flash on the device's JTAG interface. The flash can then be
4850 accessed through JTAG.
4852 Since signaling between JTAG and SPI is compatible, all that is required for
4853 a proxy bitstream is to connect TDI-MOSI, TDO-MISO, TCK-CLK and activate
4854 the flash chip select when the JTAG state machine is in SHIFT-DR. Such
4855 a bitstream for several Xilinx FPGAs can be found in
4856 @file{contrib/loaders/flash/fpga/xilinx_bscan_spi.py}. It requires migen
4857 (@url{http://github.com/m-labs/migen}) and a Xilinx toolchain to build.
4859 This flash bank driver requires a target on a JTAG tap and will access that
4860 tap directly. Since no support from the target is needed, the target can be a
4861 "testee" dummy. Since the target does not expose the flash memory
4862 mapping, target commands that would otherwise be expected to access the flash
4863 will not work. These include all @command{*_image} and
4864 @command{$target_name m*} commands as well as @command{program}. Equivalent
4865 functionality is available through the @command{flash write_bank},
4866 @command{flash read_bank}, and @command{flash verify_bank} commands.
4869 @item @var{ir} ... is loaded into the JTAG IR to map the flash as the JTAG DR.
4870 For the bitstreams generated from @file{xilinx_bscan_spi.py} this is the
4871 @var{USER1} instruction.
4872 @item @var{dr_length} ... is the length of the DR register. This will be 1 for
4873 @file{xilinx_bscan_spi.py} bitstreams and most other cases.
4877 target create $_TARGETNAME testee -chain-position $_CHIPNAME.fpga
4878 set _XILINX_USER1 0x02
4880 flash bank $_FLASHNAME spi 0x0 0 0 0 $_TARGETNAME $_XILINX_USER1 $_DR_LENGTH
4884 @deffn {Flash Driver} lpcspifi
4885 @cindex NXP SPI Flash Interface
4888 NXP's LPC43xx and LPC18xx families include a proprietary SPI
4889 Flash Interface (SPIFI) peripheral that can drive and provide
4890 memory mapped access to external SPI flash devices.
4892 The lpcspifi driver initializes this interface and provides
4893 program and erase functionality for these serial flash devices.
4894 Use of this driver @b{requires} a working area of at least 1kB
4895 to be configured on the target device; more than this will
4896 significantly reduce flash programming times.
4898 The setup command only requires the @var{base} parameter. All
4899 other parameters are ignored, and the flash size and layout
4900 are configured by the driver.
4903 flash bank $_FLASHNAME lpcspifi 0x14000000 0 0 0 $_TARGETNAME
4908 @deffn {Flash Driver} stmsmi
4909 @cindex STMicroelectronics Serial Memory Interface
4912 Some devices form STMicroelectronics (e.g. STR75x MCU family,
4913 SPEAr MPU family) include a proprietary
4914 ``Serial Memory Interface'' (SMI) controller able to drive external
4916 Depending on specific device and board configuration, up to 4 external
4917 flash devices can be connected.
4919 SMI makes the flash content directly accessible in the CPU address
4920 space; each external device is mapped in a memory bank.
4921 CPU can directly read data, execute code and boot from SMI banks.
4922 Normal OpenOCD commands like @command{mdw} can be used to display
4925 The setup command only requires the @var{base} parameter in order
4926 to identify the memory bank.
4927 All other parameters are ignored. Additional information, like
4928 flash size, are detected automatically.
4931 flash bank $_FLASHNAME stmsmi 0xf8000000 0 0 0 $_TARGETNAME
4936 @deffn {Flash Driver} mrvlqspi
4937 This driver supports QSPI flash controller of Marvell's Wireless
4938 Microcontroller platform.
4940 The flash size is autodetected based on the table of known JEDEC IDs
4941 hardcoded in the OpenOCD sources.
4944 flash bank $_FLASHNAME mrvlqspi 0x0 0 0 0 $_TARGETNAME 0x46010000
4949 @subsection Internal Flash (Microcontrollers)
4951 @deffn {Flash Driver} aduc702x
4952 The ADUC702x analog microcontrollers from Analog Devices
4953 include internal flash and use ARM7TDMI cores.
4954 The aduc702x flash driver works with models ADUC7019 through ADUC7028.
4955 The setup command only requires the @var{target} argument
4956 since all devices in this family have the same memory layout.
4959 flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME
4964 @deffn {Flash Driver} at91samd
4966 All members of the ATSAMD, ATSAMR, ATSAML and ATSAMC microcontroller
4967 families from Atmel include internal flash and use ARM's Cortex-M0+ core.
4968 This driver uses the same cmd names/syntax as @xref{at91sam3}.
4970 @deffn Command {at91samd chip-erase}
4971 Issues a complete Flash erase via the Device Service Unit (DSU). This can be
4972 used to erase a chip back to its factory state and does not require the
4973 processor to be halted.
4976 @deffn Command {at91samd set-security}
4977 Secures the Flash via the Set Security Bit (SSB) command. This prevents access
4978 to the Flash and can only be undone by using the chip-erase command which
4979 erases the Flash contents and turns off the security bit. Warning: at this
4980 time, openocd will not be able to communicate with a secured chip and it is
4981 therefore not possible to chip-erase it without using another tool.
4984 at91samd set-security enable
4988 @deffn Command {at91samd eeprom}
4989 Shows or sets the EEPROM emulation size configuration, stored in the User Row
4990 of the Flash. When setting, the EEPROM size must be specified in bytes and it
4991 must be one of the permitted sizes according to the datasheet. Settings are
4992 written immediately but only take effect on MCU reset. EEPROM emulation
4993 requires additional firmware support and the minumum EEPROM size may not be
4994 the same as the minimum that the hardware supports. Set the EEPROM size to 0
4995 in order to disable this feature.
4999 at91samd eeprom 1024
5003 @deffn Command {at91samd bootloader}
5004 Shows or sets the bootloader size configuration, stored in the User Row of the
5005 Flash. This is called the BOOTPROT region. When setting, the bootloader size
5006 must be specified in bytes and it must be one of the permitted sizes according
5007 to the datasheet. Settings are written immediately but only take effect on
5008 MCU reset. Setting the bootloader size to 0 disables bootloader protection.
5012 at91samd bootloader 16384
5016 @deffn Command {at91samd dsu_reset_deassert}
5017 This command releases internal reset held by DSU
5018 and prepares reset vector catch in case of reset halt.
5019 Command is used internally in event event reset-deassert-post.
5025 @deffn {Flash Driver} at91sam3
5027 All members of the AT91SAM3 microcontroller family from
5028 Atmel include internal flash and use ARM's Cortex-M3 core. The driver
5029 currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
5030 that the driver was orginaly developed and tested using the
5031 AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in
5032 the family was cribbed from the data sheet. @emph{Note to future
5033 readers/updaters: Please remove this worrysome comment after other
5034 chips are confirmed.}
5036 The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
5037 have one flash bank. In all cases the flash banks are at
5038 the following fixed locations:
5041 # Flash bank 0 - all chips
5042 flash bank $_FLASHNAME at91sam3 0x00080000 0 1 1 $_TARGETNAME
5043 # Flash bank 1 - only 256K chips
5044 flash bank $_FLASHNAME at91sam3 0x00100000 0 1 1 $_TARGETNAME
5047 Internally, the AT91SAM3 flash memory is organized as follows.
5048 Unlike the AT91SAM7 chips, these are not used as parameters
5049 to the @command{flash bank} command:
5052 @item @emph{N-Banks:} 256K chips have 2 banks, others have 1 bank.
5053 @item @emph{Bank Size:} 128K/64K Per flash bank
5054 @item @emph{Sectors:} 16 or 8 per bank
5055 @item @emph{SectorSize:} 8K Per Sector
5056 @item @emph{PageSize:} 256 bytes per page. Note that OpenOCD operates on 'sector' sizes, not page sizes.
5059 The AT91SAM3 driver adds some additional commands:
5061 @deffn Command {at91sam3 gpnvm}
5062 @deffnx Command {at91sam3 gpnvm clear} number
5063 @deffnx Command {at91sam3 gpnvm set} number
5064 @deffnx Command {at91sam3 gpnvm show} [@option{all}|number]
5065 With no parameters, @command{show} or @command{show all},
5066 shows the status of all GPNVM bits.
5067 With @command{show} @var{number}, displays that bit.
5069 With @command{set} @var{number} or @command{clear} @var{number},
5070 modifies that GPNVM bit.
5073 @deffn Command {at91sam3 info}
5074 This command attempts to display information about the AT91SAM3
5075 chip. @emph{First} it read the @code{CHIPID_CIDR} [address 0x400e0740, see
5076 Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
5077 document id: doc6430A] and decodes the values. @emph{Second} it reads the
5078 various clock configuration registers and attempts to display how it
5079 believes the chip is configured. By default, the SLOWCLK is assumed to
5080 be 32768 Hz, see the command @command{at91sam3 slowclk}.
5083 @deffn Command {at91sam3 slowclk} [value]
5084 This command shows/sets the slow clock frequency used in the
5085 @command{at91sam3 info} command calculations above.
5089 @deffn {Flash Driver} at91sam4
5091 All members of the AT91SAM4 microcontroller family from
5092 Atmel include internal flash and use ARM's Cortex-M4 core.
5093 This driver uses the same cmd names/syntax as @xref{at91sam3}.
5096 @deffn {Flash Driver} at91sam4l
5098 All members of the AT91SAM4L microcontroller family from
5099 Atmel include internal flash and use ARM's Cortex-M4 core.
5100 This driver uses the same cmd names/syntax as @xref{at91sam3}.
5102 The AT91SAM4L driver adds some additional commands:
5103 @deffn Command {at91sam4l smap_reset_deassert}
5104 This command releases internal reset held by SMAP
5105 and prepares reset vector catch in case of reset halt.
5106 Command is used internally in event event reset-deassert-post.
5110 @deffn {Flash Driver} atsamv
5112 All members of the ATSAMV, ATSAMS, and ATSAME families from
5113 Atmel include internal flash and use ARM's Cortex-M7 core.
5114 This driver uses the same cmd names/syntax as @xref{at91sam3}.
5117 @deffn {Flash Driver} at91sam7
5118 All members of the AT91SAM7 microcontroller family from Atmel include
5119 internal flash and use ARM7TDMI cores. The driver automatically
5120 recognizes a number of these chips using the chip identification
5121 register, and autoconfigures itself.
5124 flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME
5127 For chips which are not recognized by the controller driver, you must
5128 provide additional parameters in the following order:
5131 @item @var{chip_model} ... label used with @command{flash info}
5133 @item @var{sectors_per_bank}
5134 @item @var{pages_per_sector}
5135 @item @var{pages_size}
5136 @item @var{num_nvm_bits}
5137 @item @var{freq_khz} ... required if an external clock is provided,
5138 optional (but recommended) when the oscillator frequency is known
5141 It is recommended that you provide zeroes for all of those values
5142 except the clock frequency, so that everything except that frequency
5143 will be autoconfigured.
5144 Knowing the frequency helps ensure correct timings for flash access.
5146 The flash controller handles erases automatically on a page (128/256 byte)
5147 basis, so explicit erase commands are not necessary for flash programming.
5148 However, there is an ``EraseAll`` command that can erase an entire flash
5149 plane (of up to 256KB), and it will be used automatically when you issue
5150 @command{flash erase_sector} or @command{flash erase_address} commands.
5152 @deffn Command {at91sam7 gpnvm} bitnum (@option{set}|@option{clear})
5153 Set or clear a ``General Purpose Non-Volatile Memory'' (GPNVM)
5154 bit for the processor. Each processor has a number of such bits,
5155 used for controlling features such as brownout detection (so they
5156 are not truly general purpose).
5158 This assumes that the first flash bank (number 0) is associated with
5159 the appropriate at91sam7 target.
5164 @deffn {Flash Driver} avr
5165 The AVR 8-bit microcontrollers from Atmel integrate flash memory.
5166 @emph{The current implementation is incomplete.}
5167 @comment - defines mass_erase ... pointless given flash_erase_address
5170 @deffn {Flash Driver} efm32
5171 All members of the EFM32 microcontroller family from Energy Micro include
5172 internal flash and use ARM Cortex M3 cores. The driver automatically recognizes
5173 a number of these chips using the chip identification register, and
5174 autoconfigures itself.
5176 flash bank $_FLASHNAME efm32 0 0 0 0 $_TARGETNAME
5178 @emph{The current implementation is incomplete. Unprotecting flash pages is not
5182 @deffn {Flash Driver} fm3
5183 All members of the FM3 microcontroller family from Fujitsu
5184 include internal flash and use ARM Cortex M3 cores.
5185 The @var{fm3} driver uses the @var{target} parameter to select the
5186 correct bank config, it can currently be one of the following:
5187 @code{mb9bfxx1.cpu}, @code{mb9bfxx2.cpu}, @code{mb9bfxx3.cpu},
5188 @code{mb9bfxx4.cpu}, @code{mb9bfxx5.cpu} or @code{mb9bfxx6.cpu}.
5191 flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME
5195 @deffn {Flash Driver} kinetis
5197 Kx and KLx members of the Kinetis microcontroller family from Freescale include
5198 internal flash and use ARM Cortex M0+ or M4 cores. The driver automatically
5199 recognizes flash size and a number of flash banks (1-4) using the chip
5200 identification register, and autoconfigures itself.
5203 flash bank $_FLASHNAME kinetis 0 0 0 0 $_TARGETNAME
5206 @deffn Command {kinetis mdm check_security}
5207 Checks status of device security lock. Used internally in examine-end event.
5210 @deffn Command {kinetis mdm mass_erase}
5211 Issues a complete Flash erase via the MDM-AP.
5212 This can be used to erase a chip back to its factory state.
5213 Command removes security lock from a device (use of SRST highly recommended).
5214 It does not require the processor to be halted.
5217 @deffn Command {kinetis nvm_partition}
5218 For FlexNVM devices only (KxxDX and KxxFX).
5219 Command shows or sets data flash or EEPROM backup size in kilobytes,
5220 sets two EEPROM blocks sizes in bytes and enables/disables loading
5221 of EEPROM contents to FlexRAM during reset.
5223 For details see device reference manual, Flash Memory Module,
5224 Program Partition command.
5226 Setting is possible only once after mass_erase.
5227 Reset the device after partition setting.
5229 Show partition size:
5231 kinetis nvm_partition info
5234 Set 32 KB data flash, rest of FlexNVM is EEPROM backup. EEPROM has two blocks
5235 of 512 and 1536 bytes and its contents is loaded to FlexRAM during reset:
5237 kinetis nvm_partition dataflash 32 512 1536 on
5240 Set 16 KB EEPROM backup, rest of FlexNVM is a data flash. EEPROM has two blocks
5241 of 1024 bytes and its contents is not loaded to FlexRAM during reset:
5243 kinetis nvm_partition eebkp 16 1024 1024 off
5247 @deffn Command {kinetis disable_wdog}
5248 For Kx devices only (KLx has different COP watchdog, it is not supported).
5249 Command disables watchdog timer.
5253 @deffn {Flash Driver} kinetis_ke
5255 KE members of the Kinetis microcontroller family from Freescale include
5256 internal flash and use ARM Cortex M0+. The driver automatically recognizes
5257 the KE family and sub-family using the chip identification register, and
5258 autoconfigures itself.
5261 flash bank $_FLASHNAME kinetis_ke 0 0 0 0 $_TARGETNAME
5264 @deffn Command {kinetis_ke mdm check_security}
5265 Checks status of device security lock. Used internally in examine-end event.
5268 @deffn Command {kinetis_ke mdm mass_erase}
5269 Issues a complete Flash erase via the MDM-AP.
5270 This can be used to erase a chip back to its factory state.
5271 Command removes security lock from a device (use of SRST highly recommended).
5272 It does not require the processor to be halted.
5275 @deffn Command {kinetis_ke disable_wdog}
5276 Command disables watchdog timer.
5280 @deffn {Flash Driver} fm4
5281 All members of the FM4 microcontroller family from Spansion (formerly Fujitsu)
5282 include internal flash and use ARM Cortex-M4 cores.
5283 The @var{fm4} driver uses a @var{family} parameter to select the
5284 correct bank config, it can currently be one of the following:
5285 @code{MB9BFx64}, @code{MB9BFx65}, @code{MB9BFx66}, @code{MB9BFx67}, @code{MB9BFx68},
5286 @code{S6E2Cx8}, @code{S6E2Cx9}, @code{S6E2CxA} or @code{S6E2Dx},
5287 with @code{x} treated as wildcard and otherwise case (and any trailing
5288 characters) ignored.
5291 flash bank $@{_FLASHNAME@}0 fm4 0x00000000 0 0 0 $_TARGETNAME S6E2CCAJ0A
5292 flash bank $@{_FLASHNAME@}1 fm4 0x00100000 0 0 0 $_TARGETNAME S6E2CCAJ0A
5294 @emph{The current implementation is incomplete. Protection is not supported,
5295 nor is Chip Erase (only Sector Erase is implemented).}
5298 @deffn {Flash Driver} lpc2000
5299 This is the driver to support internal flash of all members of the
5300 LPC11(x)00 and LPC1300 microcontroller families and most members of
5301 the LPC800, LPC1500, LPC1700, LPC1800, LPC2000, LPC4000 and LPC54100
5302 microcontroller families from NXP.
5305 There are LPC2000 devices which are not supported by the @var{lpc2000}
5307 The LPC2888 is supported by the @var{lpc288x} driver.
5308 The LPC29xx family is supported by the @var{lpc2900} driver.
5311 The @var{lpc2000} driver defines two mandatory and one optional parameters,
5312 which must appear in the following order:
5315 @item @var{variant} ... required, may be
5316 @option{lpc2000_v1} (older LPC21xx and LPC22xx)
5317 @option{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
5318 @option{lpc1700} (LPC175x and LPC176x and LPC177x/8x)
5319 @option{lpc4300} - available also as @option{lpc1800} alias (LPC18x[2357] and
5321 @option{lpc800} (LPC8xx)
5322 @option{lpc1100} (LPC11(x)xx and LPC13xx)
5323 @option{lpc1500} (LPC15xx)
5324 @option{lpc54100} (LPC541xx)
5325 @option{lpc4000} (LPC40xx)
5326 or @option{auto} - automatically detects flash variant and size for LPC11(x)00,
5327 LPC8xx, LPC13xx, LPC17xx and LPC40xx
5328 @item @var{clock_kHz} ... the frequency, in kiloHertz,
5329 at which the core is running
5330 @item @option{calc_checksum} ... optional (but you probably want to provide this!),
5331 telling the driver to calculate a valid checksum for the exception vector table.
5333 If you don't provide @option{calc_checksum} when you're writing the vector
5334 table, the boot ROM will almost certainly ignore your flash image.
5335 However, if you do provide it,
5336 with most tool chains @command{verify_image} will fail.
5340 LPC flashes don't require the chip and bus width to be specified.
5343 flash bank $_FLASHNAME lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
5344 lpc2000_v2 14765 calc_checksum
5347 @deffn {Command} {lpc2000 part_id} bank
5348 Displays the four byte part identifier associated with
5349 the specified flash @var{bank}.
5353 @deffn {Flash Driver} lpc288x
5354 The LPC2888 microcontroller from NXP needs slightly different flash
5355 support from its lpc2000 siblings.
5356 The @var{lpc288x} driver defines one mandatory parameter,
5357 the programming clock rate in Hz.
5358 LPC flashes don't require the chip and bus width to be specified.
5361 flash bank $_FLASHNAME lpc288x 0 0 0 0 $_TARGETNAME 12000000
5365 @deffn {Flash Driver} lpc2900
5366 This driver supports the LPC29xx ARM968E based microcontroller family
5369 The predefined parameters @var{base}, @var{size}, @var{chip_width} and
5370 @var{bus_width} of the @code{flash bank} command are ignored. Flash size and
5371 sector layout are auto-configured by the driver.
5372 The driver has one additional mandatory parameter: The CPU clock rate
5373 (in kHz) at the time the flash operations will take place. Most of the time this
5374 will not be the crystal frequency, but a higher PLL frequency. The
5375 @code{reset-init} event handler in the board script is usually the place where
5378 The driver rejects flashless devices (currently the LPC2930).
5380 The EEPROM in LPC2900 devices is not mapped directly into the address space.
5381 It must be handled much more like NAND flash memory, and will therefore be
5382 handled by a separate @code{lpc2900_eeprom} driver (not yet available).
5384 Sector protection in terms of the LPC2900 is handled transparently. Every time a
5385 sector needs to be erased or programmed, it is automatically unprotected.
5386 What is shown as protection status in the @code{flash info} command, is
5387 actually the LPC2900 @emph{sector security}. This is a mechanism to prevent a
5388 sector from ever being erased or programmed again. As this is an irreversible
5389 mechanism, it is handled by a special command (@code{lpc2900 secure_sector}),
5390 and not by the standard @code{flash protect} command.
5392 Example for a 125 MHz clock frequency:
5394 flash bank $_FLASHNAME lpc2900 0 0 0 0 $_TARGETNAME 125000
5397 Some @code{lpc2900}-specific commands are defined. In the following command list,
5398 the @var{bank} parameter is the bank number as obtained by the
5399 @code{flash banks} command.
5401 @deffn Command {lpc2900 signature} bank
5402 Calculates a 128-bit hash value, the @emph{signature}, from the whole flash
5403 content. This is a hardware feature of the flash block, hence the calculation is
5404 very fast. You may use this to verify the content of a programmed device against
5409 signature: 0x5f40cdc8:0xc64e592e:0x10490f89:0x32a0f317
5413 @deffn Command {lpc2900 read_custom} bank filename
5414 Reads the 912 bytes of customer information from the flash index sector, and
5415 saves it to a file in binary format.
5418 lpc2900 read_custom 0 /path_to/customer_info.bin
5422 The index sector of the flash is a @emph{write-only} sector. It cannot be
5423 erased! In order to guard against unintentional write access, all following
5424 commands need to be preceeded by a successful call to the @code{password}
5427 @deffn Command {lpc2900 password} bank password
5428 You need to use this command right before each of the following commands:
5429 @code{lpc2900 write_custom}, @code{lpc2900 secure_sector},
5430 @code{lpc2900 secure_jtag}.
5432 The password string is fixed to "I_know_what_I_am_doing".
5435 lpc2900 password 0 I_know_what_I_am_doing
5436 Potentially dangerous operation allowed in next command!
5440 @deffn Command {lpc2900 write_custom} bank filename type
5441 Writes the content of the file into the customer info space of the flash index
5442 sector. The filetype can be specified with the @var{type} field. Possible values
5443 for @var{type} are: @var{bin} (binary), @var{ihex} (Intel hex format),
5444 @var{elf} (ELF binary) or @var{s19} (Motorola S-records). The file must
5445 contain a single section, and the contained data length must be exactly
5447 @quotation Attention
5448 This cannot be reverted! Be careful!
5452 lpc2900 write_custom 0 /path_to/customer_info.bin bin
5456 @deffn Command {lpc2900 secure_sector} bank first last
5457 Secures the sector range from @var{first} to @var{last} (including) against
5458 further program and erase operations. The sector security will be effective
5459 after the next power cycle.
5460 @quotation Attention
5461 This cannot be reverted! Be careful!
5463 Secured sectors appear as @emph{protected} in the @code{flash info} command.
5466 lpc2900 secure_sector 0 1 1
5468 #0 : lpc2900 at 0x20000000, size 0x000c0000, (...)
5469 # 0: 0x00000000 (0x2000 8kB) not protected
5470 # 1: 0x00002000 (0x2000 8kB) protected
5471 # 2: 0x00004000 (0x2000 8kB) not protected
5475 @deffn Command {lpc2900 secure_jtag} bank
5476 Irreversibly disable the JTAG port. The new JTAG security setting will be
5477 effective after the next power cycle.
5478 @quotation Attention
5479 This cannot be reverted! Be careful!
5483 lpc2900 secure_jtag 0
5488 @deffn {Flash Driver} mdr
5489 This drivers handles the integrated NOR flash on Milandr Cortex-M
5490 based controllers. A known limitation is that the Info memory can't be
5491 read or verified as it's not memory mapped.
5494 flash bank <name> mdr <base> <size> \
5495 0 0 <target#> @var{type} @var{page_count} @var{sec_count}
5499 @item @var{type} - 0 for main memory, 1 for info memory
5500 @item @var{page_count} - total number of pages
5501 @item @var{sec_count} - number of sector per page count
5506 if @{ [info exists IMEMORY] && [string equal $IMEMORY true] @} @{
5507 flash bank $@{_CHIPNAME@}_info.flash mdr 0x00000000 0x01000 \
5508 0 0 $_TARGETNAME 1 1 4
5510 flash bank $_CHIPNAME.flash mdr 0x00000000 0x20000 \
5511 0 0 $_TARGETNAME 0 32 4
5516 @deffn {Flash Driver} niietcm4
5517 This drivers handles the integrated NOR flash on NIIET Cortex-M4
5518 based controllers. Flash size and sector layout are auto-configured by the driver.
5519 Main flash memory is called "Bootflash" and has main region and info region.
5520 Info region is NOT memory mapped by default,
5521 but it can replace first part of main region if needed.
5522 Full erase, single and block writes are supported for both main and info regions.
5523 There is additional not memory mapped flash called "Userflash", which
5524 also have division into regions: main and info.
5525 Purpose of userflash - to store system and user settings.
5526 Driver has special commands to perform operations with this memmory.
5529 flash bank $_FLASHNAME niietcm4 0 0 0 0 $_TARGETNAME
5532 Some niietcm4-specific commands are defined:
5534 @deffn Command {niietcm4 uflash_read_byte} bank ('main'|'info') address
5535 Read byte from main or info userflash region.
5538 @deffn Command {niietcm4 uflash_write_byte} bank ('main'|'info') address value
5539 Write byte to main or info userflash region.
5542 @deffn Command {niietcm4 uflash_full_erase} bank
5543 Erase all userflash including info region.
5546 @deffn Command {niietcm4 uflash_erase} bank ('main'|'info') first_sector last_sector
5547 Erase sectors of main or info userflash region, starting at sector first up to and including last.
5550 @deffn Command {niietcm4 uflash_protect_check} bank ('main'|'info')
5551 Check sectors protect.
5554 @deffn Command {niietcm4 uflash_protect} bank ('main'|'info') first_sector last_sector ('on'|'off')
5555 Protect sectors of main or info userflash region, starting at sector first up to and including last.
5558 @deffn Command {niietcm4 bflash_info_remap} bank ('on'|'off')
5559 Enable remapping bootflash info region to 0x00000000 (or 0x40000000 if external memory boot used).
5562 @deffn Command {niietcm4 extmem_cfg} bank ('gpioa'|'gpiob'|'gpioc'|'gpiod'|'gpioe'|'gpiof'|'gpiog'|'gpioh') pin_num ('func1'|'func3')
5563 Configure external memory interface for boot.
5566 @deffn Command {niietcm4 service_mode_erase} bank
5567 Perform emergency erase of all flash (bootflash and userflash).
5570 @deffn Command {niietcm4 driver_info} bank
5571 Show information about flash driver.
5576 @deffn {Flash Driver} nrf51
5577 All members of the nRF51 microcontroller families from Nordic Semiconductor
5578 include internal flash and use ARM Cortex-M0 core.
5581 flash bank $_FLASHNAME nrf51 0 0x00000000 0 0 $_TARGETNAME
5584 Some nrf51-specific commands are defined:
5586 @deffn Command {nrf51 mass_erase}
5587 Erases the contents of the code memory and user information
5588 configuration registers as well. It must be noted that this command
5589 works only for chips that do not have factory pre-programmed region 0
5595 @deffn {Flash Driver} ocl
5596 This driver is an implementation of the ``on chip flash loader''
5597 protocol proposed by Pavel Chromy.
5599 It is a minimalistic command-response protocol intended to be used
5600 over a DCC when communicating with an internal or external flash
5601 loader running from RAM. An example implementation for AT91SAM7x is
5602 available in @file{contrib/loaders/flash/at91sam7x/}.
5605 flash bank $_FLASHNAME ocl 0 0 0 0 $_TARGETNAME
5609 @deffn {Flash Driver} pic32mx
5610 The PIC32MX microcontrollers are based on the MIPS 4K cores,
5611 and integrate flash memory.
5614 flash bank $_FLASHNAME pix32mx 0x1fc00000 0 0 0 $_TARGETNAME
5615 flash bank $_FLASHNAME pix32mx 0x1d000000 0 0 0 $_TARGETNAME
5618 @comment numerous *disabled* commands are defined:
5619 @comment - chip_erase ... pointless given flash_erase_address
5620 @comment - lock, unlock ... pointless given protect on/off (yes?)
5621 @comment - pgm_word ... shouldn't bank be deduced from address??
5622 Some pic32mx-specific commands are defined:
5623 @deffn Command {pic32mx pgm_word} address value bank
5624 Programs the specified 32-bit @var{value} at the given @var{address}
5625 in the specified chip @var{bank}.
5627 @deffn Command {pic32mx unlock} bank
5628 Unlock and erase specified chip @var{bank}.
5629 This will remove any Code Protection.
5633 @deffn {Flash Driver} psoc4
5634 All members of the PSoC 41xx/42xx microcontroller family from Cypress
5635 include internal flash and use ARM Cortex M0 cores.
5636 The driver automatically recognizes a number of these chips using
5637 the chip identification register, and autoconfigures itself.
5639 Note: Erased internal flash reads as 00.
5640 System ROM of PSoC 4 does not implement erase of a flash sector.
5643 flash bank $_FLASHNAME psoc4 0 0 0 0 $_TARGETNAME
5646 psoc4-specific commands
5647 @deffn Command {psoc4 flash_autoerase} num (on|off)
5648 Enables or disables autoerase mode for a flash bank.
5650 If flash_autoerase is off, use mass_erase before flash programming.
5651 Flash erase command fails if region to erase is not whole flash memory.
5653 If flash_autoerase is on, a sector is both erased and programmed in one
5654 system ROM call. Flash erase command is ignored.
5655 This mode is suitable for gdb load.
5657 The @var{num} parameter is a value shown by @command{flash banks}.
5660 @deffn Command {psoc4 mass_erase} num
5661 Erases the contents of the flash memory, protection and security lock.
5663 The @var{num} parameter is a value shown by @command{flash banks}.
5667 @deffn {Flash Driver} sim3x
5668 All members of the SiM3 microcontroller family from Silicon Laboratories
5669 include internal flash and use ARM Cortex M3 cores. It supports both JTAG
5671 The @var{sim3x} driver tries to probe the device to auto detect the MCU.
5672 If this failes, it will use the @var{size} parameter as the size of flash bank.
5675 flash bank $_FLASHNAME sim3x 0 $_CPUROMSIZE 0 0 $_TARGETNAME
5678 There are 2 commands defined in the @var{sim3x} driver:
5680 @deffn Command {sim3x mass_erase}
5681 Erases the complete flash. This is used to unlock the flash.
5682 And this command is only possible when using the SWD interface.
5685 @deffn Command {sim3x lock}
5686 Lock the flash. To unlock use the @command{sim3x mass_erase} command.
5690 @deffn {Flash Driver} stellaris
5691 All members of the Stellaris LM3Sxxx, LM4x and Tiva C microcontroller
5692 families from Texas Instruments include internal flash. The driver
5693 automatically recognizes a number of these chips using the chip
5694 identification register, and autoconfigures itself.
5695 @footnote{Currently there is a @command{stellaris mass_erase} command.
5696 That seems pointless since the same effect can be had using the
5697 standard @command{flash erase_address} command.}
5700 flash bank $_FLASHNAME stellaris 0 0 0 0 $_TARGETNAME
5703 @deffn Command {stellaris recover}
5704 Performs the @emph{Recovering a "Locked" Device} procedure to restore
5705 the flash and its associated nonvolatile registers to their factory
5706 default values (erased). This is the only way to remove flash
5707 protection or re-enable debugging if that capability has been
5710 Note that the final "power cycle the chip" step in this procedure
5711 must be performed by hand, since OpenOCD can't do it.
5713 if more than one Stellaris chip is connected, the procedure is
5714 applied to all of them.
5719 @deffn {Flash Driver} stm32f1x
5720 All members of the STM32F0, STM32F1 and STM32F3 microcontroller families
5721 from ST Microelectronics include internal flash and use ARM Cortex-M0/M3/M4 cores.
5722 The driver automatically recognizes a number of these chips using
5723 the chip identification register, and autoconfigures itself.
5726 flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
5729 Note that some devices have been found that have a flash size register that contains
5730 an invalid value, to workaround this issue you can override the probed value used by
5734 flash bank $_FLASHNAME stm32f1x 0 0x20000 0 0 $_TARGETNAME
5737 If you have a target with dual flash banks then define the second bank
5738 as per the following example.
5740 flash bank $_FLASHNAME stm32f1x 0x08080000 0 0 0 $_TARGETNAME
5743 Some stm32f1x-specific commands
5744 @footnote{Currently there is a @command{stm32f1x mass_erase} command.
5745 That seems pointless since the same effect can be had using the
5746 standard @command{flash erase_address} command.}
5749 @deffn Command {stm32f1x lock} num
5750 Locks the entire stm32 device.
5751 The @var{num} parameter is a value shown by @command{flash banks}.
5754 @deffn Command {stm32f1x unlock} num
5755 Unlocks the entire stm32 device.
5756 The @var{num} parameter is a value shown by @command{flash banks}.
5759 @deffn Command {stm32f1x options_read} num
5760 Read and display the stm32 option bytes written by
5761 the @command{stm32f1x options_write} command.
5762 The @var{num} parameter is a value shown by @command{flash banks}.
5765 @deffn Command {stm32f1x options_write} num (@option{SWWDG}|@option{HWWDG}) (@option{RSTSTNDBY}|@option{NORSTSTNDBY}) (@option{RSTSTOP}|@option{NORSTSTOP})
5766 Writes the stm32 option byte with the specified values.
5767 The @var{num} parameter is a value shown by @command{flash banks}.
5771 @deffn {Flash Driver} stm32f2x
5772 All members of the STM32F2 and STM32F4 microcontroller families from ST Microelectronics
5773 include internal flash and use ARM Cortex-M3/M4 cores.
5774 The driver automatically recognizes a number of these chips using
5775 the chip identification register, and autoconfigures itself.
5777 Note that some devices have been found that have a flash size register that contains
5778 an invalid value, to workaround this issue you can override the probed value used by
5782 flash bank $_FLASHNAME stm32f2x 0 0x20000 0 0 $_TARGETNAME
5785 Some stm32f2x-specific commands are defined:
5787 @deffn Command {stm32f2x lock} num
5788 Locks the entire stm32 device.
5789 The @var{num} parameter is a value shown by @command{flash banks}.
5792 @deffn Command {stm32f2x unlock} num
5793 Unlocks the entire stm32 device.
5794 The @var{num} parameter is a value shown by @command{flash banks}.
5798 @deffn {Flash Driver} stm32lx
5799 All members of the STM32L microcontroller families from ST Microelectronics
5800 include internal flash and use ARM Cortex-M3 and Cortex-M0+ cores.
5801 The driver automatically recognizes a number of these chips using
5802 the chip identification register, and autoconfigures itself.
5804 Note that some devices have been found that have a flash size register that contains
5805 an invalid value, to workaround this issue you can override the probed value used by
5806 the flash driver. If you use 0 as the bank base address, it tells the
5807 driver to autodetect the bank location assuming you're configuring the
5811 flash bank $_FLASHNAME stm32lx 0x08000000 0x20000 0 0 $_TARGETNAME
5814 Some stm32lx-specific commands are defined:
5816 @deffn Command {stm32lx mass_erase} num
5817 Mass erases the entire stm32lx device (all flash banks and EEPROM
5818 data). This is the only way to unlock a protected flash (unless RDP
5819 Level is 2 which can't be unlocked at all).
5820 The @var{num} parameter is a value shown by @command{flash banks}.
5824 @deffn {Flash Driver} str7x
5825 All members of the STR7 microcontroller family from ST Microelectronics
5826 include internal flash and use ARM7TDMI cores.
5827 The @var{str7x} driver defines one mandatory parameter, @var{variant},
5828 which is either @code{STR71x}, @code{STR73x} or @code{STR75x}.
5831 flash bank $_FLASHNAME str7x \
5832 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
5835 @deffn Command {str7x disable_jtag} bank
5836 Activate the Debug/Readout protection mechanism
5837 for the specified flash bank.
5841 @deffn {Flash Driver} str9x
5842 Most members of the STR9 microcontroller family from ST Microelectronics
5843 include internal flash and use ARM966E cores.
5844 The str9 needs the flash controller to be configured using
5845 the @command{str9x flash_config} command prior to Flash programming.
5848 flash bank $_FLASHNAME str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
5849 str9x flash_config 0 4 2 0 0x80000
5852 @deffn Command {str9x flash_config} num bbsr nbbsr bbadr nbbadr
5853 Configures the str9 flash controller.
5854 The @var{num} parameter is a value shown by @command{flash banks}.
5857 @item @var{bbsr} - Boot Bank Size register
5858 @item @var{nbbsr} - Non Boot Bank Size register
5859 @item @var{bbadr} - Boot Bank Start Address register
5860 @item @var{nbbadr} - Boot Bank Start Address register
5866 @deffn {Flash Driver} str9xpec
5869 Only use this driver for locking/unlocking the device or configuring the option bytes.
5870 Use the standard str9 driver for programming.
5871 Before using the flash commands the turbo mode must be enabled using the
5872 @command{str9xpec enable_turbo} command.
5874 Here is some background info to help
5875 you better understand how this driver works. OpenOCD has two flash drivers for
5879 Standard driver @option{str9x} programmed via the str9 core. Normally used for
5880 flash programming as it is faster than the @option{str9xpec} driver.
5882 Direct programming @option{str9xpec} using the flash controller. This is an
5883 ISC compilant (IEEE 1532) tap connected in series with the str9 core. The str9
5884 core does not need to be running to program using this flash driver. Typical use
5885 for this driver is locking/unlocking the target and programming the option bytes.
5888 Before we run any commands using the @option{str9xpec} driver we must first disable
5889 the str9 core. This example assumes the @option{str9xpec} driver has been
5890 configured for flash bank 0.
5892 # assert srst, we do not want core running
5893 # while accessing str9xpec flash driver
5895 # turn off target polling
5898 str9xpec enable_turbo 0
5900 str9xpec options_read 0
5901 # re-enable str9 core
5902 str9xpec disable_turbo 0
5906 The above example will read the str9 option bytes.
5907 When performing a unlock remember that you will not be able to halt the str9 - it
5908 has been locked. Halting the core is not required for the @option{str9xpec} driver
5909 as mentioned above, just issue the commands above manually or from a telnet prompt.
5911 Several str9xpec-specific commands are defined:
5913 @deffn Command {str9xpec disable_turbo} num
5914 Restore the str9 into JTAG chain.
5917 @deffn Command {str9xpec enable_turbo} num
5918 Enable turbo mode, will simply remove the str9 from the chain and talk
5919 directly to the embedded flash controller.
5922 @deffn Command {str9xpec lock} num
5923 Lock str9 device. The str9 will only respond to an unlock command that will
5927 @deffn Command {str9xpec part_id} num
5928 Prints the part identifier for bank @var{num}.
5931 @deffn Command {str9xpec options_cmap} num (@option{bank0}|@option{bank1})
5932 Configure str9 boot bank.
5935 @deffn Command {str9xpec options_lvdsel} num (@option{vdd}|@option{vdd_vddq})
5936 Configure str9 lvd source.
5939 @deffn Command {str9xpec options_lvdthd} num (@option{2.4v}|@option{2.7v})
5940 Configure str9 lvd threshold.
5943 @deffn Command {str9xpec options_lvdwarn} bank (@option{vdd}|@option{vdd_vddq})
5944 Configure str9 lvd reset warning source.
5947 @deffn Command {str9xpec options_read} num
5948 Read str9 option bytes.
5951 @deffn Command {str9xpec options_write} num
5952 Write str9 option bytes.
5955 @deffn Command {str9xpec unlock} num
5961 @deffn {Flash Driver} tms470
5962 Most members of the TMS470 microcontroller family from Texas Instruments
5963 include internal flash and use ARM7TDMI cores.
5964 This driver doesn't require the chip and bus width to be specified.
5966 Some tms470-specific commands are defined:
5968 @deffn Command {tms470 flash_keyset} key0 key1 key2 key3
5969 Saves programming keys in a register, to enable flash erase and write commands.
5972 @deffn Command {tms470 osc_mhz} clock_mhz
5973 Reports the clock speed, which is used to calculate timings.
5976 @deffn Command {tms470 plldis} (0|1)
5977 Disables (@var{1}) or enables (@var{0}) use of the PLL to speed up
5982 @deffn {Flash Driver} xmc1xxx
5983 All members of the XMC1xxx microcontroller family from Infineon.
5984 This driver does not require the chip and bus width to be specified.
5987 @deffn {Flash Driver} xmc4xxx
5988 All members of the XMC4xxx microcontroller family from Infineon.
5989 This driver does not require the chip and bus width to be specified.
5991 Some xmc4xxx-specific commands are defined:
5993 @deffn Command {xmc4xxx flash_password} bank_id passwd1 passwd2
5994 Saves flash protection passwords which are used to lock the user flash
5997 @deffn Command {xmc4xxx flash_unprotect} bank_id user_level[0-1]
5998 Removes Flash write protection from the selected user bank
6003 @section NAND Flash Commands
6006 Compared to NOR or SPI flash, NAND devices are inexpensive
6007 and high density. Today's NAND chips, and multi-chip modules,
6008 commonly hold multiple GigaBytes of data.
6010 NAND chips consist of a number of ``erase blocks'' of a given
6011 size (such as 128 KBytes), each of which is divided into a
6012 number of pages (of perhaps 512 or 2048 bytes each). Each
6013 page of a NAND flash has an ``out of band'' (OOB) area to hold
6014 Error Correcting Code (ECC) and other metadata, usually 16 bytes
6015 of OOB for every 512 bytes of page data.
6017 One key characteristic of NAND flash is that its error rate
6018 is higher than that of NOR flash. In normal operation, that
6019 ECC is used to correct and detect errors. However, NAND
6020 blocks can also wear out and become unusable; those blocks
6021 are then marked "bad". NAND chips are even shipped from the
6022 manufacturer with a few bad blocks. The highest density chips
6023 use a technology (MLC) that wears out more quickly, so ECC
6024 support is increasingly important as a way to detect blocks
6025 that have begun to fail, and help to preserve data integrity
6026 with techniques such as wear leveling.
6028 Software is used to manage the ECC. Some controllers don't
6029 support ECC directly; in those cases, software ECC is used.
6030 Other controllers speed up the ECC calculations with hardware.
6031 Single-bit error correction hardware is routine. Controllers
6032 geared for newer MLC chips may correct 4 or more errors for
6033 every 512 bytes of data.
6035 You will need to make sure that any data you write using
6036 OpenOCD includes the apppropriate kind of ECC. For example,
6037 that may mean passing the @code{oob_softecc} flag when
6038 writing NAND data, or ensuring that the correct hardware
6041 The basic steps for using NAND devices include:
6043 @item Declare via the command @command{nand device}
6044 @* Do this in a board-specific configuration file,
6045 passing parameters as needed by the controller.
6046 @item Configure each device using @command{nand probe}.
6047 @* Do this only after the associated target is set up,
6048 such as in its reset-init script or in procures defined
6049 to access that device.
6050 @item Operate on the flash via @command{nand subcommand}
6051 @* Often commands to manipulate the flash are typed by a human, or run
6052 via a script in some automated way. Common task include writing a
6053 boot loader, operating system, or other data needed to initialize or
6057 @b{NOTE:} At the time this text was written, the largest NAND
6058 flash fully supported by OpenOCD is 2 GiBytes (16 GiBits).
6059 This is because the variables used to hold offsets and lengths
6060 are only 32 bits wide.
6061 (Larger chips may work in some cases, unless an offset or length
6062 is larger than 0xffffffff, the largest 32-bit unsigned integer.)
6063 Some larger devices will work, since they are actually multi-chip
6064 modules with two smaller chips and individual chipselect lines.
6066 @anchor{nandconfiguration}
6067 @subsection NAND Configuration Commands
6068 @cindex NAND configuration
6070 NAND chips must be declared in configuration scripts,
6071 plus some additional configuration that's done after
6072 OpenOCD has initialized.
6074 @deffn {Config Command} {nand device} name driver target [configparams...]
6075 Declares a NAND device, which can be read and written to
6076 after it has been configured through @command{nand probe}.
6077 In OpenOCD, devices are single chips; this is unlike some
6078 operating systems, which may manage multiple chips as if
6079 they were a single (larger) device.
6080 In some cases, configuring a device will activate extra
6081 commands; see the controller-specific documentation.
6083 @b{NOTE:} This command is not available after OpenOCD
6084 initialization has completed. Use it in board specific
6085 configuration files, not interactively.
6088 @item @var{name} ... may be used to reference the NAND bank
6089 in most other NAND commands. A number is also available.
6090 @item @var{driver} ... identifies the NAND controller driver
6091 associated with the NAND device being declared.
6092 @xref{nanddriverlist,,NAND Driver List}.
6093 @item @var{target} ... names the target used when issuing
6094 commands to the NAND controller.
6095 @comment Actually, it's currently a controller-specific parameter...
6096 @item @var{configparams} ... controllers may support, or require,
6097 additional parameters. See the controller-specific documentation
6098 for more information.
6102 @deffn Command {nand list}
6103 Prints a summary of each device declared
6104 using @command{nand device}, numbered from zero.
6105 Note that un-probed devices show no details.
6108 #0: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
6109 blocksize: 131072, blocks: 8192
6110 #1: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
6111 blocksize: 131072, blocks: 8192
6116 @deffn Command {nand probe} num
6117 Probes the specified device to determine key characteristics
6118 like its page and block sizes, and how many blocks it has.
6119 The @var{num} parameter is the value shown by @command{nand list}.
6120 You must (successfully) probe a device before you can use
6121 it with most other NAND commands.
6124 @subsection Erasing, Reading, Writing to NAND Flash
6126 @deffn Command {nand dump} num filename offset length [oob_option]
6127 @cindex NAND reading
6128 Reads binary data from the NAND device and writes it to the file,
6129 starting at the specified offset.
6130 The @var{num} parameter is the value shown by @command{nand list}.
6132 Use a complete path name for @var{filename}, so you don't depend
6133 on the directory used to start the OpenOCD server.
6135 The @var{offset} and @var{length} must be exact multiples of the
6136 device's page size. They describe a data region; the OOB data
6137 associated with each such page may also be accessed.
6139 @b{NOTE:} At the time this text was written, no error correction
6140 was done on the data that's read, unless raw access was disabled
6141 and the underlying NAND controller driver had a @code{read_page}
6142 method which handled that error correction.
6144 By default, only page data is saved to the specified file.
6145 Use an @var{oob_option} parameter to save OOB data:
6147 @item no oob_* parameter
6148 @*Output file holds only page data; OOB is discarded.
6149 @item @code{oob_raw}
6150 @*Output file interleaves page data and OOB data;
6151 the file will be longer than "length" by the size of the
6152 spare areas associated with each data page.
6153 Note that this kind of "raw" access is different from
6154 what's implied by @command{nand raw_access}, which just
6155 controls whether a hardware-aware access method is used.
6156 @item @code{oob_only}
6157 @*Output file has only raw OOB data, and will
6158 be smaller than "length" since it will contain only the
6159 spare areas associated with each data page.
6163 @deffn Command {nand erase} num [offset length]
6164 @cindex NAND erasing
6165 @cindex NAND programming
6166 Erases blocks on the specified NAND device, starting at the
6167 specified @var{offset} and continuing for @var{length} bytes.
6168 Both of those values must be exact multiples of the device's
6169 block size, and the region they specify must fit entirely in the chip.
6170 If those parameters are not specified,
6171 the whole NAND chip will be erased.
6172 The @var{num} parameter is the value shown by @command{nand list}.
6174 @b{NOTE:} This command will try to erase bad blocks, when told
6175 to do so, which will probably invalidate the manufacturer's bad
6177 For the remainder of the current server session, @command{nand info}
6178 will still report that the block ``is'' bad.
6181 @deffn Command {nand write} num filename offset [option...]
6182 @cindex NAND writing
6183 @cindex NAND programming
6184 Writes binary data from the file into the specified NAND device,
6185 starting at the specified offset. Those pages should already
6186 have been erased; you can't change zero bits to one bits.
6187 The @var{num} parameter is the value shown by @command{nand list}.
6189 Use a complete path name for @var{filename}, so you don't depend
6190 on the directory used to start the OpenOCD server.
6192 The @var{offset} must be an exact multiple of the device's page size.
6193 All data in the file will be written, assuming it doesn't run
6194 past the end of the device.
6195 Only full pages are written, and any extra space in the last
6196 page will be filled with 0xff bytes. (That includes OOB data,
6197 if that's being written.)
6199 @b{NOTE:} At the time this text was written, bad blocks are
6200 ignored. That is, this routine will not skip bad blocks,
6201 but will instead try to write them. This can cause problems.
6203 Provide at most one @var{option} parameter. With some
6204 NAND drivers, the meanings of these parameters may change
6205 if @command{nand raw_access} was used to disable hardware ECC.
6207 @item no oob_* parameter
6208 @*File has only page data, which is written.
6209 If raw acccess is in use, the OOB area will not be written.
6210 Otherwise, if the underlying NAND controller driver has
6211 a @code{write_page} routine, that routine may write the OOB
6212 with hardware-computed ECC data.
6213 @item @code{oob_only}
6214 @*File has only raw OOB data, which is written to the OOB area.
6215 Each page's data area stays untouched. @i{This can be a dangerous
6216 option}, since it can invalidate the ECC data.
6217 You may need to force raw access to use this mode.
6218 @item @code{oob_raw}
6219 @*File interleaves data and OOB data, both of which are written
6220 If raw access is enabled, the data is written first, then the
6222 Otherwise, if the underlying NAND controller driver has
6223 a @code{write_page} routine, that routine may modify the OOB
6224 before it's written, to include hardware-computed ECC data.
6225 @item @code{oob_softecc}
6226 @*File has only page data, which is written.
6227 The OOB area is filled with 0xff, except for a standard 1-bit
6228 software ECC code stored in conventional locations.
6229 You might need to force raw access to use this mode, to prevent
6230 the underlying driver from applying hardware ECC.
6231 @item @code{oob_softecc_kw}
6232 @*File has only page data, which is written.
6233 The OOB area is filled with 0xff, except for a 4-bit software ECC
6234 specific to the boot ROM in Marvell Kirkwood SoCs.
6235 You might need to force raw access to use this mode, to prevent
6236 the underlying driver from applying hardware ECC.
6240 @deffn Command {nand verify} num filename offset [option...]
6241 @cindex NAND verification
6242 @cindex NAND programming
6243 Verify the binary data in the file has been programmed to the
6244 specified NAND device, starting at the specified offset.
6245 The @var{num} parameter is the value shown by @command{nand list}.
6247 Use a complete path name for @var{filename}, so you don't depend
6248 on the directory used to start the OpenOCD server.
6250 The @var{offset} must be an exact multiple of the device's page size.
6251 All data in the file will be read and compared to the contents of the
6252 flash, assuming it doesn't run past the end of the device.
6253 As with @command{nand write}, only full pages are verified, so any extra
6254 space in the last page will be filled with 0xff bytes.
6256 The same @var{options} accepted by @command{nand write},
6257 and the file will be processed similarly to produce the buffers that
6258 can be compared against the contents produced from @command{nand dump}.
6260 @b{NOTE:} This will not work when the underlying NAND controller
6261 driver's @code{write_page} routine must update the OOB with a
6262 hardward-computed ECC before the data is written. This limitation may
6263 be removed in a future release.
6266 @subsection Other NAND commands
6267 @cindex NAND other commands
6269 @deffn Command {nand check_bad_blocks} num [offset length]
6270 Checks for manufacturer bad block markers on the specified NAND
6271 device. If no parameters are provided, checks the whole
6272 device; otherwise, starts at the specified @var{offset} and
6273 continues for @var{length} bytes.
6274 Both of those values must be exact multiples of the device's
6275 block size, and the region they specify must fit entirely in the chip.
6276 The @var{num} parameter is the value shown by @command{nand list}.
6278 @b{NOTE:} Before using this command you should force raw access
6279 with @command{nand raw_access enable} to ensure that the underlying
6280 driver will not try to apply hardware ECC.
6283 @deffn Command {nand info} num
6284 The @var{num} parameter is the value shown by @command{nand list}.
6285 This prints the one-line summary from "nand list", plus for
6286 devices which have been probed this also prints any known
6287 status for each block.
6290 @deffn Command {nand raw_access} num (@option{enable}|@option{disable})
6291 Sets or clears an flag affecting how page I/O is done.
6292 The @var{num} parameter is the value shown by @command{nand list}.
6294 This flag is cleared (disabled) by default, but changing that
6295 value won't affect all NAND devices. The key factor is whether
6296 the underlying driver provides @code{read_page} or @code{write_page}
6297 methods. If it doesn't provide those methods, the setting of
6298 this flag is irrelevant; all access is effectively ``raw''.
6300 When those methods exist, they are normally used when reading
6301 data (@command{nand dump} or reading bad block markers) or
6302 writing it (@command{nand write}). However, enabling
6303 raw access (setting the flag) prevents use of those methods,
6304 bypassing hardware ECC logic.
6305 @i{This can be a dangerous option}, since writing blocks
6306 with the wrong ECC data can cause them to be marked as bad.
6309 @anchor{nanddriverlist}
6310 @subsection NAND Driver List
6311 As noted above, the @command{nand device} command allows
6312 driver-specific options and behaviors.
6313 Some controllers also activate controller-specific commands.
6315 @deffn {NAND Driver} at91sam9
6316 This driver handles the NAND controllers found on AT91SAM9 family chips from
6317 Atmel. It takes two extra parameters: address of the NAND chip;
6318 address of the ECC controller.
6320 nand device $NANDFLASH at91sam9 $CHIPNAME 0x40000000 0xfffffe800
6322 AT91SAM9 chips support single-bit ECC hardware. The @code{write_page} and
6323 @code{read_page} methods are used to utilize the ECC hardware unless they are
6324 disabled by using the @command{nand raw_access} command. There are four
6325 additional commands that are needed to fully configure the AT91SAM9 NAND
6326 controller. Two are optional; most boards use the same wiring for ALE/CLE:
6327 @deffn Command {at91sam9 cle} num addr_line
6328 Configure the address line used for latching commands. The @var{num}
6329 parameter is the value shown by @command{nand list}.
6331 @deffn Command {at91sam9 ale} num addr_line
6332 Configure the address line used for latching addresses. The @var{num}
6333 parameter is the value shown by @command{nand list}.
6336 For the next two commands, it is assumed that the pins have already been
6337 properly configured for input or output.
6338 @deffn Command {at91sam9 rdy_busy} num pio_base_addr pin
6339 Configure the RDY/nBUSY input from the NAND device. The @var{num}
6340 parameter is the value shown by @command{nand list}. @var{pio_base_addr}
6341 is the base address of the PIO controller and @var{pin} is the pin number.
6343 @deffn Command {at91sam9 ce} num pio_base_addr pin
6344 Configure the chip enable input to the NAND device. The @var{num}
6345 parameter is the value shown by @command{nand list}. @var{pio_base_addr}
6346 is the base address of the PIO controller and @var{pin} is the pin number.
6350 @deffn {NAND Driver} davinci
6351 This driver handles the NAND controllers found on DaVinci family
6352 chips from Texas Instruments.
6353 It takes three extra parameters:
6354 address of the NAND chip;
6355 hardware ECC mode to use (@option{hwecc1},
6356 @option{hwecc4}, @option{hwecc4_infix});
6357 address of the AEMIF controller on this processor.
6359 nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000
6361 All DaVinci processors support the single-bit ECC hardware,
6362 and newer ones also support the four-bit ECC hardware.
6363 The @code{write_page} and @code{read_page} methods are used
6364 to implement those ECC modes, unless they are disabled using
6365 the @command{nand raw_access} command.
6368 @deffn {NAND Driver} lpc3180
6369 These controllers require an extra @command{nand device}
6370 parameter: the clock rate used by the controller.
6371 @deffn Command {lpc3180 select} num [mlc|slc]
6372 Configures use of the MLC or SLC controller mode.
6373 MLC implies use of hardware ECC.
6374 The @var{num} parameter is the value shown by @command{nand list}.
6377 At this writing, this driver includes @code{write_page}
6378 and @code{read_page} methods. Using @command{nand raw_access}
6379 to disable those methods will prevent use of hardware ECC
6380 in the MLC controller mode, but won't change SLC behavior.
6382 @comment current lpc3180 code won't issue 5-byte address cycles
6384 @deffn {NAND Driver} mx3
6385 This driver handles the NAND controller in i.MX31. The mxc driver
6386 should work for this chip aswell.
6389 @deffn {NAND Driver} mxc
6390 This driver handles the NAND controller found in Freescale i.MX
6391 chips. It has support for v1 (i.MX27 and i.MX31) and v2 (i.MX35).
6392 The driver takes 3 extra arguments, chip (@option{mx27},
6393 @option{mx31}, @option{mx35}), ecc (@option{noecc}, @option{hwecc})
6394 and optionally if bad block information should be swapped between
6395 main area and spare area (@option{biswap}), defaults to off.
6397 nand device mx35.nand mxc imx35.cpu mx35 hwecc biswap
6399 @deffn Command {mxc biswap} bank_num [enable|disable]
6400 Turns on/off bad block information swaping from main area,
6401 without parameter query status.
6405 @deffn {NAND Driver} orion
6406 These controllers require an extra @command{nand device}
6407 parameter: the address of the controller.
6409 nand device orion 0xd8000000
6411 These controllers don't define any specialized commands.
6412 At this writing, their drivers don't include @code{write_page}
6413 or @code{read_page} methods, so @command{nand raw_access} won't
6414 change any behavior.
6417 @deffn {NAND Driver} s3c2410
6418 @deffnx {NAND Driver} s3c2412
6419 @deffnx {NAND Driver} s3c2440
6420 @deffnx {NAND Driver} s3c2443
6421 @deffnx {NAND Driver} s3c6400
6422 These S3C family controllers don't have any special
6423 @command{nand device} options, and don't define any
6424 specialized commands.
6425 At this writing, their drivers don't include @code{write_page}
6426 or @code{read_page} methods, so @command{nand raw_access} won't
6427 change any behavior.
6432 @subsection mFlash Configuration
6433 @cindex mFlash Configuration
6435 @deffn {Config Command} {mflash bank} soc base RST_pin target
6436 Configures a mflash for @var{soc} host bank at
6438 The pin number format depends on the host GPIO naming convention.
6439 Currently, the mflash driver supports s3c2440 and pxa270.
6441 Example for s3c2440 mflash where @var{RST pin} is GPIO B1:
6444 mflash bank $_FLASHNAME s3c2440 0x10000000 1b 0
6447 Example for pxa270 mflash where @var{RST pin} is GPIO 43:
6450 mflash bank $_FLASHNAME pxa270 0x08000000 43 0
6454 @subsection mFlash commands
6455 @cindex mFlash commands
6457 @deffn Command {mflash config pll} frequency
6458 Configure mflash PLL.
6459 The @var{frequency} is the mflash input frequency, in Hz.
6460 Issuing this command will erase mflash's whole internal nand and write new pll.
6461 After this command, mflash needs power-on-reset for normal operation.
6462 If pll was newly configured, storage and boot(optional) info also need to be update.
6465 @deffn Command {mflash config boot}
6466 Configure bootable option.
6467 If bootable option is set, mflash offer the first 8 sectors
6471 @deffn Command {mflash config storage}
6472 Configure storage information.
6473 For the normal storage operation, this information must be
6477 @deffn Command {mflash dump} num filename offset size
6478 Dump @var{size} bytes, starting at @var{offset} bytes from the
6479 beginning of the bank @var{num}, to the file named @var{filename}.
6482 @deffn Command {mflash probe}
6486 @deffn Command {mflash write} num filename offset
6487 Write the binary file @var{filename} to mflash bank @var{num}, starting at
6488 @var{offset} bytes from the beginning of the bank.
6491 @node Flash Programming
6492 @chapter Flash Programming
6494 OpenOCD implements numerous ways to program the target flash, whether internal or external.
6495 Programming can be acheived by either using GDB @ref{programmingusinggdb,,Programming using GDB},
6496 or using the cmds given in @ref{flashprogrammingcommands,,Flash Programming Commands}.
6498 @*To simplify using the flash cmds directly a jimtcl script is available that handles the programming and verify stage.
6499 OpenOCD will program/verify/reset the target and optionally shutdown.
6501 The script is executed as follows and by default the following actions will be peformed.
6503 @item 'init' is executed.
6504 @item 'reset init' is called to reset and halt the target, any 'reset init' scripts are executed.
6505 @item @code{flash write_image} is called to erase and write any flash using the filename given.
6506 @item @code{verify_image} is called if @option{verify} parameter is given.
6507 @item @code{reset run} is called if @option{reset} parameter is given.
6508 @item OpenOCD is shutdown if @option{exit} parameter is given.
6511 An example of usage is given below. @xref{program}.
6514 # program and verify using elf/hex/s19. verify and reset
6515 # are optional parameters
6516 openocd -f board/stm32f3discovery.cfg \
6517 -c "program filename.elf verify reset exit"
6519 # binary files need the flash address passing
6520 openocd -f board/stm32f3discovery.cfg \
6521 -c "program filename.bin exit 0x08000000"
6524 @node PLD/FPGA Commands
6525 @chapter PLD/FPGA Commands
6529 Programmable Logic Devices (PLDs) and the more flexible
6530 Field Programmable Gate Arrays (FPGAs) are both types of programmable hardware.
6531 OpenOCD can support programming them.
6532 Although PLDs are generally restrictive (cells are less functional, and
6533 there are no special purpose cells for memory or computational tasks),
6534 they share the same OpenOCD infrastructure.
6535 Accordingly, both are called PLDs here.
6537 @section PLD/FPGA Configuration and Commands
6539 As it does for JTAG TAPs, debug targets, and flash chips (both NOR and NAND),
6540 OpenOCD maintains a list of PLDs available for use in various commands.
6541 Also, each such PLD requires a driver.
6543 They are referenced by the number shown by the @command{pld devices} command,
6544 and new PLDs are defined by @command{pld device driver_name}.
6546 @deffn {Config Command} {pld device} driver_name tap_name [driver_options]
6547 Defines a new PLD device, supported by driver @var{driver_name},
6548 using the TAP named @var{tap_name}.
6549 The driver may make use of any @var{driver_options} to configure its
6553 @deffn {Command} {pld devices}
6554 Lists the PLDs and their numbers.
6557 @deffn {Command} {pld load} num filename
6558 Loads the file @file{filename} into the PLD identified by @var{num}.
6559 The file format must be inferred by the driver.
6562 @section PLD/FPGA Drivers, Options, and Commands
6564 Drivers may support PLD-specific options to the @command{pld device}
6565 definition command, and may also define commands usable only with
6566 that particular type of PLD.
6568 @deffn {FPGA Driver} virtex2 [no_jstart]
6569 Virtex-II is a family of FPGAs sold by Xilinx.
6570 It supports the IEEE 1532 standard for In-System Configuration (ISC).
6572 If @var{no_jstart} is non-zero, the JSTART instruction is not used after
6573 loading the bitstream. While required for Series2, Series3, and Series6, it
6574 breaks bitstream loading on Series7.
6576 @deffn {Command} {virtex2 read_stat} num
6577 Reads and displays the Virtex-II status register (STAT)
6582 @node General Commands
6583 @chapter General Commands
6586 The commands documented in this chapter here are common commands that
6587 you, as a human, may want to type and see the output of. Configuration type
6588 commands are documented elsewhere.
6592 @item @b{Source Of Commands}
6593 @* OpenOCD commands can occur in a configuration script (discussed
6594 elsewhere) or typed manually by a human or supplied programatically,
6595 or via one of several TCP/IP Ports.
6597 @item @b{From the human}
6598 @* A human should interact with the telnet interface (default port: 4444)
6599 or via GDB (default port 3333).
6601 To issue commands from within a GDB session, use the @option{monitor}
6602 command, e.g. use @option{monitor poll} to issue the @option{poll}
6603 command. All output is relayed through the GDB session.
6605 @item @b{Machine Interface}
6606 The Tcl interface's intent is to be a machine interface. The default Tcl
6611 @section Daemon Commands
6613 @deffn {Command} exit
6614 Exits the current telnet session.
6617 @deffn {Command} help [string]
6618 With no parameters, prints help text for all commands.
6619 Otherwise, prints each helptext containing @var{string}.
6620 Not every command provides helptext.
6622 Configuration commands, and commands valid at any time, are
6623 explicitly noted in parenthesis.
6624 In most cases, no such restriction is listed; this indicates commands
6625 which are only available after the configuration stage has completed.
6628 @deffn Command sleep msec [@option{busy}]
6629 Wait for at least @var{msec} milliseconds before resuming.
6630 If @option{busy} is passed, busy-wait instead of sleeping.
6631 (This option is strongly discouraged.)
6632 Useful in connection with script files
6633 (@command{script} command and @command{target_name} configuration).
6636 @deffn Command shutdown [@option{error}]
6637 Close the OpenOCD daemon, disconnecting all clients (GDB, telnet,
6638 other). If option @option{error} is used, OpenOCD will return a
6639 non-zero exit code to the parent process.
6643 @deffn Command debug_level [n]
6644 @cindex message level
6645 Display debug level.
6646 If @var{n} (from 0..3) is provided, then set it to that level.
6647 This affects the kind of messages sent to the server log.
6648 Level 0 is error messages only;
6649 level 1 adds warnings;
6650 level 2 adds informational messages;
6651 and level 3 adds debugging messages.
6652 The default is level 2, but that can be overridden on
6653 the command line along with the location of that log
6654 file (which is normally the server's standard output).
6658 @deffn Command echo [-n] message
6659 Logs a message at "user" priority.
6660 Output @var{message} to stdout.
6661 Option "-n" suppresses trailing newline.
6663 echo "Downloading kernel -- please wait"
6667 @deffn Command log_output [filename]
6668 Redirect logging to @var{filename};
6669 the initial log output channel is stderr.
6672 @deffn Command add_script_search_dir [directory]
6673 Add @var{directory} to the file/script search path.
6676 @anchor{targetstatehandling}
6677 @section Target State handling
6680 @cindex target initialization
6682 In this section ``target'' refers to a CPU configured as
6683 shown earlier (@pxref{CPU Configuration}).
6684 These commands, like many, implicitly refer to
6685 a current target which is used to perform the
6686 various operations. The current target may be changed
6687 by using @command{targets} command with the name of the
6688 target which should become current.
6690 @deffn Command reg [(number|name) [(value|'force')]]
6691 Access a single register by @var{number} or by its @var{name}.
6692 The target must generally be halted before access to CPU core
6693 registers is allowed. Depending on the hardware, some other
6694 registers may be accessible while the target is running.
6696 @emph{With no arguments}:
6697 list all available registers for the current target,
6698 showing number, name, size, value, and cache status.
6699 For valid entries, a value is shown; valid entries
6700 which are also dirty (and will be written back later)
6701 are flagged as such.
6703 @emph{With number/name}: display that register's value.
6704 Use @var{force} argument to read directly from the target,
6705 bypassing any internal cache.
6707 @emph{With both number/name and value}: set register's value.
6708 Writes may be held in a writeback cache internal to OpenOCD,
6709 so that setting the value marks the register as dirty instead
6710 of immediately flushing that value. Resuming CPU execution
6711 (including by single stepping) or otherwise activating the
6712 relevant module will flush such values.
6714 Cores may have surprisingly many registers in their
6715 Debug and trace infrastructure:
6720 (0) r0 (/32): 0x0000D3C2 (dirty)
6721 (1) r1 (/32): 0xFD61F31C
6724 (164) ETM_contextid_comparator_mask (/32)
6729 @deffn Command halt [ms]
6730 @deffnx Command wait_halt [ms]
6731 The @command{halt} command first sends a halt request to the target,
6732 which @command{wait_halt} doesn't.
6733 Otherwise these behave the same: wait up to @var{ms} milliseconds,
6734 or 5 seconds if there is no parameter, for the target to halt
6735 (and enter debug mode).
6736 Using 0 as the @var{ms} parameter prevents OpenOCD from waiting.
6739 On ARM cores, software using the @emph{wait for interrupt} operation
6740 often blocks the JTAG access needed by a @command{halt} command.
6741 This is because that operation also puts the core into a low
6742 power mode by gating the core clock;
6743 but the core clock is needed to detect JTAG clock transitions.
6745 One partial workaround uses adaptive clocking: when the core is
6746 interrupted the operation completes, then JTAG clocks are accepted
6747 at least until the interrupt handler completes.
6748 However, this workaround is often unusable since the processor, board,
6749 and JTAG adapter must all support adaptive JTAG clocking.
6750 Also, it can't work until an interrupt is issued.
6752 A more complete workaround is to not use that operation while you
6753 work with a JTAG debugger.
6754 Tasking environments generaly have idle loops where the body is the
6755 @emph{wait for interrupt} operation.
6756 (On older cores, it is a coprocessor action;
6757 newer cores have a @option{wfi} instruction.)
6758 Such loops can just remove that operation, at the cost of higher
6759 power consumption (because the CPU is needlessly clocked).
6764 @deffn Command resume [address]
6765 Resume the target at its current code position,
6766 or the optional @var{address} if it is provided.
6767 OpenOCD will wait 5 seconds for the target to resume.
6770 @deffn Command step [address]
6771 Single-step the target at its current code position,
6772 or the optional @var{address} if it is provided.
6775 @anchor{resetcommand}
6776 @deffn Command reset
6777 @deffnx Command {reset run}
6778 @deffnx Command {reset halt}
6779 @deffnx Command {reset init}
6780 Perform as hard a reset as possible, using SRST if possible.
6781 @emph{All defined targets will be reset, and target
6782 events will fire during the reset sequence.}
6784 The optional parameter specifies what should
6785 happen after the reset.
6786 If there is no parameter, a @command{reset run} is executed.
6787 The other options will not work on all systems.
6788 @xref{Reset Configuration}.
6791 @item @b{run} Let the target run
6792 @item @b{halt} Immediately halt the target
6793 @item @b{init} Immediately halt the target, and execute the reset-init script
6797 @deffn Command soft_reset_halt
6798 Requesting target halt and executing a soft reset. This is often used
6799 when a target cannot be reset and halted. The target, after reset is
6800 released begins to execute code. OpenOCD attempts to stop the CPU and
6801 then sets the program counter back to the reset vector. Unfortunately
6802 the code that was executed may have left the hardware in an unknown
6806 @section I/O Utilities
6808 These commands are available when
6809 OpenOCD is built with @option{--enable-ioutil}.
6810 They are mainly useful on embedded targets,
6812 Hosts with operating systems have complementary tools.
6814 @emph{Note:} there are several more such commands.
6816 @deffn Command append_file filename [string]*
6817 Appends the @var{string} parameters to
6818 the text file @file{filename}.
6819 Each string except the last one is followed by one space.
6820 The last string is followed by a newline.
6823 @deffn Command cat filename
6824 Reads and displays the text file @file{filename}.
6827 @deffn Command cp src_filename dest_filename
6828 Copies contents from the file @file{src_filename}
6829 into @file{dest_filename}.
6833 @emph{No description provided.}
6837 @emph{No description provided.}
6841 @emph{No description provided.}
6844 @deffn Command meminfo
6845 Display available RAM memory on OpenOCD host.
6846 Used in OpenOCD regression testing scripts.
6850 @emph{No description provided.}
6854 @emph{No description provided.}
6857 @deffn Command rm filename
6858 @c "rm" has both normal and Jim-level versions??
6859 Unlinks the file @file{filename}.
6862 @deffn Command trunc filename
6863 Removes all data in the file @file{filename}.
6866 @anchor{memoryaccess}
6867 @section Memory access commands
6868 @cindex memory access
6870 These commands allow accesses of a specific size to the memory
6871 system. Often these are used to configure the current target in some
6872 special way. For example - one may need to write certain values to the
6873 SDRAM controller to enable SDRAM.
6876 @item Use the @command{targets} (plural) command
6877 to change the current target.
6878 @item In system level scripts these commands are deprecated.
6879 Please use their TARGET object siblings to avoid making assumptions
6880 about what TAP is the current target, or about MMU configuration.
6883 @deffn Command mdw [phys] addr [count]
6884 @deffnx Command mdh [phys] addr [count]
6885 @deffnx Command mdb [phys] addr [count]
6886 Display contents of address @var{addr}, as
6887 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
6888 or 8-bit bytes (@command{mdb}).
6889 When the current target has an MMU which is present and active,
6890 @var{addr} is interpreted as a virtual address.
6891 Otherwise, or if the optional @var{phys} flag is specified,
6892 @var{addr} is interpreted as a physical address.
6893 If @var{count} is specified, displays that many units.
6894 (If you want to manipulate the data instead of displaying it,
6895 see the @code{mem2array} primitives.)
6898 @deffn Command mww [phys] addr word
6899 @deffnx Command mwh [phys] addr halfword
6900 @deffnx Command mwb [phys] addr byte
6901 Writes the specified @var{word} (32 bits),
6902 @var{halfword} (16 bits), or @var{byte} (8-bit) value,
6903 at the specified address @var{addr}.
6904 When the current target has an MMU which is present and active,
6905 @var{addr} is interpreted as a virtual address.
6906 Otherwise, or if the optional @var{phys} flag is specified,
6907 @var{addr} is interpreted as a physical address.
6910 @anchor{imageaccess}
6911 @section Image loading commands
6912 @cindex image loading
6913 @cindex image dumping
6915 @deffn Command {dump_image} filename address size
6916 Dump @var{size} bytes of target memory starting at @var{address} to the
6917 binary file named @var{filename}.
6920 @deffn Command {fast_load}
6921 Loads an image stored in memory by @command{fast_load_image} to the
6922 current target. Must be preceeded by fast_load_image.
6925 @deffn Command {fast_load_image} filename address [@option{bin}|@option{ihex}|@option{elf}|@option{s19}]
6926 Normally you should be using @command{load_image} or GDB load. However, for
6927 testing purposes or when I/O overhead is significant(OpenOCD running on an embedded
6928 host), storing the image in memory and uploading the image to the target
6929 can be a way to upload e.g. multiple debug sessions when the binary does not change.
6930 Arguments are the same as @command{load_image}, but the image is stored in OpenOCD host
6931 memory, i.e. does not affect target. This approach is also useful when profiling
6932 target programming performance as I/O and target programming can easily be profiled
6936 @deffn Command {load_image} filename address [[@option{bin}|@option{ihex}|@option{elf}|@option{s19}] @option{min_addr} @option{max_length}]
6937 Load image from file @var{filename} to target memory offset by @var{address} from its load address.
6938 The file format may optionally be specified
6939 (@option{bin}, @option{ihex}, @option{elf}, or @option{s19}).
6940 In addition the following arguments may be specifed:
6941 @var{min_addr} - ignore data below @var{min_addr} (this is w.r.t. to the target's load address + @var{address})
6942 @var{max_length} - maximum number of bytes to load.
6944 proc load_image_bin @{fname foffset address length @} @{
6945 # Load data from fname filename at foffset offset to
6946 # target at address. Load at most length bytes.
6947 load_image $fname [expr $address - $foffset] bin \
6953 @deffn Command {test_image} filename [address [@option{bin}|@option{ihex}|@option{elf}]]
6954 Displays image section sizes and addresses
6955 as if @var{filename} were loaded into target memory
6956 starting at @var{address} (defaults to zero).
6957 The file format may optionally be specified
6958 (@option{bin}, @option{ihex}, or @option{elf})
6961 @deffn Command {verify_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
6962 Verify @var{filename} against target memory starting at @var{address}.
6963 The file format may optionally be specified
6964 (@option{bin}, @option{ihex}, or @option{elf})
6965 This will first attempt a comparison using a CRC checksum, if this fails it will try a binary compare.
6969 @section Breakpoint and Watchpoint commands
6973 CPUs often make debug modules accessible through JTAG, with
6974 hardware support for a handful of code breakpoints and data
6976 In addition, CPUs almost always support software breakpoints.
6978 @deffn Command {bp} [address len [@option{hw}]]
6979 With no parameters, lists all active breakpoints.
6980 Else sets a breakpoint on code execution starting
6981 at @var{address} for @var{length} bytes.
6982 This is a software breakpoint, unless @option{hw} is specified
6983 in which case it will be a hardware breakpoint.
6985 (@xref{arm9vectorcatch,,arm9 vector_catch}, or @pxref{xscalevectorcatch,,xscale vector_catch},
6986 for similar mechanisms that do not consume hardware breakpoints.)
6989 @deffn Command {rbp} address
6990 Remove the breakpoint at @var{address}.
6993 @deffn Command {rwp} address
6994 Remove data watchpoint on @var{address}
6997 @deffn Command {wp} [address len [(@option{r}|@option{w}|@option{a}) [value [mask]]]]
6998 With no parameters, lists all active watchpoints.
6999 Else sets a data watchpoint on data from @var{address} for @var{length} bytes.
7000 The watch point is an "access" watchpoint unless
7001 the @option{r} or @option{w} parameter is provided,
7002 defining it as respectively a read or write watchpoint.
7003 If a @var{value} is provided, that value is used when determining if
7004 the watchpoint should trigger. The value may be first be masked
7005 using @var{mask} to mark ``don't care'' fields.
7008 @section Misc Commands
7011 @deffn Command {profile} seconds filename [start end]
7012 Profiling samples the CPU's program counter as quickly as possible,
7013 which is useful for non-intrusive stochastic profiling.
7014 Saves up to 10000 samples in @file{filename} using ``gmon.out''
7015 format. Optional @option{start} and @option{end} parameters allow to
7016 limit the address range.
7019 @deffn Command {version}
7020 Displays a string identifying the version of this OpenOCD server.
7023 @deffn Command {virt2phys} virtual_address
7024 Requests the current target to map the specified @var{virtual_address}
7025 to its corresponding physical address, and displays the result.
7028 @node Architecture and Core Commands
7029 @chapter Architecture and Core Commands
7030 @cindex Architecture Specific Commands
7031 @cindex Core Specific Commands
7033 Most CPUs have specialized JTAG operations to support debugging.
7034 OpenOCD packages most such operations in its standard command framework.
7035 Some of those operations don't fit well in that framework, so they are
7036 exposed here as architecture or implementation (core) specific commands.
7038 @anchor{armhardwaretracing}
7039 @section ARM Hardware Tracing
7044 CPUs based on ARM cores may include standard tracing interfaces,
7045 based on an ``Embedded Trace Module'' (ETM) which sends voluminous
7046 address and data bus trace records to a ``Trace Port''.
7050 Development-oriented boards will sometimes provide a high speed
7051 trace connector for collecting that data, when the particular CPU
7052 supports such an interface.
7053 (The standard connector is a 38-pin Mictor, with both JTAG
7054 and trace port support.)
7055 Those trace connectors are supported by higher end JTAG adapters
7056 and some logic analyzer modules; frequently those modules can
7057 buffer several megabytes of trace data.
7058 Configuring an ETM coupled to such an external trace port belongs
7059 in the board-specific configuration file.
7061 If the CPU doesn't provide an external interface, it probably
7062 has an ``Embedded Trace Buffer'' (ETB) on the chip, which is a
7063 dedicated SRAM. 4KBytes is one common ETB size.
7064 Configuring an ETM coupled only to an ETB belongs in the CPU-specific
7065 (target) configuration file, since it works the same on all boards.
7068 ETM support in OpenOCD doesn't seem to be widely used yet.
7071 ETM support may be buggy, and at least some @command{etm config}
7072 parameters should be detected by asking the ETM for them.
7074 ETM trigger events could also implement a kind of complex
7075 hardware breakpoint, much more powerful than the simple
7076 watchpoint hardware exported by EmbeddedICE modules.
7077 @emph{Such breakpoints can be triggered even when using the
7078 dummy trace port driver}.
7080 It seems like a GDB hookup should be possible,
7081 as well as tracing only during specific states
7082 (perhaps @emph{handling IRQ 23} or @emph{calls foo()}).
7084 There should be GUI tools to manipulate saved trace data and help
7085 analyse it in conjunction with the source code.
7086 It's unclear how much of a common interface is shared
7087 with the current XScale trace support, or should be
7088 shared with eventual Nexus-style trace module support.
7090 At this writing (November 2009) only ARM7, ARM9, and ARM11 support
7091 for ETM modules is available. The code should be able to
7092 work with some newer cores; but not all of them support
7093 this original style of JTAG access.
7096 @subsection ETM Configuration
7097 ETM setup is coupled with the trace port driver configuration.
7099 @deffn {Config Command} {etm config} target width mode clocking driver
7100 Declares the ETM associated with @var{target}, and associates it
7101 with a given trace port @var{driver}. @xref{traceportdrivers,,Trace Port Drivers}.
7103 Several of the parameters must reflect the trace port capabilities,
7104 which are a function of silicon capabilties (exposed later
7105 using @command{etm info}) and of what hardware is connected to
7106 that port (such as an external pod, or ETB).
7107 The @var{width} must be either 4, 8, or 16,
7108 except with ETMv3.0 and newer modules which may also
7109 support 1, 2, 24, 32, 48, and 64 bit widths.
7110 (With those versions, @command{etm info} also shows whether
7111 the selected port width and mode are supported.)
7113 The @var{mode} must be @option{normal}, @option{multiplexed},
7114 or @option{demultiplexed}.
7115 The @var{clocking} must be @option{half} or @option{full}.
7118 With ETMv3.0 and newer, the bits set with the @var{mode} and
7119 @var{clocking} parameters both control the mode.
7120 This modified mode does not map to the values supported by
7121 previous ETM modules, so this syntax is subject to change.
7125 You can see the ETM registers using the @command{reg} command.
7126 Not all possible registers are present in every ETM.
7127 Most of the registers are write-only, and are used to configure
7128 what CPU activities are traced.
7132 @deffn Command {etm info}
7133 Displays information about the current target's ETM.
7134 This includes resource counts from the @code{ETM_CONFIG} register,
7135 as well as silicon capabilities (except on rather old modules).
7136 from the @code{ETM_SYS_CONFIG} register.
7139 @deffn Command {etm status}
7140 Displays status of the current target's ETM and trace port driver:
7141 is the ETM idle, or is it collecting data?
7142 Did trace data overflow?
7146 @deffn Command {etm tracemode} [type context_id_bits cycle_accurate branch_output]
7147 Displays what data that ETM will collect.
7148 If arguments are provided, first configures that data.
7149 When the configuration changes, tracing is stopped
7150 and any buffered trace data is invalidated.
7153 @item @var{type} ... describing how data accesses are traced,
7154 when they pass any ViewData filtering that that was set up.
7156 @option{none} (save nothing),
7157 @option{data} (save data),
7158 @option{address} (save addresses),
7159 @option{all} (save data and addresses)
7160 @item @var{context_id_bits} ... 0, 8, 16, or 32
7161 @item @var{cycle_accurate} ... @option{enable} or @option{disable}
7162 cycle-accurate instruction tracing.
7163 Before ETMv3, enabling this causes much extra data to be recorded.
7164 @item @var{branch_output} ... @option{enable} or @option{disable}.
7165 Disable this unless you need to try reconstructing the instruction
7166 trace stream without an image of the code.
7170 @deffn Command {etm trigger_debug} (@option{enable}|@option{disable})
7171 Displays whether ETM triggering debug entry (like a breakpoint) is
7172 enabled or disabled, after optionally modifying that configuration.
7173 The default behaviour is @option{disable}.
7174 Any change takes effect after the next @command{etm start}.
7176 By using script commands to configure ETM registers, you can make the
7177 processor enter debug state automatically when certain conditions,
7178 more complex than supported by the breakpoint hardware, happen.
7181 @subsection ETM Trace Operation
7183 After setting up the ETM, you can use it to collect data.
7184 That data can be exported to files for later analysis.
7185 It can also be parsed with OpenOCD, for basic sanity checking.
7187 To configure what is being traced, you will need to write
7188 various trace registers using @command{reg ETM_*} commands.
7189 For the definitions of these registers, read ARM publication
7190 @emph{IHI 0014, ``Embedded Trace Macrocell, Architecture Specification''}.
7191 Be aware that most of the relevant registers are write-only,
7192 and that ETM resources are limited. There are only a handful
7193 of address comparators, data comparators, counters, and so on.
7195 Examples of scenarios you might arrange to trace include:
7198 @item Code flow within a function, @emph{excluding} subroutines
7199 it calls. Use address range comparators to enable tracing
7200 for instruction access within that function's body.
7201 @item Code flow within a function, @emph{including} subroutines
7202 it calls. Use the sequencer and address comparators to activate
7203 tracing on an ``entered function'' state, then deactivate it by
7204 exiting that state when the function's exit code is invoked.
7205 @item Code flow starting at the fifth invocation of a function,
7206 combining one of the above models with a counter.
7207 @item CPU data accesses to the registers for a particular device,
7208 using address range comparators and the ViewData logic.
7209 @item Such data accesses only during IRQ handling, combining the above
7210 model with sequencer triggers which on entry and exit to the IRQ handler.
7211 @item @emph{... more}
7214 At this writing, September 2009, there are no Tcl utility
7215 procedures to help set up any common tracing scenarios.
7217 @deffn Command {etm analyze}
7218 Reads trace data into memory, if it wasn't already present.
7219 Decodes and prints the data that was collected.
7222 @deffn Command {etm dump} filename
7223 Stores the captured trace data in @file{filename}.
7226 @deffn Command {etm image} filename [base_address] [type]
7227 Opens an image file.
7230 @deffn Command {etm load} filename
7231 Loads captured trace data from @file{filename}.
7234 @deffn Command {etm start}
7235 Starts trace data collection.
7238 @deffn Command {etm stop}
7239 Stops trace data collection.
7242 @anchor{traceportdrivers}
7243 @subsection Trace Port Drivers
7245 To use an ETM trace port it must be associated with a driver.
7247 @deffn {Trace Port Driver} dummy
7248 Use the @option{dummy} driver if you are configuring an ETM that's
7249 not connected to anything (on-chip ETB or off-chip trace connector).
7250 @emph{This driver lets OpenOCD talk to the ETM, but it does not expose
7251 any trace data collection.}
7252 @deffn {Config Command} {etm_dummy config} target
7253 Associates the ETM for @var{target} with a dummy driver.
7257 @deffn {Trace Port Driver} etb
7258 Use the @option{etb} driver if you are configuring an ETM
7259 to use on-chip ETB memory.
7260 @deffn {Config Command} {etb config} target etb_tap
7261 Associates the ETM for @var{target} with the ETB at @var{etb_tap}.
7262 You can see the ETB registers using the @command{reg} command.
7264 @deffn Command {etb trigger_percent} [percent]
7265 This displays, or optionally changes, ETB behavior after the
7266 ETM's configured @emph{trigger} event fires.
7267 It controls how much more trace data is saved after the (single)
7268 trace trigger becomes active.
7271 @item The default corresponds to @emph{trace around} usage,
7272 recording 50 percent data before the event and the rest
7274 @item The minimum value of @var{percent} is 2 percent,
7275 recording almost exclusively data before the trigger.
7276 Such extreme @emph{trace before} usage can help figure out
7277 what caused that event to happen.
7278 @item The maximum value of @var{percent} is 100 percent,
7279 recording data almost exclusively after the event.
7280 This extreme @emph{trace after} usage might help sort out
7281 how the event caused trouble.
7283 @c REVISIT allow "break" too -- enter debug mode.
7288 @deffn {Trace Port Driver} oocd_trace
7289 This driver isn't available unless OpenOCD was explicitly configured
7290 with the @option{--enable-oocd_trace} option. You probably don't want
7291 to configure it unless you've built the appropriate prototype hardware;
7292 it's @emph{proof-of-concept} software.
7294 Use the @option{oocd_trace} driver if you are configuring an ETM that's
7295 connected to an off-chip trace connector.
7297 @deffn {Config Command} {oocd_trace config} target tty
7298 Associates the ETM for @var{target} with a trace driver which
7299 collects data through the serial port @var{tty}.
7302 @deffn Command {oocd_trace resync}
7303 Re-synchronizes with the capture clock.
7306 @deffn Command {oocd_trace status}
7307 Reports whether the capture clock is locked or not.
7312 @section Generic ARM
7315 These commands should be available on all ARM processors.
7316 They are available in addition to other core-specific
7317 commands that may be available.
7319 @deffn Command {arm core_state} [@option{arm}|@option{thumb}]
7320 Displays the core_state, optionally changing it to process
7321 either @option{arm} or @option{thumb} instructions.
7322 The target may later be resumed in the currently set core_state.
7323 (Processors may also support the Jazelle state, but
7324 that is not currently supported in OpenOCD.)
7327 @deffn Command {arm disassemble} address [count [@option{thumb}]]
7329 Disassembles @var{count} instructions starting at @var{address}.
7330 If @var{count} is not specified, a single instruction is disassembled.
7331 If @option{thumb} is specified, or the low bit of the address is set,
7332 Thumb2 (mixed 16/32-bit) instructions are used;
7333 else ARM (32-bit) instructions are used.
7334 (Processors may also support the Jazelle state, but
7335 those instructions are not currently understood by OpenOCD.)
7337 Note that all Thumb instructions are Thumb2 instructions,
7338 so older processors (without Thumb2 support) will still
7339 see correct disassembly of Thumb code.
7340 Also, ThumbEE opcodes are the same as Thumb2,
7341 with a handful of exceptions.
7342 ThumbEE disassembly currently has no explicit support.
7345 @deffn Command {arm mcr} pX op1 CRn CRm op2 value
7346 Write @var{value} to a coprocessor @var{pX} register
7347 passing parameters @var{CRn},
7348 @var{CRm}, opcodes @var{opc1} and @var{opc2},
7349 and using the MCR instruction.
7350 (Parameter sequence matches the ARM instruction, but omits
7354 @deffn Command {arm mrc} pX coproc op1 CRn CRm op2
7355 Read a coprocessor @var{pX} register passing parameters @var{CRn},
7356 @var{CRm}, opcodes @var{opc1} and @var{opc2},
7357 and the MRC instruction.
7358 Returns the result so it can be manipulated by Jim scripts.
7359 (Parameter sequence matches the ARM instruction, but omits
7363 @deffn Command {arm reg}
7364 Display a table of all banked core registers, fetching the current value from every
7365 core mode if necessary.
7368 @deffn Command {arm semihosting} [@option{enable}|@option{disable}]
7369 @cindex ARM semihosting
7370 Display status of semihosting, after optionally changing that status.
7372 Semihosting allows for code executing on an ARM target to use the
7373 I/O facilities on the host computer i.e. the system where OpenOCD
7374 is running. The target application must be linked against a library
7375 implementing the ARM semihosting convention that forwards operation
7376 requests by using a special SVC instruction that is trapped at the
7377 Supervisor Call vector by OpenOCD.
7380 @section ARMv4 and ARMv5 Architecture
7384 The ARMv4 and ARMv5 architectures are widely used in embedded systems,
7385 and introduced core parts of the instruction set in use today.
7386 That includes the Thumb instruction set, introduced in the ARMv4T
7389 @subsection ARM7 and ARM9 specific commands
7393 These commands are specific to ARM7 and ARM9 cores, like ARM7TDMI, ARM720T,
7394 ARM9TDMI, ARM920T or ARM926EJ-S.
7395 They are available in addition to the ARM commands,
7396 and any other core-specific commands that may be available.
7398 @deffn Command {arm7_9 dbgrq} [@option{enable}|@option{disable}]
7399 Displays the value of the flag controlling use of the
7400 the EmbeddedIce DBGRQ signal to force entry into debug mode,
7401 instead of breakpoints.
7402 If a boolean parameter is provided, first assigns that flag.
7405 safe for all but ARM7TDMI-S cores (like NXP LPC).
7406 This feature is enabled by default on most ARM9 cores,
7407 including ARM9TDMI, ARM920T, and ARM926EJ-S.
7410 @deffn Command {arm7_9 dcc_downloads} [@option{enable}|@option{disable}]
7412 Displays the value of the flag controlling use of the debug communications
7413 channel (DCC) to write larger (>128 byte) amounts of memory.
7414 If a boolean parameter is provided, first assigns that flag.
7416 DCC downloads offer a huge speed increase, but might be
7417 unsafe, especially with targets running at very low speeds. This command was introduced
7418 with OpenOCD rev. 60, and requires a few bytes of working area.
7421 @deffn Command {arm7_9 fast_memory_access} [@option{enable}|@option{disable}]
7422 Displays the value of the flag controlling use of memory writes and reads
7423 that don't check completion of the operation.
7424 If a boolean parameter is provided, first assigns that flag.
7426 This provides a huge speed increase, especially with USB JTAG
7427 cables (FT2232), but might be unsafe if used with targets running at very low
7428 speeds, like the 32kHz startup clock of an AT91RM9200.
7431 @subsection ARM720T specific commands
7434 These commands are available to ARM720T based CPUs,
7435 which are implementations of the ARMv4T architecture
7436 based on the ARM7TDMI-S integer core.
7437 They are available in addition to the ARM and ARM7/ARM9 commands.
7439 @deffn Command {arm720t cp15} opcode [value]
7440 @emph{DEPRECATED -- avoid using this.
7441 Use the @command{arm mrc} or @command{arm mcr} commands instead.}
7443 Display cp15 register returned by the ARM instruction @var{opcode};
7444 else if a @var{value} is provided, that value is written to that register.
7445 The @var{opcode} should be the value of either an MRC or MCR instruction.
7448 @subsection ARM9 specific commands
7451 ARM9-family cores are built around ARM9TDMI or ARM9E (including ARM9EJS)
7453 Such cores include the ARM920T, ARM926EJ-S, and ARM966.
7455 @c 9-june-2009: tried this on arm920t, it didn't work.
7456 @c no-params always lists nothing caught, and that's how it acts.
7457 @c 23-oct-2009: doesn't work _consistently_ ... as if the ICE
7458 @c versions have different rules about when they commit writes.
7460 @anchor{arm9vectorcatch}
7461 @deffn Command {arm9 vector_catch} [@option{all}|@option{none}|list]
7462 @cindex vector_catch
7463 Vector Catch hardware provides a sort of dedicated breakpoint
7464 for hardware events such as reset, interrupt, and abort.
7465 You can use this to conserve normal breakpoint resources,
7466 so long as you're not concerned with code that branches directly
7467 to those hardware vectors.
7469 This always finishes by listing the current configuration.
7470 If parameters are provided, it first reconfigures the
7471 vector catch hardware to intercept
7472 @option{all} of the hardware vectors,
7473 @option{none} of them,
7474 or a list with one or more of the following:
7475 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt}
7476 @option{irq} @option{fiq}.
7479 @subsection ARM920T specific commands
7482 These commands are available to ARM920T based CPUs,
7483 which are implementations of the ARMv4T architecture
7484 built using the ARM9TDMI integer core.
7485 They are available in addition to the ARM, ARM7/ARM9,
7488 @deffn Command {arm920t cache_info}
7489 Print information about the caches found. This allows to see whether your target
7490 is an ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
7493 @deffn Command {arm920t cp15} regnum [value]
7494 Display cp15 register @var{regnum};
7495 else if a @var{value} is provided, that value is written to that register.
7496 This uses "physical access" and the register number is as
7497 shown in bits 38..33 of table 9-9 in the ARM920T TRM.
7498 (Not all registers can be written.)
7501 @deffn Command {arm920t cp15i} opcode [value [address]]
7502 @emph{DEPRECATED -- avoid using this.
7503 Use the @command{arm mrc} or @command{arm mcr} commands instead.}
7505 Interpreted access using ARM instruction @var{opcode}, which should
7506 be the value of either an MRC or MCR instruction
7507 (as shown tables 9-11, 9-12, and 9-13 in the ARM920T TRM).
7508 If no @var{value} is provided, the result is displayed.
7509 Else if that value is written using the specified @var{address},
7510 or using zero if no other address is provided.
7513 @deffn Command {arm920t read_cache} filename
7514 Dump the content of ICache and DCache to a file named @file{filename}.
7517 @deffn Command {arm920t read_mmu} filename
7518 Dump the content of the ITLB and DTLB to a file named @file{filename}.
7521 @subsection ARM926ej-s specific commands
7524 These commands are available to ARM926ej-s based CPUs,
7525 which are implementations of the ARMv5TEJ architecture
7526 based on the ARM9EJ-S integer core.
7527 They are available in addition to the ARM, ARM7/ARM9,
7530 The Feroceon cores also support these commands, although
7531 they are not built from ARM926ej-s designs.
7533 @deffn Command {arm926ejs cache_info}
7534 Print information about the caches found.
7537 @subsection ARM966E specific commands
7540 These commands are available to ARM966 based CPUs,
7541 which are implementations of the ARMv5TE architecture.
7542 They are available in addition to the ARM, ARM7/ARM9,
7545 @deffn Command {arm966e cp15} regnum [value]
7546 Display cp15 register @var{regnum};
7547 else if a @var{value} is provided, that value is written to that register.
7548 The six bit @var{regnum} values are bits 37..32 from table 7-2 of the
7550 There is no current control over bits 31..30 from that table,
7551 as required for BIST support.
7554 @subsection XScale specific commands
7557 Some notes about the debug implementation on the XScale CPUs:
7559 The XScale CPU provides a special debug-only mini-instruction cache
7560 (mini-IC) in which exception vectors and target-resident debug handler
7561 code are placed by OpenOCD. In order to get access to the CPU, OpenOCD
7562 must point vector 0 (the reset vector) to the entry of the debug
7563 handler. However, this means that the complete first cacheline in the
7564 mini-IC is marked valid, which makes the CPU fetch all exception
7565 handlers from the mini-IC, ignoring the code in RAM.
7567 To address this situation, OpenOCD provides the @code{xscale
7568 vector_table} command, which allows the user to explicity write
7569 individual entries to either the high or low vector table stored in
7572 It is recommended to place a pc-relative indirect branch in the vector
7573 table, and put the branch destination somewhere in memory. Doing so
7574 makes sure the code in the vector table stays constant regardless of
7575 code layout in memory:
7578 ldr pc,[pc,#0x100-8]
7579 ldr pc,[pc,#0x100-8]
7580 ldr pc,[pc,#0x100-8]
7581 ldr pc,[pc,#0x100-8]
7582 ldr pc,[pc,#0x100-8]
7583 ldr pc,[pc,#0x100-8]
7584 ldr pc,[pc,#0x100-8]
7585 ldr pc,[pc,#0x100-8]
7587 .long real_reset_vector
7588 .long real_ui_handler
7589 .long real_swi_handler
7591 .long real_data_abort
7592 .long 0 /* unused */
7593 .long real_irq_handler
7594 .long real_fiq_handler
7597 Alternatively, you may choose to keep some or all of the mini-IC
7598 vector table entries synced with those written to memory by your
7599 system software. The mini-IC can not be modified while the processor
7600 is executing, but for each vector table entry not previously defined
7601 using the @code{xscale vector_table} command, OpenOCD will copy the
7602 value from memory to the mini-IC every time execution resumes from a
7603 halt. This is done for both high and low vector tables (although the
7604 table not in use may not be mapped to valid memory, and in this case
7605 that copy operation will silently fail). This means that you will
7606 need to briefly halt execution at some strategic point during system
7607 start-up; e.g., after the software has initialized the vector table,
7608 but before exceptions are enabled. A breakpoint can be used to
7609 accomplish this once the appropriate location in the start-up code has
7610 been identified. A watchpoint over the vector table region is helpful
7611 in finding the location if you're not sure. Note that the same
7612 situation exists any time the vector table is modified by the system
7615 The debug handler must be placed somewhere in the address space using
7616 the @code{xscale debug_handler} command. The allowed locations for the
7617 debug handler are either (0x800 - 0x1fef800) or (0xfe000800 -
7618 0xfffff800). The default value is 0xfe000800.
7620 XScale has resources to support two hardware breakpoints and two
7621 watchpoints. However, the following restrictions on watchpoint
7622 functionality apply: (1) the value and mask arguments to the @code{wp}
7623 command are not supported, (2) the watchpoint length must be a
7624 power of two and not less than four, and can not be greater than the
7625 watchpoint address, and (3) a watchpoint with a length greater than
7626 four consumes all the watchpoint hardware resources. This means that
7627 at any one time, you can have enabled either two watchpoints with a
7628 length of four, or one watchpoint with a length greater than four.
7630 These commands are available to XScale based CPUs,
7631 which are implementations of the ARMv5TE architecture.
7633 @deffn Command {xscale analyze_trace}
7634 Displays the contents of the trace buffer.
7637 @deffn Command {xscale cache_clean_address} address
7638 Changes the address used when cleaning the data cache.
7641 @deffn Command {xscale cache_info}
7642 Displays information about the CPU caches.
7645 @deffn Command {xscale cp15} regnum [value]
7646 Display cp15 register @var{regnum};
7647 else if a @var{value} is provided, that value is written to that register.
7650 @deffn Command {xscale debug_handler} target address
7651 Changes the address used for the specified target's debug handler.
7654 @deffn Command {xscale dcache} [@option{enable}|@option{disable}]
7655 Enables or disable the CPU's data cache.
7658 @deffn Command {xscale dump_trace} filename
7659 Dumps the raw contents of the trace buffer to @file{filename}.
7662 @deffn Command {xscale icache} [@option{enable}|@option{disable}]
7663 Enables or disable the CPU's instruction cache.
7666 @deffn Command {xscale mmu} [@option{enable}|@option{disable}]
7667 Enables or disable the CPU's memory management unit.
7670 @deffn Command {xscale trace_buffer} [@option{enable}|@option{disable} [@option{fill} [n] | @option{wrap}]]
7671 Displays the trace buffer status, after optionally
7672 enabling or disabling the trace buffer
7673 and modifying how it is emptied.
7676 @deffn Command {xscale trace_image} filename [offset [type]]
7677 Opens a trace image from @file{filename}, optionally rebasing
7678 its segment addresses by @var{offset}.
7679 The image @var{type} may be one of
7680 @option{bin} (binary), @option{ihex} (Intel hex),
7681 @option{elf} (ELF file), @option{s19} (Motorola s19),
7682 @option{mem}, or @option{builder}.
7685 @anchor{xscalevectorcatch}
7686 @deffn Command {xscale vector_catch} [mask]
7687 @cindex vector_catch
7688 Display a bitmask showing the hardware vectors to catch.
7689 If the optional parameter is provided, first set the bitmask to that value.
7691 The mask bits correspond with bit 16..23 in the DCSR:
7694 0x02 Trap Undefined Instructions
7695 0x04 Trap Software Interrupt
7696 0x08 Trap Prefetch Abort
7697 0x10 Trap Data Abort
7704 @deffn Command {xscale vector_table} [(@option{low}|@option{high}) index value]
7705 @cindex vector_table
7707 Set an entry in the mini-IC vector table. There are two tables: one for
7708 low vectors (at 0x00000000), and one for high vectors (0xFFFF0000), each
7709 holding the 8 exception vectors. @var{index} can be 1-7, because vector 0
7710 points to the debug handler entry and can not be overwritten.
7711 @var{value} holds the 32-bit opcode that is placed in the mini-IC.
7713 Without arguments, the current settings are displayed.
7717 @section ARMv6 Architecture
7720 @subsection ARM11 specific commands
7723 @deffn Command {arm11 memwrite burst} [@option{enable}|@option{disable}]
7724 Displays the value of the memwrite burst-enable flag,
7725 which is enabled by default.
7726 If a boolean parameter is provided, first assigns that flag.
7727 Burst writes are only used for memory writes larger than 1 word.
7728 They improve performance by assuming that the CPU has read each data
7729 word over JTAG and completed its write before the next word arrives,
7730 instead of polling for a status flag to verify that completion.
7731 This is usually safe, because JTAG runs much slower than the CPU.
7734 @deffn Command {arm11 memwrite error_fatal} [@option{enable}|@option{disable}]
7735 Displays the value of the memwrite error_fatal flag,
7736 which is enabled by default.
7737 If a boolean parameter is provided, first assigns that flag.
7738 When set, certain memory write errors cause earlier transfer termination.
7741 @deffn Command {arm11 step_irq_enable} [@option{enable}|@option{disable}]
7742 Displays the value of the flag controlling whether
7743 IRQs are enabled during single stepping;
7744 they are disabled by default.
7745 If a boolean parameter is provided, first assigns that.
7748 @deffn Command {arm11 vcr} [value]
7749 @cindex vector_catch
7750 Displays the value of the @emph{Vector Catch Register (VCR)},
7751 coprocessor 14 register 7.
7752 If @var{value} is defined, first assigns that.
7754 Vector Catch hardware provides dedicated breakpoints
7755 for certain hardware events.
7756 The specific bit values are core-specific (as in fact is using
7757 coprocessor 14 register 7 itself) but all current ARM11
7758 cores @emph{except the ARM1176} use the same six bits.
7761 @section ARMv7 Architecture
7764 @subsection ARMv7 Debug Access Port (DAP) specific commands
7765 @cindex Debug Access Port
7767 These commands are specific to ARM architecture v7 Debug Access Port (DAP),
7768 included on Cortex-M and Cortex-A systems.
7769 They are available in addition to other core-specific commands that may be available.
7771 @deffn Command {dap apid} [num]
7772 Displays ID register from AP @var{num},
7773 defaulting to the currently selected AP.
7776 @deffn Command {dap apsel} [num]
7777 Select AP @var{num}, defaulting to 0.
7780 @deffn Command {dap baseaddr} [num]
7781 Displays debug base address from MEM-AP @var{num},
7782 defaulting to the currently selected AP.
7785 @deffn Command {dap info} [num]
7786 Displays the ROM table for MEM-AP @var{num},
7787 defaulting to the currently selected AP.
7790 @deffn Command {dap memaccess} [value]
7791 Displays the number of extra tck cycles in the JTAG idle to use for MEM-AP
7792 memory bus access [0-255], giving additional time to respond to reads.
7793 If @var{value} is defined, first assigns that.
7796 @deffn Command {dap apcsw} [0 / 1]
7797 fix CSW_SPROT from register AP_REG_CSW on selected dap.
7801 @deffn Command {dap ti_be_32_quirks} [@option{enable}]
7802 Set/get quirks mode for TI TMS450/TMS570 processors
7807 @subsection ARMv7-A specific commands
7810 @deffn Command {cortex_a cache_info}
7811 display information about target caches
7814 @deffn Command {cortex_a dacrfixup [@option{on}|@option{off}]}
7815 Work around issues with software breakpoints when the program text is
7816 mapped read-only by the operating system. This option sets the CP15 DACR
7817 to "all-manager" to bypass MMU permission checks on memory access.
7821 @deffn Command {cortex_a dbginit}
7822 Initialize core debug
7823 Enables debug by unlocking the Software Lock and clearing sticky powerdown indications
7826 @deffn Command {cortex_a smp_off}
7830 @deffn Command {cortex_a smp_on}
7834 @deffn Command {cortex_a smp_gdb} [core_id]
7835 Display/set the current core displayed in GDB
7838 @deffn Command {cortex_a maskisr} [@option{on}|@option{off}]
7839 Selects whether interrupts will be processed when single stepping
7842 @deffn Command {cache_config l2x} [base way]
7847 @subsection ARMv7-R specific commands
7850 @deffn Command {cortex_r dbginit}
7851 Initialize core debug
7852 Enables debug by unlocking the Software Lock and clearing sticky powerdown indications
7855 @deffn Command {cortex_r maskisr} [@option{on}|@option{off}]
7856 Selects whether interrupts will be processed when single stepping
7860 @subsection ARMv7-M specific commands
7868 @deffn Command {tpiu config} (@option{disable} | ((@option{external} | @option{internal (@var{filename} | -)}) @
7869 (@option{sync @var{port_width}} | ((@option{manchester} | @option{uart}) @var{formatter_enable})) @
7870 @var{TRACECLKIN_freq} [@var{trace_freq}]))
7872 ARMv7-M architecture provides several modules to generate debugging
7873 information internally (ITM, DWT and ETM). Their output is directed
7874 through TPIU to be captured externally either on an SWO pin (this
7875 configuration is called SWV) or on a synchronous parallel trace port.
7877 This command configures the TPIU module of the target and, if internal
7878 capture mode is selected, starts to capture trace output by using the
7879 debugger adapter features.
7881 Some targets require additional actions to be performed in the
7882 @b{trace-config} handler for trace port to be activated.
7886 @item @option{disable} disable TPIU handling;
7887 @item @option{external} configure TPIU to let user capture trace
7888 output externally (with an additional UART or logic analyzer hardware);
7889 @item @option{internal @var{filename}} configure TPIU and debug adapter to
7890 gather trace data and append it to @var{filename} (which can be
7891 either a regular file or a named pipe);
7892 @item @option{internal -} configure TPIU and debug adapter to
7893 gather trace data, but not write to any file. Useful in conjunction with the @command{tcl_trace} command;
7894 @item @option{sync @var{port_width}} use synchronous parallel trace output
7895 mode, and set port width to @var{port_width};
7896 @item @option{manchester} use asynchronous SWO mode with Manchester
7898 @item @option{uart} use asynchronous SWO mode with NRZ (same as
7899 regular UART 8N1) coding;
7900 @item @var{formatter_enable} is @option{on} or @option{off} to enable
7901 or disable TPIU formatter which needs to be used when both ITM and ETM
7902 data is to be output via SWO;
7903 @item @var{TRACECLKIN_freq} this should be specified to match target's
7904 current TRACECLKIN frequency (usually the same as HCLK);
7905 @item @var{trace_freq} trace port frequency. Can be omitted in
7906 internal mode to let the adapter driver select the maximum supported
7912 @item STM32L152 board is programmed with an application that configures
7913 PLL to provide core clock with 24MHz frequency; to use ITM output it's
7916 #include <libopencm3/cm3/itm.h>
7921 (the most obvious way is to use the first stimulus port for printf,
7922 for that this ITM_STIM8 assignment can be used inside _write(); to make it
7923 blocking to avoid data loss, add @code{while (!(ITM_STIM8(0) &
7924 ITM_STIM_FIFOREADY));});
7925 @item An FT2232H UART is connected to the SWO pin of the board;
7926 @item Commands to configure UART for 12MHz baud rate:
7928 $ setserial /dev/ttyUSB1 spd_cust divisor 5
7929 $ stty -F /dev/ttyUSB1 38400
7931 (FT2232H's base frequency is 60MHz, spd_cust allows to alias 38400
7932 baud with our custom divisor to get 12MHz)
7933 @item @code{itmdump -f /dev/ttyUSB1 -d1}
7934 @item OpenOCD invocation line:
7936 openocd -f interface/stlink-v2-1.cfg \
7937 -c "transport select hla_swd" \
7938 -f target/stm32l1.cfg \
7939 -c "tpiu config external uart off 24000000 12000000"
7944 @deffn Command {itm port} @var{port} (@option{0}|@option{1}|@option{on}|@option{off})
7945 Enable or disable trace output for ITM stimulus @var{port} (counting
7946 from 0). Port 0 is enabled on target creation automatically.
7949 @deffn Command {itm ports} (@option{0}|@option{1}|@option{on}|@option{off})
7950 Enable or disable trace output for all ITM stimulus ports.
7953 @subsection Cortex-M specific commands
7956 @deffn Command {cortex_m maskisr} (@option{auto}|@option{on}|@option{off})
7957 Control masking (disabling) interrupts during target step/resume.
7959 The @option{auto} option handles interrupts during stepping a way they get
7960 served but don't disturb the program flow. The step command first allows
7961 pending interrupt handlers to execute, then disables interrupts and steps over
7962 the next instruction where the core was halted. After the step interrupts
7963 are enabled again. If the interrupt handlers don't complete within 500ms,
7964 the step command leaves with the core running.
7966 Note that a free breakpoint is required for the @option{auto} option. If no
7967 breakpoint is available at the time of the step, then the step is taken
7968 with interrupts enabled, i.e. the same way the @option{off} option does.
7970 Default is @option{auto}.
7973 @deffn Command {cortex_m vector_catch} [@option{all}|@option{none}|list]
7974 @cindex vector_catch
7975 Vector Catch hardware provides dedicated breakpoints
7976 for certain hardware events.
7978 Parameters request interception of
7979 @option{all} of these hardware event vectors,
7980 @option{none} of them,
7981 or one or more of the following:
7982 @option{hard_err} for a HardFault exception;
7983 @option{mm_err} for a MemManage exception;
7984 @option{bus_err} for a BusFault exception;
7987 @option{chk_err}, or
7988 @option{nocp_err} for various UsageFault exceptions; or
7990 If NVIC setup code does not enable them,
7991 MemManage, BusFault, and UsageFault exceptions
7992 are mapped to HardFault.
7993 UsageFault checks for
7994 divide-by-zero and unaligned access
7995 must also be explicitly enabled.
7997 This finishes by listing the current vector catch configuration.
8000 @deffn Command {cortex_m reset_config} (@option{srst}|@option{sysresetreq}|@option{vectreset})
8001 Control reset handling. The default @option{srst} is to use srst if fitted,
8002 otherwise fallback to @option{vectreset}.
8004 @item @option{srst} use hardware srst if fitted otherwise fallback to @option{vectreset}.
8005 @item @option{sysresetreq} use NVIC SYSRESETREQ to reset system.
8006 @item @option{vectreset} use NVIC VECTRESET to reset system.
8008 Using @option{vectreset} is a safe option for all current Cortex-M cores.
8009 This however has the disadvantage of only resetting the core, all peripherals
8010 are uneffected. A solution would be to use a @code{reset-init} event handler to manually reset
8012 @xref{targetevents,,Target Events}.
8015 @section Intel Architecture
8017 Intel Quark X10xx is the first product in the Quark family of SoCs. It is an IA-32
8018 (Pentium x86 ISA) compatible SoC. The core CPU in the X10xx is codenamed Lakemont.
8019 Lakemont version 1 (LMT1) is used in X10xx. The CPU TAP (Lakemont TAP) is used for
8020 software debug and the CLTAP is used for SoC level operations.
8021 Useful docs are here: https://communities.intel.com/community/makers/documentation
8023 @item Intel Quark SoC X1000 OpenOCD/GDB/Eclipse App Note (web search for doc num 330015)
8024 @item Intel Quark SoC X1000 Debug Operations User Guide (web search for doc num 329866)
8025 @item Intel Quark SoC X1000 Datasheet (web search for doc num 329676)
8028 @subsection x86 32-bit specific commands
8029 The three main address spaces for x86 are memory, I/O and configuration space.
8030 These commands allow a user to read and write to the 64Kbyte I/O address space.
8032 @deffn Command {x86_32 idw} address
8033 Display the contents of a 32-bit I/O port from address range 0x0000 - 0xffff.
8036 @deffn Command {x86_32 idh} address
8037 Display the contents of a 16-bit I/O port from address range 0x0000 - 0xffff.
8040 @deffn Command {x86_32 idb} address
8041 Display the contents of a 8-bit I/O port from address range 0x0000 - 0xffff.
8044 @deffn Command {x86_32 iww} address
8045 Write the contents of a 32-bit I/O port to address range 0x0000 - 0xffff.
8048 @deffn Command {x86_32 iwh} address
8049 Write the contents of a 16-bit I/O port to address range 0x0000 - 0xffff.
8052 @deffn Command {x86_32 iwb} address
8053 Write the contents of a 8-bit I/O port to address range 0x0000 - 0xffff.
8056 @section OpenRISC Architecture
8058 The OpenRISC CPU is a soft core. It is used in a programmable SoC which can be
8059 configured with any of the TAP / Debug Unit available.
8061 @subsection TAP and Debug Unit selection commands
8062 @deffn Command {tap_select} (@option{vjtag}|@option{mohor}|@option{xilinx_bscan})
8063 Select between the Altera Virtual JTAG , Xilinx Virtual JTAG and Mohor TAP.
8065 @deffn Command {du_select} (@option{adv}|@option{mohor}) [option]
8066 Select between the Advanced Debug Interface and the classic one.
8068 An option can be passed as a second argument to the debug unit.
8070 When using the Advanced Debug Interface, option = 1 means the RTL core is
8071 configured with ADBG_USE_HISPEED = 1. This configuration skips status checking
8072 between bytes while doing read or write bursts.
8075 @subsection Registers commands
8076 @deffn Command {addreg} [name] [address] [feature] [reg_group]
8077 Add a new register in the cpu register list. This register will be
8078 included in the generated target descriptor file.
8080 @strong{[feature]} must be "org.gnu.gdb.or1k.group[0..10]".
8082 @strong{[reg_group]} can be anything. The default register list defines "system",
8083 "dmmu", "immu", "dcache", "icache", "mac", "debug", "perf", "power", "pic"
8088 addreg rtest 0x1234 org.gnu.gdb.or1k.group0 system
8093 @deffn Command {readgroup} (@option{group})
8094 Display all registers in @emph{group}.
8096 @emph{group} can be "system",
8097 "dmmu", "immu", "dcache", "icache", "mac", "debug", "perf", "power", "pic",
8098 "timer" or any new group created with addreg command.
8101 @anchor{softwaredebugmessagesandtracing}
8102 @section Software Debug Messages and Tracing
8103 @cindex Linux-ARM DCC support
8107 OpenOCD can process certain requests from target software, when
8108 the target uses appropriate libraries.
8109 The most powerful mechanism is semihosting, but there is also
8110 a lighter weight mechanism using only the DCC channel.
8112 Currently @command{target_request debugmsgs}
8113 is supported only for @option{arm7_9} and @option{cortex_m} cores.
8114 These messages are received as part of target polling, so
8115 you need to have @command{poll on} active to receive them.
8116 They are intrusive in that they will affect program execution
8117 times. If that is a problem, @pxref{armhardwaretracing,,ARM Hardware Tracing}.
8119 See @file{libdcc} in the contrib dir for more details.
8120 In addition to sending strings, characters, and
8121 arrays of various size integers from the target,
8122 @file{libdcc} also exports a software trace point mechanism.
8123 The target being debugged may
8124 issue trace messages which include a 24-bit @dfn{trace point} number.
8125 Trace point support includes two distinct mechanisms,
8126 each supported by a command:
8129 @item @emph{History} ... A circular buffer of trace points
8130 can be set up, and then displayed at any time.
8131 This tracks where code has been, which can be invaluable in
8132 finding out how some fault was triggered.
8134 The buffer may overflow, since it collects records continuously.
8135 It may be useful to use some of the 24 bits to represent a
8136 particular event, and other bits to hold data.
8138 @item @emph{Counting} ... An array of counters can be set up,
8139 and then displayed at any time.
8140 This can help establish code coverage and identify hot spots.
8142 The array of counters is directly indexed by the trace point
8143 number, so trace points with higher numbers are not counted.
8146 Linux-ARM kernels have a ``Kernel low-level debugging
8147 via EmbeddedICE DCC channel'' option (CONFIG_DEBUG_ICEDCC,
8148 depends on CONFIG_DEBUG_LL) which uses this mechanism to
8149 deliver messages before a serial console can be activated.
8150 This is not the same format used by @file{libdcc}.
8151 Other software, such as the U-Boot boot loader, sometimes
8152 does the same thing.
8154 @deffn Command {target_request debugmsgs} [@option{enable}|@option{disable}|@option{charmsg}]
8155 Displays current handling of target DCC message requests.
8156 These messages may be sent to the debugger while the target is running.
8157 The optional @option{enable} and @option{charmsg} parameters
8158 both enable the messages, while @option{disable} disables them.
8160 With @option{charmsg} the DCC words each contain one character,
8161 as used by Linux with CONFIG_DEBUG_ICEDCC;
8162 otherwise the libdcc format is used.
8165 @deffn Command {trace history} [@option{clear}|count]
8166 With no parameter, displays all the trace points that have triggered
8167 in the order they triggered.
8168 With the parameter @option{clear}, erases all current trace history records.
8169 With a @var{count} parameter, allocates space for that many
8173 @deffn Command {trace point} [@option{clear}|identifier]
8174 With no parameter, displays all trace point identifiers and how many times
8175 they have been triggered.
8176 With the parameter @option{clear}, erases all current trace point counters.
8177 With a numeric @var{identifier} parameter, creates a new a trace point counter
8178 and associates it with that identifier.
8180 @emph{Important:} The identifier and the trace point number
8181 are not related except by this command.
8182 These trace point numbers always start at zero (from server startup,
8183 or after @command{trace point clear}) and count up from there.
8188 @chapter JTAG Commands
8189 @cindex JTAG Commands
8190 Most general purpose JTAG commands have been presented earlier.
8191 (@xref{jtagspeed,,JTAG Speed}, @ref{Reset Configuration}, and @ref{TAP Declaration}.)
8192 Lower level JTAG commands, as presented here,
8193 may be needed to work with targets which require special
8194 attention during operations such as reset or initialization.
8196 To use these commands you will need to understand some
8197 of the basics of JTAG, including:
8200 @item A JTAG scan chain consists of a sequence of individual TAP
8201 devices such as a CPUs.
8202 @item Control operations involve moving each TAP through the same
8203 standard state machine (in parallel)
8204 using their shared TMS and clock signals.
8205 @item Data transfer involves shifting data through the chain of
8206 instruction or data registers of each TAP, writing new register values
8207 while the reading previous ones.
8208 @item Data register sizes are a function of the instruction active in
8209 a given TAP, while instruction register sizes are fixed for each TAP.
8210 All TAPs support a BYPASS instruction with a single bit data register.
8211 @item The way OpenOCD differentiates between TAP devices is by
8212 shifting different instructions into (and out of) their instruction
8216 @section Low Level JTAG Commands
8218 These commands are used by developers who need to access
8219 JTAG instruction or data registers, possibly controlling
8220 the order of TAP state transitions.
8221 If you're not debugging OpenOCD internals, or bringing up a
8222 new JTAG adapter or a new type of TAP device (like a CPU or
8223 JTAG router), you probably won't need to use these commands.
8224 In a debug session that doesn't use JTAG for its transport protocol,
8225 these commands are not available.
8227 @deffn Command {drscan} tap [numbits value]+ [@option{-endstate} tap_state]
8228 Loads the data register of @var{tap} with a series of bit fields
8229 that specify the entire register.
8230 Each field is @var{numbits} bits long with
8231 a numeric @var{value} (hexadecimal encouraged).
8232 The return value holds the original value of each
8235 For example, a 38 bit number might be specified as one
8236 field of 32 bits then one of 6 bits.
8237 @emph{For portability, never pass fields which are more
8238 than 32 bits long. Many OpenOCD implementations do not
8239 support 64-bit (or larger) integer values.}
8241 All TAPs other than @var{tap} must be in BYPASS mode.
8242 The single bit in their data registers does not matter.
8244 When @var{tap_state} is specified, the JTAG state machine is left
8246 For example @sc{drpause} might be specified, so that more
8247 instructions can be issued before re-entering the @sc{run/idle} state.
8248 If the end state is not specified, the @sc{run/idle} state is entered.
8251 OpenOCD does not record information about data register lengths,
8252 so @emph{it is important that you get the bit field lengths right}.
8253 Remember that different JTAG instructions refer to different
8254 data registers, which may have different lengths.
8255 Moreover, those lengths may not be fixed;
8256 the SCAN_N instruction can change the length of
8257 the register accessed by the INTEST instruction
8258 (by connecting a different scan chain).
8262 @deffn Command {flush_count}
8263 Returns the number of times the JTAG queue has been flushed.
8264 This may be used for performance tuning.
8266 For example, flushing a queue over USB involves a
8267 minimum latency, often several milliseconds, which does
8268 not change with the amount of data which is written.
8269 You may be able to identify performance problems by finding
8270 tasks which waste bandwidth by flushing small transfers too often,
8271 instead of batching them into larger operations.
8274 @deffn Command {irscan} [tap instruction]+ [@option{-endstate} tap_state]
8275 For each @var{tap} listed, loads the instruction register
8276 with its associated numeric @var{instruction}.
8277 (The number of bits in that instruction may be displayed
8278 using the @command{scan_chain} command.)
8279 For other TAPs, a BYPASS instruction is loaded.
8281 When @var{tap_state} is specified, the JTAG state machine is left
8283 For example @sc{irpause} might be specified, so the data register
8284 can be loaded before re-entering the @sc{run/idle} state.
8285 If the end state is not specified, the @sc{run/idle} state is entered.
8288 OpenOCD currently supports only a single field for instruction
8289 register values, unlike data register values.
8290 For TAPs where the instruction register length is more than 32 bits,
8291 portable scripts currently must issue only BYPASS instructions.
8295 @deffn Command {jtag_reset} trst srst
8296 Set values of reset signals.
8297 The @var{trst} and @var{srst} parameter values may be
8298 @option{0}, indicating that reset is inactive (pulled or driven high),
8299 or @option{1}, indicating it is active (pulled or driven low).
8300 The @command{reset_config} command should already have been used
8301 to configure how the board and JTAG adapter treat these two
8302 signals, and to say if either signal is even present.
8303 @xref{Reset Configuration}.
8305 Note that TRST is specially handled.
8306 It actually signifies JTAG's @sc{reset} state.
8307 So if the board doesn't support the optional TRST signal,
8308 or it doesn't support it along with the specified SRST value,
8309 JTAG reset is triggered with TMS and TCK signals
8310 instead of the TRST signal.
8311 And no matter how that JTAG reset is triggered, once
8312 the scan chain enters @sc{reset} with TRST inactive,
8313 TAP @code{post-reset} events are delivered to all TAPs
8314 with handlers for that event.
8317 @deffn Command {pathmove} start_state [next_state ...]
8318 Start by moving to @var{start_state}, which
8319 must be one of the @emph{stable} states.
8320 Unless it is the only state given, this will often be the
8321 current state, so that no TCK transitions are needed.
8322 Then, in a series of single state transitions
8323 (conforming to the JTAG state machine) shift to
8324 each @var{next_state} in sequence, one per TCK cycle.
8325 The final state must also be stable.
8328 @deffn Command {runtest} @var{num_cycles}
8329 Move to the @sc{run/idle} state, and execute at least
8330 @var{num_cycles} of the JTAG clock (TCK).
8331 Instructions often need some time
8332 to execute before they take effect.
8335 @c tms_sequence (short|long)
8336 @c ... temporary, debug-only, other than USBprog bug workaround...
8338 @deffn Command {verify_ircapture} (@option{enable}|@option{disable})
8339 Verify values captured during @sc{ircapture} and returned
8340 during IR scans. Default is enabled, but this can be
8341 overridden by @command{verify_jtag}.
8342 This flag is ignored when validating JTAG chain configuration.
8345 @deffn Command {verify_jtag} (@option{enable}|@option{disable})
8346 Enables verification of DR and IR scans, to help detect
8347 programming errors. For IR scans, @command{verify_ircapture}
8348 must also be enabled.
8352 @section TAP state names
8353 @cindex TAP state names
8355 The @var{tap_state} names used by OpenOCD in the @command{drscan},
8356 @command{irscan}, and @command{pathmove} commands are the same
8357 as those used in SVF boundary scan documents, except that
8358 SVF uses @sc{idle} instead of @sc{run/idle}.
8361 @item @b{RESET} ... @emph{stable} (with TMS high);
8362 acts as if TRST were pulsed
8363 @item @b{RUN/IDLE} ... @emph{stable}; don't assume this always means IDLE
8366 @item @b{DRSHIFT} ... @emph{stable}; TDI/TDO shifting
8367 through the data register
8369 @item @b{DRPAUSE} ... @emph{stable}; data register ready
8370 for update or more shifting
8375 @item @b{IRSHIFT} ... @emph{stable}; TDI/TDO shifting
8376 through the instruction register
8378 @item @b{IRPAUSE} ... @emph{stable}; instruction register ready
8379 for update or more shifting
8384 Note that only six of those states are fully ``stable'' in the
8385 face of TMS fixed (low except for @sc{reset})
8386 and a free-running JTAG clock. For all the
8387 others, the next TCK transition changes to a new state.
8390 @item From @sc{drshift} and @sc{irshift}, clock transitions will
8391 produce side effects by changing register contents. The values
8392 to be latched in upcoming @sc{drupdate} or @sc{irupdate} states
8393 may not be as expected.
8394 @item @sc{run/idle}, @sc{drpause}, and @sc{irpause} are reasonable
8395 choices after @command{drscan} or @command{irscan} commands,
8396 since they are free of JTAG side effects.
8397 @item @sc{run/idle} may have side effects that appear at non-JTAG
8398 levels, such as advancing the ARM9E-S instruction pipeline.
8399 Consult the documentation for the TAP(s) you are working with.
8402 @node Boundary Scan Commands
8403 @chapter Boundary Scan Commands
8405 One of the original purposes of JTAG was to support
8406 boundary scan based hardware testing.
8407 Although its primary focus is to support On-Chip Debugging,
8408 OpenOCD also includes some boundary scan commands.
8410 @section SVF: Serial Vector Format
8411 @cindex Serial Vector Format
8414 The Serial Vector Format, better known as @dfn{SVF}, is a
8415 way to represent JTAG test patterns in text files.
8416 In a debug session using JTAG for its transport protocol,
8417 OpenOCD supports running such test files.
8419 @deffn Command {svf} filename [@option{quiet}]
8420 This issues a JTAG reset (Test-Logic-Reset) and then
8421 runs the SVF script from @file{filename}.
8422 Unless the @option{quiet} option is specified,
8423 each command is logged before it is executed.
8426 @section XSVF: Xilinx Serial Vector Format
8427 @cindex Xilinx Serial Vector Format
8430 The Xilinx Serial Vector Format, better known as @dfn{XSVF}, is a
8431 binary representation of SVF which is optimized for use with
8433 In a debug session using JTAG for its transport protocol,
8434 OpenOCD supports running such test files.
8436 @quotation Important
8437 Not all XSVF commands are supported.
8440 @deffn Command {xsvf} (tapname|@option{plain}) filename [@option{virt2}] [@option{quiet}]
8441 This issues a JTAG reset (Test-Logic-Reset) and then
8442 runs the XSVF script from @file{filename}.
8443 When a @var{tapname} is specified, the commands are directed at
8445 When @option{virt2} is specified, the @sc{xruntest} command counts
8446 are interpreted as TCK cycles instead of microseconds.
8447 Unless the @option{quiet} option is specified,
8448 messages are logged for comments and some retries.
8451 The OpenOCD sources also include two utility scripts
8452 for working with XSVF; they are not currently installed
8453 after building the software.
8454 You may find them useful:
8457 @item @emph{svf2xsvf} ... converts SVF files into the extended XSVF
8458 syntax understood by the @command{xsvf} command; see notes below.
8459 @item @emph{xsvfdump} ... converts XSVF files into a text output format;
8460 understands the OpenOCD extensions.
8463 The input format accepts a handful of non-standard extensions.
8464 These include three opcodes corresponding to SVF extensions
8465 from Lattice Semiconductor (LCOUNT, LDELAY, LDSR), and
8466 two opcodes supporting a more accurate translation of SVF
8467 (XTRST, XWAITSTATE).
8468 If @emph{xsvfdump} shows a file is using those opcodes, it
8469 probably will not be usable with other XSVF tools.
8472 @node Utility Commands
8473 @chapter Utility Commands
8474 @cindex Utility Commands
8476 @section RAM testing
8479 There is often a need to stress-test random access memory (RAM) for
8480 errors. OpenOCD comes with a Tcl implementation of well-known memory
8481 testing procedures allowing the detection of all sorts of issues with
8482 electrical wiring, defective chips, PCB layout and other common
8485 To use them, you usually need to initialise your RAM controller first;
8486 consult your SoC's documentation to get the recommended list of
8487 register operations and translate them to the corresponding
8488 @command{mww}/@command{mwb} commands.
8490 Load the memory testing functions with
8493 source [find tools/memtest.tcl]
8496 to get access to the following facilities:
8498 @deffn Command {memTestDataBus} address
8499 Test the data bus wiring in a memory region by performing a walking
8500 1's test at a fixed address within that region.
8503 @deffn Command {memTestAddressBus} baseaddress size
8504 Perform a walking 1's test on the relevant bits of the address and
8505 check for aliasing. This test will find single-bit address failures
8506 such as stuck-high, stuck-low, and shorted pins.
8509 @deffn Command {memTestDevice} baseaddress size
8510 Test the integrity of a physical memory device by performing an
8511 increment/decrement test over the entire region. In the process every
8512 storage bit in the device is tested as zero and as one.
8515 @deffn Command {runAllMemTests} baseaddress size
8516 Run all of the above tests over a specified memory region.
8519 @section Firmware recovery helpers
8520 @cindex Firmware recovery
8522 OpenOCD includes an easy-to-use script to facilitate mass-market
8523 devices recovery with JTAG.
8525 For quickstart instructions run:
8527 openocd -f tools/firmware-recovery.tcl -c firmware_help
8533 If OpenOCD runs on an embedded host (as ZY1000 does), then TFTP can
8534 be used to access files on PCs (either the developer's PC or some other PC).
8536 The way this works on the ZY1000 is to prefix a filename by
8537 "/tftp/ip/" and append the TFTP path on the TFTP
8538 server (tftpd). For example,
8541 load_image /tftp/10.0.0.96/c:\temp\abc.elf
8544 will load c:\temp\abc.elf from the developer pc (10.0.0.96) into memory as
8545 if the file was hosted on the embedded host.
8547 In order to achieve decent performance, you must choose a TFTP server
8548 that supports a packet size bigger than the default packet size (512 bytes). There
8549 are numerous TFTP servers out there (free and commercial) and you will have to do
8550 a bit of googling to find something that fits your requirements.
8552 @node GDB and OpenOCD
8553 @chapter GDB and OpenOCD
8555 OpenOCD complies with the remote gdbserver protocol and, as such, can be used
8556 to debug remote targets.
8557 Setting up GDB to work with OpenOCD can involve several components:
8560 @item The OpenOCD server support for GDB may need to be configured.
8561 @xref{gdbconfiguration,,GDB Configuration}.
8562 @item GDB's support for OpenOCD may need configuration,
8563 as shown in this chapter.
8564 @item If you have a GUI environment like Eclipse,
8565 that also will probably need to be configured.
8568 Of course, the version of GDB you use will need to be one which has
8569 been built to know about the target CPU you're using. It's probably
8570 part of the tool chain you're using. For example, if you are doing
8571 cross-development for ARM on an x86 PC, instead of using the native
8572 x86 @command{gdb} command you might use @command{arm-none-eabi-gdb}
8573 if that's the tool chain used to compile your code.
8575 @section Connecting to GDB
8576 @cindex Connecting to GDB
8577 Use GDB 6.7 or newer with OpenOCD if you run into trouble. For
8578 instance GDB 6.3 has a known bug that produces bogus memory access
8579 errors, which has since been fixed; see
8580 @url{http://osdir.com/ml/gdb.bugs.discuss/2004-12/msg00018.html}
8582 OpenOCD can communicate with GDB in two ways:
8586 A socket (TCP/IP) connection is typically started as follows:
8588 target remote localhost:3333
8590 This would cause GDB to connect to the gdbserver on the local pc using port 3333.
8592 It is also possible to use the GDB extended remote protocol as follows:
8594 target extended-remote localhost:3333
8597 A pipe connection is typically started as follows:
8599 target remote | openocd -c "gdb_port pipe; log_output openocd.log"
8601 This would cause GDB to run OpenOCD and communicate using pipes (stdin/stdout).
8602 Using this method has the advantage of GDB starting/stopping OpenOCD for the debug
8603 session. log_output sends the log output to a file to ensure that the pipe is
8604 not saturated when using higher debug level outputs.
8607 To list the available OpenOCD commands type @command{monitor help} on the
8610 @section Sample GDB session startup
8612 With the remote protocol, GDB sessions start a little differently
8613 than they do when you're debugging locally.
8614 Here's an example showing how to start a debug session with a
8616 In this case the program was linked to be loaded into SRAM on a Cortex-M3.
8617 Most programs would be written into flash (address 0) and run from there.
8620 $ arm-none-eabi-gdb example.elf
8621 (gdb) target remote localhost:3333
8622 Remote debugging using localhost:3333
8624 (gdb) monitor reset halt
8627 Loading section .vectors, size 0x100 lma 0x20000000
8628 Loading section .text, size 0x5a0 lma 0x20000100
8629 Loading section .data, size 0x18 lma 0x200006a0
8630 Start address 0x2000061c, load size 1720
8631 Transfer rate: 22 KB/sec, 573 bytes/write.
8637 You could then interrupt the GDB session to make the program break,
8638 type @command{where} to show the stack, @command{list} to show the
8639 code around the program counter, @command{step} through code,
8640 set breakpoints or watchpoints, and so on.
8642 @section Configuring GDB for OpenOCD
8644 OpenOCD supports the gdb @option{qSupported} packet, this enables information
8645 to be sent by the GDB remote server (i.e. OpenOCD) to GDB. Typical information includes
8646 packet size and the device's memory map.
8647 You do not need to configure the packet size by hand,
8648 and the relevant parts of the memory map should be automatically
8649 set up when you declare (NOR) flash banks.
8651 However, there are other things which GDB can't currently query.
8652 You may need to set those up by hand.
8653 As OpenOCD starts up, you will often see a line reporting
8657 Info : lm3s.cpu: hardware has 6 breakpoints, 4 watchpoints
8660 You can pass that information to GDB with these commands:
8663 set remote hardware-breakpoint-limit 6
8664 set remote hardware-watchpoint-limit 4
8667 With that particular hardware (Cortex-M3) the hardware breakpoints
8668 only work for code running from flash memory. Most other ARM systems
8669 do not have such restrictions.
8671 Another example of useful GDB configuration came from a user who
8672 found that single stepping his Cortex-M3 didn't work well with IRQs
8673 and an RTOS until he told GDB to disable the IRQs while stepping:
8677 mon cortex_m maskisr on
8679 define hookpost-step
8680 mon cortex_m maskisr off
8684 Rather than typing such commands interactively, you may prefer to
8685 save them in a file and have GDB execute them as it starts, perhaps
8686 using a @file{.gdbinit} in your project directory or starting GDB
8687 using @command{gdb -x filename}.
8689 @section Programming using GDB
8690 @cindex Programming using GDB
8691 @anchor{programmingusinggdb}
8693 By default the target memory map is sent to GDB. This can be disabled by
8694 the following OpenOCD configuration option:
8696 gdb_memory_map disable
8698 For this to function correctly a valid flash configuration must also be set
8699 in OpenOCD. For faster performance you should also configure a valid
8702 Informing GDB of the memory map of the target will enable GDB to protect any
8703 flash areas of the target and use hardware breakpoints by default. This means
8704 that the OpenOCD option @command{gdb_breakpoint_override} is not required when
8705 using a memory map. @xref{gdbbreakpointoverride,,gdb_breakpoint_override}.
8707 To view the configured memory map in GDB, use the GDB command @option{info mem}.
8708 All other unassigned addresses within GDB are treated as RAM.
8710 GDB 6.8 and higher set any memory area not in the memory map as inaccessible.
8711 This can be changed to the old behaviour by using the following GDB command
8713 set mem inaccessible-by-default off
8716 If @command{gdb_flash_program enable} is also used, GDB will be able to
8717 program any flash memory using the vFlash interface.
8719 GDB will look at the target memory map when a load command is given, if any
8720 areas to be programmed lie within the target flash area the vFlash packets
8723 If the target needs configuring before GDB programming, an event
8724 script can be executed:
8726 $_TARGETNAME configure -event EVENTNAME BODY
8729 To verify any flash programming the GDB command @option{compare-sections}
8731 @anchor{usingopenocdsmpwithgdb}
8732 @section Using OpenOCD SMP with GDB
8734 For SMP support following GDB serial protocol packet have been defined :
8736 @item j - smp status request
8737 @item J - smp set request
8740 OpenOCD implements :
8742 @item @option{jc} packet for reading core id displayed by
8743 GDB connection. Reply is @option{XXXXXXXX} (8 hex digits giving core id) or
8744 @option{E01} for target not smp.
8745 @item @option{JcXXXXXXXX} (8 hex digits) packet for setting core id displayed at next GDB continue
8746 (core id -1 is reserved for returning to normal resume mode). Reply @option{E01}
8747 for target not smp or @option{OK} on success.
8750 Handling of this packet within GDB can be done :
8752 @item by the creation of an internal variable (i.e @option{_core}) by mean
8753 of function allocate_computed_value allowing following GDB command.
8756 #Jc01 packet is sent
8758 #jc packet is sent and result is affected in $
8761 @item by the usage of GDB maintenance command as described in following example (2 cpus in SMP with
8762 core id 0 and 1 @pxref{definecputargetsworkinginsmp,,Define CPU targets working in SMP}).
8765 # toggle0 : force display of coreid 0
8771 # toggle1 : force display of coreid 1
8780 @section RTOS Support
8781 @cindex RTOS Support
8782 @anchor{gdbrtossupport}
8784 OpenOCD includes RTOS support, this will however need enabling as it defaults to disabled.
8785 It can be enabled by passing @option{-rtos} arg to the target @xref{rtostype,,RTOS Type}.
8787 @* An example setup is below:
8790 $_TARGETNAME configure -rtos auto
8793 This will attempt to auto detect the RTOS within your application.
8795 Currently supported rtos's include:
8798 @item @option{ThreadX}
8799 @item @option{FreeRTOS}
8800 @item @option{linux}
8801 @item @option{ChibiOS}
8802 @item @option{embKernel}
8807 Before an RTOS can be detected, it must export certain symbols; otherwise, it cannot
8808 be used by OpenOCD. Below is a list of the required symbols for each supported RTOS.
8813 Cyg_Thread::thread_list, Cyg_Scheduler_Base::current_thread.
8814 @item ThreadX symbols
8815 _tx_thread_current_ptr, _tx_thread_created_ptr, _tx_thread_created_count.
8816 @item FreeRTOS symbols
8817 @c The following is taken from recent texinfo to provide compatibility
8818 @c with ancient versions that do not support @raggedright
8821 \rightskip0pt plus2em \spaceskip.3333em \xspaceskip.5em\relax
8822 pxCurrentTCB, pxReadyTasksLists, xDelayedTaskList1, xDelayedTaskList2,
8823 pxDelayedTaskList, pxOverflowDelayedTaskList, xPendingReadyList,
8824 uxCurrentNumberOfTasks, uxTopUsedPriority.
8830 @item ChibiOS symbols
8831 rlist, ch_debug, chSysInit.
8832 @item embKernel symbols
8833 Rtos::sCurrentTask, Rtos::sListReady, Rtos::sListSleep,
8834 Rtos::sListSuspended, Rtos::sMaxPriorities, Rtos::sCurrentTaskCount.
8836 _mqx_kernel_data, MQX_init_struct.
8839 For most RTOS supported the above symbols will be exported by default. However for
8840 some, eg. FreeRTOS, extra steps must be taken.
8842 These RTOSes may require additional OpenOCD-specific file to be linked
8843 along with the project:
8847 contrib/rtos-helpers/FreeRTOS-openocd.c
8850 @node Tcl Scripting API
8851 @chapter Tcl Scripting API
8852 @cindex Tcl Scripting API
8856 Tcl commands are stateless; e.g. the @command{telnet} command has
8857 a concept of currently active target, the Tcl API proc's take this sort
8858 of state information as an argument to each proc.
8860 There are three main types of return values: single value, name value
8861 pair list and lists.
8863 Name value pair. The proc 'foo' below returns a name/value pair
8868 > set foo(you) Oyvind
8869 > set foo(mouse) Micky
8870 > set foo(duck) Donald
8882 me Duane you Oyvind mouse Micky duck Donald
8885 Thus, to get the names of the associative array is easy:
8888 foreach { name value } [set foo] {
8889 puts "Name: $name, Value: $value"
8893 Lists returned should be relatively small. Otherwise, a range
8894 should be passed in to the proc in question.
8896 @section Internal low-level Commands
8898 By "low-level," we mean commands that a human would typically not
8901 Some low-level commands need to be prefixed with "ocd_"; e.g.
8902 @command{ocd_flash_banks}
8903 is the low-level API upon which @command{flash banks} is implemented.
8906 @item @b{mem2array} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
8908 Read memory and return as a Tcl array for script processing
8909 @item @b{array2mem} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
8911 Convert a Tcl array to memory locations and write the values
8912 @item @b{ocd_flash_banks} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}> <@var{target}> [@option{driver options} ...]
8914 Return information about the flash banks
8916 @item @b{capture} <@var{command}>
8918 Run <@var{command}> and return full log output that was produced during
8919 its execution. Example:
8922 > capture "reset init"
8927 OpenOCD commands can consist of two words, e.g. "flash banks". The
8928 @file{startup.tcl} "unknown" proc will translate this into a Tcl proc
8929 called "flash_banks".
8931 @section OpenOCD specific Global Variables
8933 Real Tcl has ::tcl_platform(), and platform::identify, and many other
8934 variables. JimTCL, as implemented in OpenOCD creates $ocd_HOSTOS which
8935 holds one of the following values:
8938 @item @b{cygwin} Running under Cygwin
8939 @item @b{darwin} Darwin (Mac-OS) is the underlying operating sytem.
8940 @item @b{freebsd} Running under FreeBSD
8941 @item @b{openbsd} Running under OpenBSD
8942 @item @b{netbsd} Running under NetBSD
8943 @item @b{linux} Linux is the underlying operating sytem
8944 @item @b{mingw32} Running under MingW32
8945 @item @b{winxx} Built using Microsoft Visual Studio
8946 @item @b{ecos} Running under eCos
8947 @item @b{other} Unknown, none of the above.
8950 Note: 'winxx' was choosen because today (March-2009) no distinction is made between Win32 and Win64.
8953 We should add support for a variable like Tcl variable
8954 @code{tcl_platform(platform)}, it should be called
8955 @code{jim_platform} (because it
8956 is jim, not real tcl).
8959 @section Tcl RPC server
8962 OpenOCD provides a simple RPC server that allows to run arbitrary Tcl
8963 commands and receive the results.
8965 To access it, your application needs to connect to a configured TCP port
8966 (see @command{tcl_port}). Then it can pass any string to the
8967 interpreter terminating it with @code{0x1a} and wait for the return
8968 value (it will be terminated with @code{0x1a} as well). This can be
8969 repeated as many times as desired without reopening the connection.
8971 Remember that most of the OpenOCD commands need to be prefixed with
8972 @code{ocd_} to get the results back. Sometimes you might also need the
8973 @command{capture} command.
8975 See @file{contrib/rpc_examples/} for specific client implementations.
8977 @section Tcl RPC server notifications
8978 @cindex RPC Notifications
8980 Notifications are sent asynchronously to other commands being executed over
8981 the RPC server, so the port must be polled continuously.
8983 Target event, state and reset notifications are emitted as Tcl associative arrays
8984 in the following format.
8987 type target_event event [event-name]
8988 type target_state state [state-name]
8989 type target_reset mode [reset-mode]
8992 @deffn {Command} tcl_notifications [on/off]
8993 Toggle output of target notifications to the current Tcl RPC server.
8994 Only available from the Tcl RPC server.
8999 @section Tcl RPC server trace output
9000 @cindex RPC trace output
9002 Trace data is sent asynchronously to other commands being executed over
9003 the RPC server, so the port must be polled continuously.
9005 Target trace data is emitted as a Tcl associative array in the following format.
9008 type target_trace data [trace-data-hex-encoded]
9011 @deffn {Command} tcl_trace [on/off]
9012 Toggle output of target trace data to the current Tcl RPC server.
9013 Only available from the Tcl RPC server.
9016 See an example application here:
9017 @url{https://github.com/apmorton/OpenOcdTraceUtil} [OpenOcdTraceUtil]
9026 @item @b{RTCK, also known as: Adaptive Clocking - What is it?}
9028 @cindex adaptive clocking
9031 In digital circuit design it is often refered to as ``clock
9032 synchronisation'' the JTAG interface uses one clock (TCK or TCLK)
9033 operating at some speed, your CPU target is operating at another.
9034 The two clocks are not synchronised, they are ``asynchronous''
9036 In order for the two to work together they must be synchronised
9037 well enough to work; JTAG can't go ten times faster than the CPU,
9038 for example. There are 2 basic options:
9041 Use a special "adaptive clocking" circuit to change the JTAG
9042 clock rate to match what the CPU currently supports.
9044 The JTAG clock must be fixed at some speed that's enough slower than
9045 the CPU clock that all TMS and TDI transitions can be detected.
9048 @b{Does this really matter?} For some chips and some situations, this
9049 is a non-issue, like a 500MHz ARM926 with a 5 MHz JTAG link;
9050 the CPU has no difficulty keeping up with JTAG.
9051 Startup sequences are often problematic though, as are other
9052 situations where the CPU clock rate changes (perhaps to save
9055 For example, Atmel AT91SAM chips start operation from reset with
9056 a 32kHz system clock. Boot firmware may activate the main oscillator
9057 and PLL before switching to a faster clock (perhaps that 500 MHz
9059 If you're using JTAG to debug that startup sequence, you must slow
9060 the JTAG clock to sometimes 1 to 4kHz. After startup completes,
9061 JTAG can use a faster clock.
9063 Consider also debugging a 500MHz ARM926 hand held battery powered
9064 device that enters a low power ``deep sleep'' mode, at 32kHz CPU
9065 clock, between keystrokes unless it has work to do. When would
9066 that 5 MHz JTAG clock be usable?
9068 @b{Solution #1 - A special circuit}
9070 In order to make use of this,
9071 your CPU, board, and JTAG adapter must all support the RTCK
9072 feature. Not all of them support this; keep reading!
9074 The RTCK ("Return TCK") signal in some ARM chips is used to help with
9075 this problem. ARM has a good description of the problem described at
9076 this link: @url{http://www.arm.com/support/faqdev/4170.html} [checked
9077 28/nov/2008]. Link title: ``How does the JTAG synchronisation logic
9078 work? / how does adaptive clocking work?''.
9080 The nice thing about adaptive clocking is that ``battery powered hand
9081 held device example'' - the adaptiveness works perfectly all the
9082 time. One can set a break point or halt the system in the deep power
9083 down code, slow step out until the system speeds up.
9085 Note that adaptive clocking may also need to work at the board level,
9086 when a board-level scan chain has multiple chips.
9087 Parallel clock voting schemes are good way to implement this,
9088 both within and between chips, and can easily be implemented
9090 It's not difficult to have logic fan a module's input TCK signal out
9091 to each TAP in the scan chain, and then wait until each TAP's RTCK comes
9092 back with the right polarity before changing the output RTCK signal.
9093 Texas Instruments makes some clock voting logic available
9094 for free (with no support) in VHDL form; see
9095 @url{http://tiexpressdsp.com/index.php/Adaptive_Clocking}
9097 @b{Solution #2 - Always works - but may be slower}
9099 Often this is a perfectly acceptable solution.
9101 In most simple terms: Often the JTAG clock must be 1/10 to 1/12 of
9102 the target clock speed. But what that ``magic division'' is varies
9103 depending on the chips on your board.
9104 @b{ARM rule of thumb} Most ARM based systems require an 6:1 division;
9105 ARM11 cores use an 8:1 division.
9106 @b{Xilinx rule of thumb} is 1/12 the clock speed.
9108 Note: most full speed FT2232 based JTAG adapters are limited to a
9109 maximum of 6MHz. The ones using USB high speed chips (FT2232H)
9110 often support faster clock rates (and adaptive clocking).
9112 You can still debug the 'low power' situations - you just need to
9113 either use a fixed and very slow JTAG clock rate ... or else
9114 manually adjust the clock speed at every step. (Adjusting is painful
9115 and tedious, and is not always practical.)
9117 It is however easy to ``code your way around it'' - i.e.: Cheat a little,
9118 have a special debug mode in your application that does a ``high power
9119 sleep''. If you are careful - 98% of your problems can be debugged
9122 Note that on ARM you may need to avoid using the @emph{wait for interrupt}
9123 operation in your idle loops even if you don't otherwise change the CPU
9125 That operation gates the CPU clock, and thus the JTAG clock; which
9126 prevents JTAG access. One consequence is not being able to @command{halt}
9127 cores which are executing that @emph{wait for interrupt} operation.
9129 To set the JTAG frequency use the command:
9137 @item @b{Win32 Pathnames} Why don't backslashes work in Windows paths?
9139 OpenOCD uses Tcl and a backslash is an escape char. Use @{ and @}
9140 around Windows filenames.
9153 @item @b{Missing: cygwin1.dll} OpenOCD complains about a missing cygwin1.dll.
9155 Make sure you have Cygwin installed, or at least a version of OpenOCD that
9156 claims to come with all the necessary DLLs. When using Cygwin, try launching
9157 OpenOCD from the Cygwin shell.
9159 @item @b{Breakpoint Issue} I'm trying to set a breakpoint using GDB (or a frontend like Insight or
9160 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
9161 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
9163 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
9164 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720T or ARM920T,
9165 software breakpoints consume one of the two available hardware breakpoints.
9167 @item @b{LPC2000 Flash} When erasing or writing LPC2000 on-chip flash, the operation fails at random.
9169 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
9170 clock at the time you're programming the flash. If you've specified the crystal's
9171 frequency, make sure the PLL is disabled. If you've specified the full core speed
9172 (e.g. 60MHz), make sure the PLL is enabled.
9174 @item @b{Amontec Chameleon} When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
9175 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
9176 out while waiting for end of scan, rtck was disabled".
9178 Make sure your PC's parallel port operates in EPP mode. You might have to try several
9179 settings in your PC BIOS (ECP, EPP, and different versions of those).
9181 @item @b{Data Aborts} When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
9182 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
9183 memory read caused data abort".
9185 The errors are non-fatal, and are the result of GDB trying to trace stack frames
9186 beyond the last valid frame. It might be possible to prevent this by setting up
9187 a proper "initial" stack frame, if you happen to know what exactly has to
9188 be done, feel free to add this here.
9190 @b{Simple:} In your startup code - push 8 registers of zeros onto the
9191 stack before calling main(). What GDB is doing is ``climbing'' the run
9192 time stack by reading various values on the stack using the standard
9193 call frame for the target. GDB keeps going - until one of 2 things
9194 happen @b{#1} an invalid frame is found, or @b{#2} some huge number of
9195 stackframes have been processed. By pushing zeros on the stack, GDB
9198 @b{Debugging Interrupt Service Routines} - In your ISR before you call
9199 your C code, do the same - artifically push some zeros onto the stack,
9200 remember to pop them off when the ISR is done.
9202 @b{Also note:} If you have a multi-threaded operating system, they
9203 often do not @b{in the intrest of saving memory} waste these few
9207 @item @b{JTAG Reset Config} I get the following message in the OpenOCD console (or log file):
9208 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
9210 This warning doesn't indicate any serious problem, as long as you don't want to
9211 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
9212 trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
9213 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
9214 independently. With this setup, it's not possible to halt the core right out of
9215 reset, everything else should work fine.
9217 @item @b{USB Power} When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
9218 toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
9219 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
9220 quit with an error message. Is there a stability issue with OpenOCD?
9222 No, this is not a stability issue concerning OpenOCD. Most users have solved
9223 this issue by simply using a self-powered USB hub, which they connect their
9224 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
9225 supply stable enough for the Amontec JTAGkey to be operated.
9227 @b{Laptops running on battery have this problem too...}
9229 @item @b{USB Power} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
9230 following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
9231 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
9232 What does that mean and what might be the reason for this?
9234 First of all, the reason might be the USB power supply. Try using a self-powered
9235 hub instead of a direct connection to your computer. Secondly, the error code 4
9236 corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
9237 chip ran into some sort of error - this points us to a USB problem.
9239 @item @b{GDB Disconnects} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
9240 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
9241 What does that mean and what might be the reason for this?
9243 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
9244 has closed the connection to OpenOCD. This might be a GDB issue.
9246 @item @b{LPC2000 Flash} In the configuration file in the section where flash device configurations
9247 are described, there is a parameter for specifying the clock frequency
9248 for LPC2000 internal flash devices (e.g. @option{flash bank $_FLASHNAME lpc2000
9249 0x0 0x40000 0 0 $_TARGETNAME lpc2000_v1 14746 calc_checksum}), which must be
9250 specified in kilohertz. However, I do have a quartz crystal of a
9251 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz,
9252 i.e. 14,745.600 kHz). Is it possible to specify real numbers for the
9255 No. The clock frequency specified here must be given as an integral number.
9256 However, this clock frequency is used by the In-Application-Programming (IAP)
9257 routines of the LPC2000 family only, which seems to be very tolerant concerning
9258 the given clock frequency, so a slight difference between the specified clock
9259 frequency and the actual clock frequency will not cause any trouble.
9261 @item @b{Command Order} Do I have to keep a specific order for the commands in the configuration file?
9263 Well, yes and no. Commands can be given in arbitrary order, yet the
9264 devices listed for the JTAG scan chain must be given in the right
9265 order (jtag newdevice), with the device closest to the TDO-Pin being
9266 listed first. In general, whenever objects of the same type exist
9267 which require an index number, then these objects must be given in the
9268 right order (jtag newtap, targets and flash banks - a target
9269 references a jtag newtap and a flash bank references a target).
9271 You can use the ``scan_chain'' command to verify and display the tap order.
9273 Also, some commands can't execute until after @command{init} has been
9274 processed. Such commands include @command{nand probe} and everything
9275 else that needs to write to controller registers, perhaps for setting
9276 up DRAM and loading it with code.
9278 @anchor{faqtaporder}
9279 @item @b{JTAG TAP Order} Do I have to declare the TAPS in some
9282 Yes; whenever you have more than one, you must declare them in
9283 the same order used by the hardware.
9285 Many newer devices have multiple JTAG TAPs. For example: ST
9286 Microsystems STM32 chips have two TAPs, a ``boundary scan TAP'' and
9287 ``Cortex-M3'' TAP. Example: The STM32 reference manual, Document ID:
9288 RM0008, Section 26.5, Figure 259, page 651/681, the ``TDI'' pin is
9289 connected to the boundary scan TAP, which then connects to the
9290 Cortex-M3 TAP, which then connects to the TDO pin.
9292 Thus, the proper order for the STM32 chip is: (1) The Cortex-M3, then
9293 (2) The boundary scan TAP. If your board includes an additional JTAG
9294 chip in the scan chain (for example a Xilinx CPLD or FPGA) you could
9295 place it before or after the STM32 chip in the chain. For example:
9298 @item OpenOCD_TDI(output) -> STM32 TDI Pin (BS Input)
9299 @item STM32 BS TDO (output) -> STM32 Cortex-M3 TDI (input)
9300 @item STM32 Cortex-M3 TDO (output) -> SM32 TDO Pin
9301 @item STM32 TDO Pin (output) -> Xilinx TDI Pin (input)
9302 @item Xilinx TDO Pin -> OpenOCD TDO (input)
9305 The ``jtag device'' commands would thus be in the order shown below. Note:
9308 @item jtag newtap Xilinx tap -irlen ...
9309 @item jtag newtap stm32 cpu -irlen ...
9310 @item jtag newtap stm32 bs -irlen ...
9311 @item # Create the debug target and say where it is
9312 @item target create stm32.cpu -chain-position stm32.cpu ...
9316 @item @b{SYSCOMP} Sometimes my debugging session terminates with an error. When I look into the
9317 log file, I can see these error messages: Error: arm7_9_common.c:561
9318 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP
9324 @node Tcl Crash Course
9325 @chapter Tcl Crash Course
9328 Not everyone knows Tcl - this is not intended to be a replacement for
9329 learning Tcl, the intent of this chapter is to give you some idea of
9330 how the Tcl scripts work.
9332 This chapter is written with two audiences in mind. (1) OpenOCD users
9333 who need to understand a bit more of how Jim-Tcl works so they can do
9334 something useful, and (2) those that want to add a new command to
9337 @section Tcl Rule #1
9338 There is a famous joke, it goes like this:
9340 @item Rule #1: The wife is always correct
9341 @item Rule #2: If you think otherwise, See Rule #1
9344 The Tcl equal is this:
9347 @item Rule #1: Everything is a string
9348 @item Rule #2: If you think otherwise, See Rule #1
9351 As in the famous joke, the consequences of Rule #1 are profound. Once
9352 you understand Rule #1, you will understand Tcl.
9354 @section Tcl Rule #1b
9355 There is a second pair of rules.
9357 @item Rule #1: Control flow does not exist. Only commands
9358 @* For example: the classic FOR loop or IF statement is not a control
9359 flow item, they are commands, there is no such thing as control flow
9361 @item Rule #2: If you think otherwise, See Rule #1
9362 @* Actually what happens is this: There are commands that by
9363 convention, act like control flow key words in other languages. One of
9364 those commands is the word ``for'', another command is ``if''.
9367 @section Per Rule #1 - All Results are strings
9368 Every Tcl command results in a string. The word ``result'' is used
9369 deliberatly. No result is just an empty string. Remember: @i{Rule #1 -
9370 Everything is a string}
9372 @section Tcl Quoting Operators
9373 In life of a Tcl script, there are two important periods of time, the
9374 difference is subtle.
9377 @item Evaluation Time
9380 The two key items here are how ``quoted things'' work in Tcl. Tcl has
9381 three primary quoting constructs, the [square-brackets] the
9382 @{curly-braces@} and ``double-quotes''
9384 By now you should know $VARIABLES always start with a $DOLLAR
9385 sign. BTW: To set a variable, you actually use the command ``set'', as
9386 in ``set VARNAME VALUE'' much like the ancient BASIC langauge ``let x
9387 = 1'' statement, but without the equal sign.
9390 @item @b{[square-brackets]}
9391 @* @b{[square-brackets]} are command substitutions. It operates much
9392 like Unix Shell `back-ticks`. The result of a [square-bracket]
9393 operation is exactly 1 string. @i{Remember Rule #1 - Everything is a
9394 string}. These two statements are roughly identical:
9398 echo "The Date is: $X"
9401 puts "The Date is: $X"
9403 @item @b{``double-quoted-things''}
9404 @* @b{``double-quoted-things''} are just simply quoted
9405 text. $VARIABLES and [square-brackets] are expanded in place - the
9406 result however is exactly 1 string. @i{Remember Rule #1 - Everything
9410 puts "It is now \"[date]\", $x is in 1 hour"
9412 @item @b{@{Curly-Braces@}}
9413 @*@b{@{Curly-Braces@}} are magic: $VARIABLES and [square-brackets] are
9414 parsed, but are NOT expanded or executed. @{Curly-Braces@} are like
9415 'single-quote' operators in BASH shell scripts, with the added
9416 feature: @{curly-braces@} can be nested, single quotes can not. @{@{@{this is
9417 nested 3 times@}@}@} NOTE: [date] is a bad example;
9418 at this writing, Jim/OpenOCD does not have a date command.
9421 @section Consequences of Rule 1/2/3/4
9423 The consequences of Rule 1 are profound.
9425 @subsection Tokenisation & Execution.
9427 Of course, whitespace, blank lines and #comment lines are handled in
9430 As a script is parsed, each (multi) line in the script file is
9431 tokenised and according to the quoting rules. After tokenisation, that
9432 line is immedatly executed.
9434 Multi line statements end with one or more ``still-open''
9435 @{curly-braces@} which - eventually - closes a few lines later.
9437 @subsection Command Execution
9439 Remember earlier: There are no ``control flow''
9440 statements in Tcl. Instead there are COMMANDS that simply act like
9441 control flow operators.
9443 Commands are executed like this:
9446 @item Parse the next line into (argc) and (argv[]).
9447 @item Look up (argv[0]) in a table and call its function.
9448 @item Repeat until End Of File.
9451 It sort of works like this:
9454 ReadAndParse( &argc, &argv );
9456 cmdPtr = LookupCommand( argv[0] );
9458 (*cmdPtr->Execute)( argc, argv );
9462 When the command ``proc'' is parsed (which creates a procedure
9463 function) it gets 3 parameters on the command line. @b{1} the name of
9464 the proc (function), @b{2} the list of parameters, and @b{3} the body
9465 of the function. Not the choice of words: LIST and BODY. The PROC
9466 command stores these items in a table somewhere so it can be found by
9469 @subsection The FOR command
9471 The most interesting command to look at is the FOR command. In Tcl,
9472 the FOR command is normally implemented in C. Remember, FOR is a
9473 command just like any other command.
9475 When the ascii text containing the FOR command is parsed, the parser
9476 produces 5 parameter strings, @i{(If in doubt: Refer to Rule #1)} they
9480 @item The ascii text 'for'
9481 @item The start text
9482 @item The test expression
9487 Sort of reminds you of ``main( int argc, char **argv )'' does it not?
9488 Remember @i{Rule #1 - Everything is a string.} The key point is this:
9489 Often many of those parameters are in @{curly-braces@} - thus the
9490 variables inside are not expanded or replaced until later.
9492 Remember that every Tcl command looks like the classic ``main( argc,
9493 argv )'' function in C. In JimTCL - they actually look like this:
9497 MyCommand( Jim_Interp *interp,
9499 Jim_Obj * const *argvs );
9502 Real Tcl is nearly identical. Although the newer versions have
9503 introduced a byte-code parser and intepreter, but at the core, it
9504 still operates in the same basic way.
9506 @subsection FOR command implementation
9508 To understand Tcl it is perhaps most helpful to see the FOR
9509 command. Remember, it is a COMMAND not a control flow structure.
9511 In Tcl there are two underlying C helper functions.
9513 Remember Rule #1 - You are a string.
9515 The @b{first} helper parses and executes commands found in an ascii
9516 string. Commands can be seperated by semicolons, or newlines. While
9517 parsing, variables are expanded via the quoting rules.
9519 The @b{second} helper evaluates an ascii string as a numerical
9520 expression and returns a value.
9522 Here is an example of how the @b{FOR} command could be
9523 implemented. The pseudo code below does not show error handling.
9525 void Execute_AsciiString( void *interp, const char *string );
9527 int Evaluate_AsciiExpression( void *interp, const char *string );
9530 MyForCommand( void *interp,
9535 SetResult( interp, "WRONG number of parameters");
9539 // argv[0] = the ascii string just like C
9541 // Execute the start statement.
9542 Execute_AsciiString( interp, argv[1] );
9546 i = Evaluate_AsciiExpression(interp, argv[2]);
9551 Execute_AsciiString( interp, argv[3] );
9553 // Execute the LOOP part
9554 Execute_AsciiString( interp, argv[4] );
9558 SetResult( interp, "" );
9563 Every other command IF, WHILE, FORMAT, PUTS, EXPR, everything works
9564 in the same basic way.
9566 @section OpenOCD Tcl Usage
9568 @subsection source and find commands
9569 @b{Where:} In many configuration files
9570 @* Example: @b{ source [find FILENAME] }
9571 @*Remember the parsing rules
9573 @item The @command{find} command is in square brackets,
9574 and is executed with the parameter FILENAME. It should find and return
9575 the full path to a file with that name; it uses an internal search path.
9576 The RESULT is a string, which is substituted into the command line in
9577 place of the bracketed @command{find} command.
9578 (Don't try to use a FILENAME which includes the "#" character.
9579 That character begins Tcl comments.)
9580 @item The @command{source} command is executed with the resulting filename;
9581 it reads a file and executes as a script.
9583 @subsection format command
9584 @b{Where:} Generally occurs in numerous places.
9585 @* Tcl has no command like @b{printf()}, instead it has @b{format}, which is really more like
9591 puts [format "The answer: %d" [expr $x * $y]]
9594 @item The SET command creates 2 variables, X and Y.
9595 @item The double [nested] EXPR command performs math
9596 @* The EXPR command produces numerical result as a string.
9598 @item The format command is executed, producing a single string
9599 @* Refer to Rule #1.
9600 @item The PUTS command outputs the text.
9602 @subsection Body or Inlined Text
9603 @b{Where:} Various TARGET scripts.
9606 proc someproc @{@} @{
9607 ... multiple lines of stuff ...
9609 $_TARGETNAME configure -event FOO someproc
9610 #2 Good - no variables
9611 $_TARGETNAME confgure -event foo "this ; that;"
9612 #3 Good Curly Braces
9613 $_TARGETNAME configure -event FOO @{
9616 #4 DANGER DANGER DANGER
9617 $_TARGETNAME configure -event foo "puts \"Time: [date]\""
9620 @item The $_TARGETNAME is an OpenOCD variable convention.
9621 @*@b{$_TARGETNAME} represents the last target created, the value changes
9622 each time a new target is created. Remember the parsing rules. When
9623 the ascii text is parsed, the @b{$_TARGETNAME} becomes a simple string,
9624 the name of the target which happens to be a TARGET (object)
9626 @item The 2nd parameter to the @option{-event} parameter is a TCBODY
9627 @*There are 4 examples:
9629 @item The TCLBODY is a simple string that happens to be a proc name
9630 @item The TCLBODY is several simple commands seperated by semicolons
9631 @item The TCLBODY is a multi-line @{curly-brace@} quoted string
9632 @item The TCLBODY is a string with variables that get expanded.
9635 In the end, when the target event FOO occurs the TCLBODY is
9636 evaluated. Method @b{#1} and @b{#2} are functionally identical. For
9637 Method @b{#3} and @b{#4} it is more interesting. What is the TCLBODY?
9639 Remember the parsing rules. In case #3, @{curly-braces@} mean the
9640 $VARS and [square-brackets] are expanded later, when the EVENT occurs,
9641 and the text is evaluated. In case #4, they are replaced before the
9642 ``Target Object Command'' is executed. This occurs at the same time
9643 $_TARGETNAME is replaced. In case #4 the date will never
9644 change. @{BTW: [date] is a bad example; at this writing,
9645 Jim/OpenOCD does not have a date command@}
9647 @subsection Global Variables
9648 @b{Where:} You might discover this when writing your own procs @* In
9649 simple terms: Inside a PROC, if you need to access a global variable
9650 you must say so. See also ``upvar''. Example:
9652 proc myproc @{ @} @{
9653 set y 0 #Local variable Y
9654 global x #Global variable X
9655 puts [format "X=%d, Y=%d" $x $y]
9658 @section Other Tcl Hacks
9659 @b{Dynamic variable creation}
9661 # Dynamically create a bunch of variables.
9662 for @{ set x 0 @} @{ $x < 32 @} @{ set x [expr $x + 1]@} @{
9664 set vn [format "BIT%d" $x]
9668 set $vn [expr (1 << $x)]
9671 @b{Dynamic proc/command creation}
9673 # One "X" function - 5 uart functions.
9674 foreach who @{A B C D E@}
9675 proc [format "show_uart%c" $who] @{ @} "show_UARTx $who"
9681 @node OpenOCD Concept Index
9682 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
9683 @comment case issue with ``Index.html'' and ``index.html''
9684 @comment Occurs when creating ``--html --no-split'' output
9685 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
9686 @unnumbered OpenOCD Concept Index
9690 @node Command and Driver Index
9691 @unnumbered Command and Driver Index