1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
7 * OpenOCD: (openocd). OpenOCD User's Guide
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009 David Brownell
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
40 @titlefont{@emph{Open On-Chip Debugger:}}
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
47 @vskip 0pt plus 1filll
56 @top OpenOCD User's Guide
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developers
64 * JTAG Hardware Dongles:: JTAG Hardware Dongles
65 * About JIM-Tcl:: About JIM-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Translating Configuration Files:: Translating Configuration Files
70 * Daemon Configuration:: Daemon Configuration
71 * Interface - Dongle Configuration:: Interface - Dongle Configuration
72 * Reset Configuration:: Reset Configuration
73 * TAP Declaration:: TAP Declaration
74 * CPU Configuration:: CPU Configuration
75 * Flash Commands:: Flash Commands
76 * NAND Flash Commands:: NAND Flash Commands
77 * PLD/FPGA Commands:: PLD/FPGA Commands
78 * General Commands:: General Commands
79 * Architecture and Core Commands:: Architecture and Core Commands
80 * JTAG Commands:: JTAG Commands
81 * Boundary Scan Commands:: Boundary Scan Commands
83 * GDB and OpenOCD:: Using GDB and OpenOCD
84 * Tcl Scripting API:: Tcl Scripting API
85 * Upgrading:: Deprecated/Removed Commands
86 * FAQ:: Frequently Asked Questions
87 * Tcl Crash Course:: Tcl Crash Course
88 * License:: GNU Free Documentation License
90 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
91 @comment case issue with ``Index.html'' and ``index.html''
92 @comment Occurs when creating ``--html --no-split'' output
93 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
94 * OpenOCD Concept Index:: Concept Index
95 * Command and Driver Index:: Command and Driver Index
102 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
103 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
104 Since that time, the project has grown into an active open-source project,
105 supported by a diverse community of software and hardware developers from
108 @section What is OpenOCD?
112 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
113 in-system programming and boundary-scan testing for embedded target
116 @b{JTAG:} OpenOCD uses a ``hardware interface dongle'' to communicate
117 with the JTAG (IEEE 1149.1) compliant TAPs on your target board.
118 A @dfn{TAP} is a ``Test Access Port'', a module which processes
119 special instructions and data. TAPs are daisy-chained within and
120 between chips and boards.
122 @b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
123 based, parallel port based, and other standalone boxes that run
124 OpenOCD internally. @xref{JTAG Hardware Dongles}.
126 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
127 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
128 Cortex-M3 (Stellaris LM3 and ST STM32) based cores to be
129 debugged via the GDB protocol.
131 @b{Flash Programing:} Flash writing is supported for external CFI
132 compatible NOR flashes (Intel and AMD/Spansion command set) and several
133 internal flashes (LPC1700, LPC2000, AT91SAM7, AT91SAM3U, STR7x, STR9x, LM3, and
134 STM32x). Preliminary support for various NAND flash controllers
135 (LPC3180, Orion, S3C24xx, more) controller is included.
137 @section OpenOCD Web Site
139 The OpenOCD web site provides the latest public news from the community:
141 @uref{http://openocd.berlios.de/web/}
143 @section Latest User's Guide:
145 The user's guide you are now reading may not be the latest one
146 available. A version for more recent code may be available.
147 Its HTML form is published irregularly at:
149 @uref{http://openocd.berlios.de/doc/html/index.html}
151 PDF form is likewise published at:
153 @uref{http://openocd.berlios.de/doc/pdf/openocd.pdf}
155 @section OpenOCD User's Forum
157 There is an OpenOCD forum (phpBB) hosted by SparkFun:
159 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
163 @chapter OpenOCD Developer Resources
166 If you are interested in improving the state of OpenOCD's debugging and
167 testing support, new contributions will be welcome. Motivated developers
168 can produce new target, flash or interface drivers, improve the
169 documentation, as well as more conventional bug fixes and enhancements.
171 The resources in this chapter are available for developers wishing to explore
172 or expand the OpenOCD source code.
174 @section OpenOCD GIT Repository
176 During the 0.3.x release cycle, OpenOCD switched from Subversion to
177 a GIT repository hosted at SourceForge. The repository URL is:
179 @uref{git://openocd.git.sourceforge.net/gitroot/openocd/openocd}
181 You may prefer to use a mirror and the HTTP protocol:
183 @uref{http://repo.or.cz/r/openocd.git}
185 With standard GIT tools, use @command{git clone} to initialize
186 a local repository, and @command{git pull} to update it.
187 There are also gitweb pages letting you browse the repository
188 with a web browser, or download arbitrary snapshots without
189 needing a GIT client:
191 @uref{http://openocd.git.sourceforge.net/git/gitweb.cgi?p=openocd/openocd}
193 @uref{http://repo.or.cz/w/openocd.git}
195 The @file{README} file contains the instructions for building the project
196 from the repository or a snapshot.
198 Developers that want to contribute patches to the OpenOCD system are
199 @b{strongly} encouraged to work against mainline.
200 Patches created against older versions may require additional
201 work from their submitter in order to be updated for newer releases.
203 @section Doxygen Developer Manual
205 During the 0.2.x release cycle, the OpenOCD project began
206 providing a Doxygen reference manual. This document contains more
207 technical information about the software internals, development
208 processes, and similar documentation:
210 @uref{http://openocd.berlios.de/doc/doxygen/index.html}
212 This document is a work-in-progress, but contributions would be welcome
213 to fill in the gaps. All of the source files are provided in-tree,
214 listed in the Doxyfile configuration in the top of the source tree.
216 @section OpenOCD Developer Mailing List
218 The OpenOCD Developer Mailing List provides the primary means of
219 communication between developers:
221 @uref{https://lists.berlios.de/mailman/listinfo/openocd-development}
223 Discuss and submit patches to this list.
224 The @file{PATCHES} file contains basic information about how
228 @node JTAG Hardware Dongles
229 @chapter JTAG Hardware Dongles
238 Defined: @b{dongle}: A small device that plugins into a computer and serves as
239 an adapter .... [snip]
241 In the OpenOCD case, this generally refers to @b{a small adapater} one
242 attaches to your computer via USB or the Parallel Printer Port. The
243 execption being the Zylin ZY1000 which is a small box you attach via
244 an ethernet cable. The Zylin ZY1000 has the advantage that it does not
245 require any drivers to be installed on the developer PC. It also has
246 a built in web interface. It supports RTCK/RCLK or adaptive clocking
247 and has a built in relay to power cycle targets remotely.
250 @section Choosing a Dongle
252 There are several things you should keep in mind when choosing a dongle.
255 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
256 Does your dongle support it? You might need a level converter.
257 @item @b{Pinout} What pinout does your target board use?
258 Does your dongle support it? You may be able to use jumper
259 wires, or an "octopus" connector, to convert pinouts.
260 @item @b{Connection} Does your computer have the USB, printer, or
261 Ethernet port needed?
262 @item @b{RTCK} Do you require RTCK? Also known as ``adaptive clocking''
265 @section Stand alone Systems
267 @b{ZY1000} See: @url{http://www.zylin.com/zy1000.html} Technically, not a
268 dongle, but a standalone box. The ZY1000 has the advantage that it does
269 not require any drivers installed on the developer PC. It also has
270 a built in web interface. It supports RTCK/RCLK or adaptive clocking
271 and has a built in relay to power cycle targets remotely.
273 @section USB FT2232 Based
275 There are many USB JTAG dongles on the market, many of them are based
276 on a chip from ``Future Technology Devices International'' (FTDI)
277 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
278 See: @url{http://www.ftdichip.com} for more information.
279 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
280 chips are starting to become available in JTAG adapters.
284 @* Link @url{http://www.hs-augsburg.de/~hhoegl/proj/usbjtag/usbjtag.html}
286 @* See: @url{http://www.amontec.com/jtagkey.shtml}
288 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
290 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
292 @* See: @url{http://www.signalyzer.com}
293 @item @b{evb_lm3s811}
294 @* See: @url{http://www.luminarymicro.com} - The Stellaris LM3S811 eval board has an FTD2232C chip built in.
295 @item @b{luminary_icdi}
296 @* See: @url{http://www.luminarymicro.com} - Luminary In-Circuit Debug Interface (ICDI) Board, included in the Stellaris LM3S9B90 and LM3S9B92 Evaluation Kits.
297 @item @b{olimex-jtag}
298 @* See: @url{http://www.olimex.com}
300 @* See: @url{http://www.tincantools.com}
301 @item @b{turtelizer2}
303 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
304 @url{http://www.ethernut.de}
306 @* Link: @url{http://www.hitex.com/index.php?id=383}
308 @* Link @url{http://www.hitex.com/stm32-stick}
309 @item @b{axm0432_jtag}
310 @* Axiom AXM-0432 Link @url{http://www.axman.com}
312 @* Link @url{http://www.hitex.com/index.php?id=cortino}
315 @section USB JLINK based
316 There are several OEM versions of the Segger @b{JLINK} adapter. It is
317 an example of a micro controller based JTAG adapter, it uses an
318 AT91SAM764 internally.
321 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
322 @* Link: @url{http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3892}
323 @item @b{SEGGER JLINK}
324 @* Link: @url{http://www.segger.com/jlink.html}
326 @* Link: @url{http://www.iar.com/website1/1.0.1.0/369/1/index.php}
329 @section USB RLINK based
330 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer, permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for SWD and not JTAG, thus not supported.
333 @item @b{Raisonance RLink}
334 @* Link: @url{http://www.raisonance.com/products/RLink.php}
335 @item @b{STM32 Primer}
336 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
337 @item @b{STM32 Primer2}
338 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
344 @* Link: @url{http://www.embedded-projects.net/usbprog} - which uses an Atmel MEGA32 and a UBN9604
346 @item @b{USB - Presto}
347 @* Link: @url{http://tools.asix.net/prg_presto.htm}
349 @item @b{Versaloon-Link}
350 @* Link: @url{http://www.simonqian.com/en/Versaloon}
352 @item @b{ARM-JTAG-EW}
353 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
356 @section IBM PC Parallel Printer Port Based
358 The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
359 and the MacGraigor Wiggler. There are many clones and variations of
362 Note that parallel ports are becoming much less common, so if you
363 have the choice you should probably avoid these adapters in favor
368 @item @b{Wiggler} - There are many clones of this.
369 @* Link: @url{http://www.macraigor.com/wiggler.htm}
371 @item @b{DLC5} - From XILINX - There are many clones of this
372 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
373 produced, PDF schematics are easily found and it is easy to make.
375 @item @b{Amontec - JTAG Accelerator}
376 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
379 @* Link: @url{http://www.gateworks.com/products/avila_accessories/gw16042.php}
382 @*@uref{http://www.ccac.rwth-aachen.de/@/~michaels/@/index.php/hardware/@/armjtag,
383 Improved parallel-port wiggler-style JTAG adapter}
385 @item @b{Wiggler_ntrst_inverted}
386 @* Yet another variation - See the source code, src/jtag/parport.c
388 @item @b{old_amt_wiggler}
389 @* Unknown - probably not on the market today
392 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
395 @* Link: @url{http://www.amontec.com/chameleon.shtml}
401 @* ispDownload from Lattice Semiconductor
402 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
405 @* From ST Microsystems;
406 @uref{http://www.st.com/stonline/@/products/literature/um/7889.pdf,
407 FlashLINK JTAG programing cable for PSD and uPSD}
415 @* An EP93xx based Linux machine using the GPIO pins directly.
418 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
423 @chapter About JIM-Tcl
427 OpenOCD includes a small ``Tcl Interpreter'' known as JIM-Tcl.
428 This programming language provides a simple and extensible
431 All commands presented in this Guide are extensions to JIM-Tcl.
432 You can use them as simple commands, without needing to learn
433 much of anything about Tcl.
434 Alternatively, can write Tcl programs with them.
436 You can learn more about JIM at its website, @url{http://jim.berlios.de}.
439 @item @b{JIM vs. Tcl}
440 @* JIM-TCL is a stripped down version of the well known Tcl language,
441 which can be found here: @url{http://www.tcl.tk}. JIM-Tcl has far
442 fewer features. JIM-Tcl is a single .C file and a single .H file and
443 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
444 4.2 MB .zip file containing 1540 files.
446 @item @b{Missing Features}
447 @* Our practice has been: Add/clone the real Tcl feature if/when
448 needed. We welcome JIM Tcl improvements, not bloat.
451 @* OpenOCD configuration scripts are JIM Tcl Scripts. OpenOCD's
452 command interpreter today is a mixture of (newer)
453 JIM-Tcl commands, and (older) the orginal command interpreter.
456 @* At the OpenOCD telnet command line (or via the GDB mon command) one
457 can type a Tcl for() loop, set variables, etc.
458 Some of the commands documented in this guide are implemented
459 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
461 @item @b{Historical Note}
462 @* JIM-Tcl was introduced to OpenOCD in spring 2008.
464 @item @b{Need a crash course in Tcl?}
465 @*@xref{Tcl Crash Course}.
470 @cindex command line options
472 @cindex directory search
474 The @option{--help} option shows:
478 --help | -h display this help
479 --version | -v display OpenOCD version
480 --file | -f use configuration file <name>
481 --search | -s dir to search for config files and scripts
482 --debug | -d set debug level <0-3>
483 --log_output | -l redirect log output to file <name>
484 --command | -c run <command>
485 --pipe | -p use pipes when talking to gdb
488 By default OpenOCD reads the file configuration file @file{openocd.cfg}
489 in the current directory. To specify a different (or multiple)
490 configuration file, you can use the ``-f'' option. For example:
493 openocd -f config1.cfg -f config2.cfg -f config3.cfg
496 OpenOCD starts by processing the configuration commands provided
497 on the command line or in @file{openocd.cfg}.
498 @xref{Configuration Stage}.
499 At the end of the configuration stage it verifies the JTAG scan
500 chain defined using those commands; your configuration should
501 ensure that this always succeeds.
502 Normally, OpenOCD then starts running as a daemon.
503 Alternatively, commands may be used to terminate the configuration
504 stage early, perform work (such as updating some flash memory),
505 and then shut down without acting as a daemon.
507 Once OpenOCD starts running as a daemon, it waits for connections from
508 clients (Telnet, GDB, Other) and processes the commands issued through
511 If you are having problems, you can enable internal debug messages via
514 Also it is possible to interleave JIM-Tcl commands w/config scripts using the
515 @option{-c} command line switch.
517 To enable debug output (when reporting problems or working on OpenOCD
518 itself), use the @option{-d} command line switch. This sets the
519 @option{debug_level} to "3", outputting the most information,
520 including debug messages. The default setting is "2", outputting only
521 informational messages, warnings and errors. You can also change this
522 setting from within a telnet or gdb session using @command{debug_level
523 <n>} (@pxref{debug_level}).
525 You can redirect all output from the daemon to a file using the
526 @option{-l <logfile>} switch.
528 Search paths for config/script files can be added to OpenOCD by using
529 the @option{-s <search>} switch. The current directory and the OpenOCD
530 target library is in the search path by default.
532 For details on the @option{-p} option. @xref{Connecting to GDB}.
534 Note! OpenOCD will launch the GDB & telnet server even if it can not
535 establish a connection with the target. In general, it is possible for
536 the JTAG controller to be unresponsive until the target is set up
537 correctly via e.g. GDB monitor commands in a GDB init script.
539 @node OpenOCD Project Setup
540 @chapter OpenOCD Project Setup
542 To use OpenOCD with your development projects, you need to do more than
543 just connecting the JTAG adapter hardware (dongle) to your development board
544 and then starting the OpenOCD server.
545 You also need to configure that server so that it knows
546 about that adapter and board, and helps your work.
548 @section Hooking up the JTAG Adapter
550 Today's most common case is a dongle with a JTAG cable on one side
551 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
552 and a USB cable on the other.
553 Instead of USB, some cables use Ethernet;
554 older ones may use a PC parallel port, or even a serial port.
557 @item @emph{Start with power to your target board turned off},
558 and nothing connected to your JTAG adapter.
559 If you're particularly paranoid, unplug power to the board.
560 It's important to have the ground signal properly set up,
561 unless you are using a JTAG adapter which provides
562 galvanic isolation between the target board and the
565 @item @emph{Be sure it's the right kind of JTAG connector.}
566 If your dongle has a 20-pin ARM connector, you need some kind
567 of adapter (or octopus, see below) to hook it up to
568 boards using 14-pin or 10-pin connectors ... or to 20-pin
569 connectors which don't use ARM's pinout.
571 In the same vein, make sure the voltage levels are compatible.
572 Not all JTAG adapters have the level shifters needed to work
573 with 1.2 Volt boards.
575 @item @emph{Be certain the cable is properly oriented} or you might
576 damage your board. In most cases there are only two possible
577 ways to connect the cable.
578 Connect the JTAG cable from your adapter to the board.
579 Be sure it's firmly connected.
581 In the best case, the connector is keyed to physically
582 prevent you from inserting it wrong.
583 This is most often done using a slot on the board's male connector
584 housing, which must match a key on the JTAG cable's female connector.
585 If there's no housing, then you must look carefully and
586 make sure pin 1 on the cable hooks up to pin 1 on the board.
587 Ribbon cables are frequently all grey except for a wire on one
588 edge, which is red. The red wire is pin 1.
590 Sometimes dongles provide cables where one end is an ``octopus'' of
591 color coded single-wire connectors, instead of a connector block.
592 These are great when converting from one JTAG pinout to another,
593 but are tedious to set up.
594 Use these with connector pinout diagrams to help you match up the
595 adapter signals to the right board pins.
597 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
598 A USB, parallel, or serial port connector will go to the host which
599 you are using to run OpenOCD.
600 For Ethernet, consult the documentation and your network administrator.
602 For USB based JTAG adapters you have an easy sanity check at this point:
603 does the host operating system see the JTAG adapter?
605 @item @emph{Connect the adapter's power supply, if needed.}
606 This step is primarily for non-USB adapters,
607 but sometimes USB adapters need extra power.
609 @item @emph{Power up the target board.}
610 Unless you just let the magic smoke escape,
611 you're now ready to set up the OpenOCD server
612 so you can use JTAG to work with that board.
616 Talk with the OpenOCD server using
617 telnet (@code{telnet localhost 4444} on many systems) or GDB.
618 @xref{GDB and OpenOCD}.
620 @section Project Directory
622 There are many ways you can configure OpenOCD and start it up.
624 A simple way to organize them all involves keeping a
625 single directory for your work with a given board.
626 When you start OpenOCD from that directory,
627 it searches there first for configuration files, scripts,
628 and for code you upload to the target board.
629 It is also the natural place to write files,
630 such as log files and data you download from the board.
632 @section Configuration Basics
634 There are two basic ways of configuring OpenOCD, and
635 a variety of ways you can mix them.
636 Think of the difference as just being how you start the server:
639 @item Many @option{-f file} or @option{-c command} options on the command line
640 @item No options, but a @dfn{user config file}
641 in the current directory named @file{openocd.cfg}
644 Here is an example @file{openocd.cfg} file for a setup
645 using a Signalyzer FT2232-based JTAG adapter to talk to
646 a board with an Atmel AT91SAM7X256 microcontroller:
649 source [find interface/signalyzer.cfg]
651 # GDB can also flash my flash!
652 gdb_memory_map enable
653 gdb_flash_program enable
655 source [find target/sam7x256.cfg]
658 Here is the command line equivalent of that configuration:
661 openocd -f interface/signalyzer.cfg \
662 -c "gdb_memory_map enable" \
663 -c "gdb_flash_program enable" \
664 -f target/sam7x256.cfg
667 You could wrap such long command lines in shell scripts,
668 each supporting a different development task.
669 One might re-flash the board with a specific firmware version.
670 Another might set up a particular debugging or run-time environment.
673 At this writing (October 2009) the command line method has
674 problems with how it treats variables.
675 For example, after @option{-c "set VAR value"}, or doing the
676 same in a script, the variable @var{VAR} will have no value
677 that can be tested in a later script.
680 Here we will focus on the simpler solution: one user config
681 file, including basic configuration plus any TCL procedures
682 to simplify your work.
684 @section User Config Files
685 @cindex config file, user
686 @cindex user config file
687 @cindex config file, overview
689 A user configuration file ties together all the parts of a project
691 One of the following will match your situation best:
694 @item Ideally almost everything comes from configuration files
695 provided by someone else.
696 For example, OpenOCD distributes a @file{scripts} directory
697 (probably in @file{/usr/share/openocd/scripts} on Linux).
698 Board and tool vendors can provide these too, as can individual
699 user sites; the @option{-s} command line option lets you say
700 where to find these files. (@xref{Running}.)
701 The AT91SAM7X256 example above works this way.
703 Three main types of non-user configuration file each have their
704 own subdirectory in the @file{scripts} directory:
707 @item @b{interface} -- one for each kind of JTAG adapter/dongle
708 @item @b{board} -- one for each different board
709 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
712 Best case: include just two files, and they handle everything else.
713 The first is an interface config file.
714 The second is board-specific, and it sets up the JTAG TAPs and
715 their GDB targets (by deferring to some @file{target.cfg} file),
716 declares all flash memory, and leaves you nothing to do except
720 source [find interface/olimex-jtag-tiny.cfg]
721 source [find board/csb337.cfg]
724 Boards with a single microcontroller often won't need more
725 than the target config file, as in the AT91SAM7X256 example.
726 That's because there is no external memory (flash, DDR RAM), and
727 the board differences are encapsulated by application code.
729 @item You can often reuse some standard config files but
730 need to write a few new ones, probably a @file{board.cfg} file.
731 You will be using commands described later in this User's Guide,
732 and working with the guidelines in the next chapter.
734 For example, there may be configuration files for your JTAG adapter
735 and target chip, but you need a new board-specific config file
736 giving access to your particular flash chips.
737 Or you might need to write another target chip configuration file
738 for a new chip built around the Cortex M3 core.
741 When you write new configuration files, please submit
742 them for inclusion in the next OpenOCD release.
743 For example, a @file{board/newboard.cfg} file will help the
744 next users of that board, and a @file{target/newcpu.cfg}
745 will help support users of any board using that chip.
749 You may may need to write some C code.
750 It may be as simple as a supporting a new ft2232 or parport
751 based dongle; a bit more involved, like a NAND or NOR flash
752 controller driver; or a big piece of work like supporting
753 a new chip architecture.
756 Reuse the existing config files when you can.
757 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
758 You may find a board configuration that's a good example to follow.
760 When you write config files, separate the reusable parts
761 (things every user of that interface, chip, or board needs)
762 from ones specific to your environment and debugging approach.
766 For example, a @code{gdb-attach} event handler that invokes
767 the @command{reset init} command will interfere with debugging
768 early boot code, which performs some of the same actions
769 that the @code{reset-init} event handler does.
772 Likewise, the @command{arm9tdmi vector_catch} command (or
774 its siblings @command{xscale vector_catch}
775 and @command{cortex_m3 vector_catch}) can be a timesaver
776 during some debug sessions, but don't make everyone use that either.
777 Keep those kinds of debugging aids in your user config file,
778 along with messaging and tracing setup.
779 (@xref{Software Debug Messages and Tracing}.)
782 You might need to override some defaults.
783 For example, you might need to move, shrink, or back up the target's
784 work area if your application needs much SRAM.
787 TCP/IP port configuration is another example of something which
788 is environment-specific, and should only appear in
789 a user config file. @xref{TCP/IP Ports}.
792 @section Project-Specific Utilities
794 A few project-specific utility
795 routines may well speed up your work.
796 Write them, and keep them in your project's user config file.
798 For example, if you are making a boot loader work on a
799 board, it's nice to be able to debug the ``after it's
800 loaded to RAM'' parts separately from the finicky early
801 code which sets up the DDR RAM controller and clocks.
802 A script like this one, or a more GDB-aware sibling,
806 proc ramboot @{ @} @{
807 # Reset, running the target's "reset-init" scripts
808 # to initialize clocks and the DDR RAM controller.
809 # Leave the CPU halted.
812 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
813 load_image u-boot.bin 0x20000000
820 Then once that code is working you will need to make it
821 boot from NOR flash; a different utility would help.
822 Alternatively, some developers write to flash using GDB.
823 (You might use a similar script if you're working with a flash
824 based microcontroller application instead of a boot loader.)
827 proc newboot @{ @} @{
828 # Reset, leaving the CPU halted. The "reset-init" event
829 # proc gives faster access to the CPU and to NOR flash;
830 # "reset halt" would be slower.
833 # Write standard version of U-Boot into the first two
834 # sectors of NOR flash ... the standard version should
835 # do the same lowlevel init as "reset-init".
836 flash protect 0 0 1 off
837 flash erase_sector 0 0 1
838 flash write_bank 0 u-boot.bin 0x0
839 flash protect 0 0 1 on
841 # Reboot from scratch using that new boot loader.
846 You may need more complicated utility procedures when booting
848 That often involves an extra bootloader stage,
849 running from on-chip SRAM to perform DDR RAM setup so it can load
850 the main bootloader code (which won't fit into that SRAM).
852 Other helper scripts might be used to write production system images,
853 involving considerably more than just a three stage bootloader.
855 @section Target Software Changes
857 Sometimes you may want to make some small changes to the software
858 you're developing, to help make JTAG debugging work better.
859 For example, in C or assembly language code you might
860 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
861 handling issues like:
865 @item @b{ARM Wait-For-Interrupt}...
866 Many ARM chips synchronize the JTAG clock using the core clock.
867 Low power states which stop that core clock thus prevent JTAG access.
868 Idle loops in tasking environments often enter those low power states
869 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
871 You may want to @emph{disable that instruction} in source code,
872 or otherwise prevent using that state,
873 to ensure you can get JTAG access at any time.
874 For example, the OpenOCD @command{halt} command may not
875 work for an idle processor otherwise.
877 @item @b{Delay after reset}...
878 Not all chips have good support for debugger access
879 right after reset; many LPC2xxx chips have issues here.
880 Similarly, applications that reconfigure pins used for
881 JTAG access as they start will also block debugger access.
883 To work with boards like this, @emph{enable a short delay loop}
884 the first thing after reset, before "real" startup activities.
885 For example, one second's delay is usually more than enough
886 time for a JTAG debugger to attach, so that
887 early code execution can be debugged
888 or firmware can be replaced.
890 @item @b{Debug Communications Channel (DCC)}...
891 Some processors include mechanisms to send messages over JTAG.
892 Many ARM cores support these, as do some cores from other vendors.
893 (OpenOCD may be able to use this DCC internally, speeding up some
894 operations like writing to memory.)
896 Your application may want to deliver various debugging messages
897 over JTAG, by @emph{linking with a small library of code}
898 provided with OpenOCD and using the utilities there to send
899 various kinds of message.
900 @xref{Software Debug Messages and Tracing}.
904 @node Config File Guidelines
905 @chapter Config File Guidelines
907 This chapter is aimed at any user who needs to write a config file,
908 including developers and integrators of OpenOCD and any user who
909 needs to get a new board working smoothly.
910 It provides guidelines for creating those files.
912 You should find the following directories under @t{$(INSTALLDIR)/scripts},
913 with files including the ones listed here.
914 Use them as-is where you can; or as models for new files.
916 @item @file{interface} ...
917 think JTAG Dongle. Files that configure JTAG adapters go here.
920 arm-jtag-ew.cfg hitex_str9-comstick.cfg oocdlink.cfg
921 arm-usb-ocd.cfg icebear.cfg openocd-usb.cfg
922 at91rm9200.cfg jlink.cfg parport.cfg
923 axm0432.cfg jtagkey2.cfg parport_dlc5.cfg
924 calao-usb-a9260-c01.cfg jtagkey.cfg rlink.cfg
925 calao-usb-a9260-c02.cfg jtagkey-tiny.cfg sheevaplug.cfg
926 calao-usb-a9260.cfg luminary.cfg signalyzer.cfg
927 chameleon.cfg luminary-icdi.cfg stm32-stick.cfg
928 cortino.cfg luminary-lm3s811.cfg turtelizer2.cfg
929 dummy.cfg olimex-arm-usb-ocd.cfg usbprog.cfg
930 flyswatter.cfg olimex-jtag-tiny.cfg vsllink.cfg
933 @item @file{board} ...
934 think Circuit Board, PWA, PCB, they go by many names. Board files
935 contain initialization items that are specific to a board.
936 They reuse target configuration files, since the same
937 microprocessor chips are used on many boards,
938 but support for external parts varies widely. For
939 example, the SDRAM initialization sequence for the board, or the type
940 of external flash and what address it uses. Any initialization
941 sequence to enable that external flash or SDRAM should be found in the
942 board file. Boards may also contain multiple targets: two CPUs; or
946 arm_evaluator7t.cfg keil_mcb1700.cfg
947 at91rm9200-dk.cfg keil_mcb2140.cfg
948 at91sam9g20-ek.cfg linksys_nslu2.cfg
949 atmel_at91sam7s-ek.cfg logicpd_imx27.cfg
950 atmel_at91sam9260-ek.cfg mini2440.cfg
951 atmel_sam3u_ek.cfg olimex_LPC2378STK.cfg
952 crossbow_tech_imote2.cfg olimex_lpc_h2148.cfg
953 csb337.cfg olimex_sam7_ex256.cfg
954 csb732.cfg olimex_sam9_l9260.cfg
955 digi_connectcore_wi-9c.cfg olimex_stm32_h103.cfg
956 dm355evm.cfg omap2420_h4.cfg
957 dm365evm.cfg osk5912.cfg
958 dm6446evm.cfg pic-p32mx.cfg
959 eir.cfg propox_mmnet1001.cfg
960 ek-lm3s1968.cfg pxa255_sst.cfg
961 ek-lm3s3748.cfg sheevaplug.cfg
962 ek-lm3s811.cfg stm3210e_eval.cfg
963 ek-lm3s9b9x.cfg stm32f10x_128k_eval.cfg
964 hammer.cfg str910-eval.cfg
965 hitex_lpc2929.cfg telo.cfg
966 hitex_stm32-performancestick.cfg ti_beagleboard.cfg
967 hitex_str9-comstick.cfg topas910.cfg
968 iar_str912_sk.cfg topasa900.cfg
969 imx27ads.cfg unknown_at91sam9260.cfg
970 imx27lnst.cfg x300t.cfg
971 imx31pdk.cfg zy1000.cfg
974 @item @file{target} ...
975 think chip. The ``target'' directory represents the JTAG TAPs
977 which OpenOCD should control, not a board. Two common types of targets
978 are ARM chips and FPGA or CPLD chips.
979 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
980 the target config file defines all of them.
983 aduc702x.cfg imx27.cfg pxa255.cfg
984 ar71xx.cfg imx31.cfg pxa270.cfg
985 at91eb40a.cfg imx35.cfg readme.txt
986 at91r40008.cfg is5114.cfg sam7se512.cfg
987 at91rm9200.cfg ixp42x.cfg sam7x256.cfg
988 at91sam3u1c.cfg lm3s1968.cfg samsung_s3c2410.cfg
989 at91sam3u1e.cfg lm3s3748.cfg samsung_s3c2440.cfg
990 at91sam3u2c.cfg lm3s6965.cfg samsung_s3c2450.cfg
991 at91sam3u2e.cfg lm3s811.cfg samsung_s3c4510.cfg
992 at91sam3u4c.cfg lm3s9b9x.cfg samsung_s3c6410.cfg
993 at91sam3u4e.cfg lpc1768.cfg sharp_lh79532.cfg
994 at91sam3uXX.cfg lpc2103.cfg smdk6410.cfg
995 at91sam7sx.cfg lpc2124.cfg smp8634.cfg
996 at91sam9260.cfg lpc2129.cfg stm32.cfg
997 c100.cfg lpc2148.cfg str710.cfg
998 c100config.tcl lpc2294.cfg str730.cfg
999 c100helper.tcl lpc2378.cfg str750.cfg
1000 c100regs.tcl lpc2478.cfg str912.cfg
1001 cs351x.cfg lpc2900.cfg telo.cfg
1002 davinci.cfg mega128.cfg ti_dm355.cfg
1003 dragonite.cfg netx500.cfg ti_dm365.cfg
1004 epc9301.cfg omap2420.cfg ti_dm6446.cfg
1005 feroceon.cfg omap3530.cfg tmpa900.cfg
1006 icepick.cfg omap5912.cfg tmpa910.cfg
1007 imx21.cfg pic32mx.cfg xba_revA3.cfg
1010 @item @emph{more} ... browse for other library files which may be useful.
1011 For example, there are various generic and CPU-specific utilities.
1014 The @file{openocd.cfg} user config
1015 file may override features in any of the above files by
1016 setting variables before sourcing the target file, or by adding
1017 commands specific to their situation.
1019 @section Interface Config Files
1021 The user config file
1022 should be able to source one of these files with a command like this:
1025 source [find interface/FOOBAR.cfg]
1028 A preconfigured interface file should exist for every interface in use
1029 today, that said, perhaps some interfaces have only been used by the
1030 sole developer who created it.
1032 A separate chapter gives information about how to set these up.
1033 @xref{Interface - Dongle Configuration}.
1034 Read the OpenOCD source code if you have a new kind of hardware interface
1035 and need to provide a driver for it.
1037 @section Board Config Files
1038 @cindex config file, board
1039 @cindex board config file
1041 The user config file
1042 should be able to source one of these files with a command like this:
1045 source [find board/FOOBAR.cfg]
1048 The point of a board config file is to package everything
1049 about a given board that user config files need to know.
1050 In summary the board files should contain (if present)
1053 @item One or more @command{source [target/...cfg]} statements
1054 @item NOR flash configuration (@pxref{NOR Configuration})
1055 @item NAND flash configuration (@pxref{NAND Configuration})
1056 @item Target @code{reset} handlers for SDRAM and I/O configuration
1057 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1058 @item All things that are not ``inside a chip''
1061 Generic things inside target chips belong in target config files,
1062 not board config files. So for example a @code{reset-init} event
1063 handler should know board-specific oscillator and PLL parameters,
1064 which it passes to target-specific utility code.
1066 The most complex task of a board config file is creating such a
1067 @code{reset-init} event handler.
1068 Define those handlers last, after you verify the rest of the board
1069 configuration works.
1071 @subsection Communication Between Config files
1073 In addition to target-specific utility code, another way that
1074 board and target config files communicate is by following a
1075 convention on how to use certain variables.
1077 The full Tcl/Tk language supports ``namespaces'', but JIM-Tcl does not.
1078 Thus the rule we follow in OpenOCD is this: Variables that begin with
1079 a leading underscore are temporary in nature, and can be modified and
1080 used at will within a target configuration file.
1082 Complex board config files can do the things like this,
1083 for a board with three chips:
1086 # Chip #1: PXA270 for network side, big endian
1087 set CHIPNAME network
1089 source [find target/pxa270.cfg]
1090 # on return: _TARGETNAME = network.cpu
1091 # other commands can refer to the "network.cpu" target.
1092 $_TARGETNAME configure .... events for this CPU..
1094 # Chip #2: PXA270 for video side, little endian
1097 source [find target/pxa270.cfg]
1098 # on return: _TARGETNAME = video.cpu
1099 # other commands can refer to the "video.cpu" target.
1100 $_TARGETNAME configure .... events for this CPU..
1102 # Chip #3: Xilinx FPGA for glue logic
1105 source [find target/spartan3.cfg]
1108 That example is oversimplified because it doesn't show any flash memory,
1109 or the @code{reset-init} event handlers to initialize external DRAM
1110 or (assuming it needs it) load a configuration into the FPGA.
1111 Such features are usually needed for low-level work with many boards,
1112 where ``low level'' implies that the board initialization software may
1113 not be working. (That's a common reason to need JTAG tools. Another
1114 is to enable working with microcontroller-based systems, which often
1115 have no debugging support except a JTAG connector.)
1117 Target config files may also export utility functions to board and user
1118 config files. Such functions should use name prefixes, to help avoid
1121 Board files could also accept input variables from user config files.
1122 For example, there might be a @code{J4_JUMPER} setting used to identify
1123 what kind of flash memory a development board is using, or how to set
1124 up other clocks and peripherals.
1126 @subsection Variable Naming Convention
1127 @cindex variable names
1129 Most boards have only one instance of a chip.
1130 However, it should be easy to create a board with more than
1131 one such chip (as shown above).
1132 Accordingly, we encourage these conventions for naming
1133 variables associated with different @file{target.cfg} files,
1134 to promote consistency and
1135 so that board files can override target defaults.
1137 Inputs to target config files include:
1140 @item @code{CHIPNAME} ...
1141 This gives a name to the overall chip, and is used as part of
1142 tap identifier dotted names.
1143 While the default is normally provided by the chip manufacturer,
1144 board files may need to distinguish between instances of a chip.
1145 @item @code{ENDIAN} ...
1146 By default @option{little} - although chips may hard-wire @option{big}.
1147 Chips that can't change endianness don't need to use this variable.
1148 @item @code{CPUTAPID} ...
1149 When OpenOCD examines the JTAG chain, it can be told verify the
1150 chips against the JTAG IDCODE register.
1151 The target file will hold one or more defaults, but sometimes the
1152 chip in a board will use a different ID (perhaps a newer revision).
1155 Outputs from target config files include:
1158 @item @code{_TARGETNAME} ...
1159 By convention, this variable is created by the target configuration
1160 script. The board configuration file may make use of this variable to
1161 configure things like a ``reset init'' script, or other things
1162 specific to that board and that target.
1163 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1164 @code{_TARGETNAME1}, ... etc.
1167 @subsection The reset-init Event Handler
1168 @cindex event, reset-init
1169 @cindex reset-init handler
1171 Board config files run in the OpenOCD configuration stage;
1172 they can't use TAPs or targets, since they haven't been
1174 This means you can't write memory or access chip registers;
1175 you can't even verify that a flash chip is present.
1176 That's done later in event handlers, of which the target @code{reset-init}
1177 handler is one of the most important.
1179 Except on microcontrollers, the basic job of @code{reset-init} event
1180 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1181 Microcontrollers rarely use boot loaders; they run right out of their
1182 on-chip flash and SRAM memory. But they may want to use one of these
1183 handlers too, if just for developer convenience.
1186 Because this is so very board-specific, and chip-specific, no examples
1188 Instead, look at the board config files distributed with OpenOCD.
1189 If you have a boot loader, its source code may also be useful.
1192 Some of this code could probably be shared between different boards.
1193 For example, setting up a DRAM controller often doesn't differ by
1194 much except the bus width (16 bits or 32?) and memory timings, so a
1195 reusable TCL procedure loaded by the @file{target.cfg} file might take
1196 those as parameters.
1197 Similarly with oscillator, PLL, and clock setup;
1198 and disabling the watchdog.
1199 Structure the code cleanly, and provide comments to help
1200 the next developer doing such work.
1201 (@emph{You might be that next person} trying to reuse init code!)
1203 The last thing normally done in a @code{reset-init} handler is probing
1204 whatever flash memory was configured. For most chips that needs to be
1205 done while the associated target is halted, either because JTAG memory
1206 access uses the CPU or to prevent conflicting CPU access.
1208 @subsection JTAG Clock Rate
1210 Before your @code{reset-init} handler has set up
1211 the PLLs and clocking, you may need to run with
1212 a low JTAG clock rate.
1214 Then you'd increase that rate after your handler has
1215 made it possible to use the faster JTAG clock.
1216 When the initial low speed is board-specific, for example
1217 because it depends on a board-specific oscillator speed, then
1218 you should probably set it up in the board config file;
1219 if it's target-specific, it belongs in the target config file.
1221 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1222 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1223 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1224 Consult chip documentation to determine the peak JTAG clock rate,
1225 which might be less than that.
1228 On most ARMs, JTAG clock detection is coupled to the core clock, so
1229 software using a @option{wait for interrupt} operation blocks JTAG access.
1230 Adaptive clocking provides a partial workaround, but a more complete
1231 solution just avoids using that instruction with JTAG debuggers.
1234 If the board supports adaptive clocking, use the @command{jtag_rclk}
1235 command, in case your board is used with JTAG adapter which
1236 also supports it. Otherwise use @command{jtag_khz}.
1237 Set the slow rate at the beginning of the reset sequence,
1238 and the faster rate as soon as the clocks are at full speed.
1240 @section Target Config Files
1241 @cindex config file, target
1242 @cindex target config file
1244 Board config files communicate with target config files using
1245 naming conventions as described above, and may source one or
1246 more target config files like this:
1249 source [find target/FOOBAR.cfg]
1252 The point of a target config file is to package everything
1253 about a given chip that board config files need to know.
1254 In summary the target files should contain
1258 @item Add TAPs to the scan chain
1259 @item Add CPU targets (includes GDB support)
1260 @item CPU/Chip/CPU-Core specific features
1264 As a rule of thumb, a target file sets up only one chip.
1265 For a microcontroller, that will often include a single TAP,
1266 which is a CPU needing a GDB target, and its on-chip flash.
1268 More complex chips may include multiple TAPs, and the target
1269 config file may need to define them all before OpenOCD
1270 can talk to the chip.
1271 For example, some phone chips have JTAG scan chains that include
1272 an ARM core for operating system use, a DSP,
1273 another ARM core embedded in an image processing engine,
1274 and other processing engines.
1276 @subsection Default Value Boiler Plate Code
1278 All target configuration files should start with code like this,
1279 letting board config files express environment-specific
1280 differences in how things should be set up.
1283 # Boards may override chip names, perhaps based on role,
1284 # but the default should match what the vendor uses
1285 if @{ [info exists CHIPNAME] @} @{
1286 set _CHIPNAME $CHIPNAME
1288 set _CHIPNAME sam7x256
1291 # ONLY use ENDIAN with targets that can change it.
1292 if @{ [info exists ENDIAN] @} @{
1298 # TAP identifiers may change as chips mature, for example with
1299 # new revision fields (the "3" here). Pick a good default; you
1300 # can pass several such identifiers to the "jtag newtap" command.
1301 if @{ [info exists CPUTAPID ] @} @{
1302 set _CPUTAPID $CPUTAPID
1304 set _CPUTAPID 0x3f0f0f0f
1307 @c but 0x3f0f0f0f is for an str73x part ...
1309 @emph{Remember:} Board config files may include multiple target
1310 config files, or the same target file multiple times
1311 (changing at least @code{CHIPNAME}).
1313 Likewise, the target configuration file should define
1314 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1315 use it later on when defining debug targets:
1318 set _TARGETNAME $_CHIPNAME.cpu
1319 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1322 @subsection Adding TAPs to the Scan Chain
1323 After the ``defaults'' are set up,
1324 add the TAPs on each chip to the JTAG scan chain.
1325 @xref{TAP Declaration}, and the naming convention
1328 In the simplest case the chip has only one TAP,
1329 probably for a CPU or FPGA.
1330 The config file for the Atmel AT91SAM7X256
1331 looks (in part) like this:
1334 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
1335 -expected-id $_CPUTAPID
1338 A board with two such at91sam7 chips would be able
1339 to source such a config file twice, with different
1340 values for @code{CHIPNAME}, so
1341 it adds a different TAP each time.
1343 If there are nonzero @option{-expected-id} values,
1344 OpenOCD attempts to verify the actual tap id against those values.
1345 It will issue error messages if there is mismatch, which
1346 can help to pinpoint problems in OpenOCD configurations.
1349 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1350 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1351 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1352 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1353 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1356 There are more complex examples too, with chips that have
1357 multiple TAPs. Ones worth looking at include:
1360 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1361 plus a JRC to enable them
1362 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1363 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1364 is not currently used)
1367 @subsection Add CPU targets
1369 After adding a TAP for a CPU, you should set it up so that
1370 GDB and other commands can use it.
1371 @xref{CPU Configuration}.
1372 For the at91sam7 example above, the command can look like this;
1373 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1374 to little endian, and this chip doesn't support changing that.
1377 set _TARGETNAME $_CHIPNAME.cpu
1378 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1381 Work areas are small RAM areas associated with CPU targets.
1382 They are used by OpenOCD to speed up downloads,
1383 and to download small snippets of code to program flash chips.
1384 If the chip includes a form of ``on-chip-ram'' - and many do - define
1385 a work area if you can.
1386 Again using the at91sam7 as an example, this can look like:
1389 $_TARGETNAME configure -work-area-phys 0x00200000 \
1390 -work-area-size 0x4000 -work-area-backup 0
1393 @subsection Chip Reset Setup
1395 As a rule, you should put the @command{reset_config} command
1396 into the board file. Most things you think you know about a
1397 chip can be tweaked by the board.
1399 Some chips have specific ways the TRST and SRST signals are
1400 managed. In the unusual case that these are @emph{chip specific}
1401 and can never be changed by board wiring, they could go here.
1403 Some chips need special attention during reset handling if
1404 they're going to be used with JTAG.
1405 An example might be needing to send some commands right
1406 after the target's TAP has been reset, providing a
1407 @code{reset-deassert-post} event handler that writes a chip
1408 register to report that JTAG debugging is being done.
1410 JTAG clocking constraints often change during reset, and in
1411 some cases target config files (rather than board config files)
1412 are the right places to handle some of those issues.
1413 For example, immediately after reset most chips run using a
1414 slower clock than they will use later.
1415 That means that after reset (and potentially, as OpenOCD
1416 first starts up) they must use a slower JTAG clock rate
1417 than they will use later.
1420 @quotation Important
1421 When you are debugging code that runs right after chip
1422 reset, getting these issues right is critical.
1423 In particular, if you see intermittent failures when
1424 OpenOCD verifies the scan chain after reset,
1425 look at how you are setting up JTAG clocking.
1428 @subsection ARM Core Specific Hacks
1430 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1431 special high speed download features - enable it.
1433 If present, the MMU, the MPU and the CACHE should be disabled.
1435 Some ARM cores are equipped with trace support, which permits
1436 examination of the instruction and data bus activity. Trace
1437 activity is controlled through an ``Embedded Trace Module'' (ETM)
1438 on one of the core's scan chains. The ETM emits voluminous data
1439 through a ``trace port''. (@xref{ARM Hardware Tracing}.)
1440 If you are using an external trace port,
1441 configure it in your board config file.
1442 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
1443 configure it in your target config file.
1446 etm config $_TARGETNAME 16 normal full etb
1447 etb config $_TARGETNAME $_CHIPNAME.etb
1450 @subsection Internal Flash Configuration
1452 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1454 @b{Never ever} in the ``target configuration file'' define any type of
1455 flash that is external to the chip. (For example a BOOT flash on
1456 Chip Select 0.) Such flash information goes in a board file - not
1457 the TARGET (chip) file.
1461 @item at91sam7x256 - has 256K flash YES enable it.
1462 @item str912 - has flash internal YES enable it.
1463 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1464 @item pxa270 - again - CS0 flash - it goes in the board file.
1467 @node Translating Configuration Files
1468 @chapter Translating Configuration Files
1470 If you have a configuration file for another hardware debugger(Abatron,
1471 BDI2000, BDI3000, Lauterbach, Segger, MacRaigor, etc.), translating
1472 it into OpenOCD syntax is often quite straightforward. The most tricky
1473 part of creating a configuration script is oftentimes the reset init
1474 sequence where e.g. PLLs, DRAM and the like is set up.
1476 One trick that you can use when translating is to write small
1477 Tcl proc's to translate the syntax into OpenOCD syntax. This
1478 can avoid manual translation errors and make it easier to
1479 convert other scripts later on.
1481 Example of transforming quirky arguments to a simple search and
1485 # rewrite commands of the form below to arm11 mcr...
1487 # Lauterbach syntax(?)
1489 # Data.Set c15:0x042f %long 0x40000015
1491 # OpenOCD syntax when using procedure below.
1493 # setc15 0x01 0x00050078
1496 proc setc15 @{regs value@} @{
1499 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
1501 arm11 mcr $TARGETNAME 15 [expr ($regs>>12)&0x7] [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] [expr ($regs>>8)&0x7] $value
1507 @node Daemon Configuration
1508 @chapter Daemon Configuration
1509 @cindex initialization
1510 The commands here are commonly found in the openocd.cfg file and are
1511 used to specify what TCP/IP ports are used, and how GDB should be
1514 @anchor{Configuration Stage}
1515 @section Configuration Stage
1516 @cindex configuration stage
1517 @cindex config command
1519 When the OpenOCD server process starts up, it enters a
1520 @emph{configuration stage} which is the only time that
1521 certain commands, @emph{configuration commands}, may be issued.
1522 In this manual, the definition of a configuration command is
1523 presented as a @emph{Config Command}, not as a @emph{Command}
1524 which may be issued interactively.
1526 Those configuration commands include declaration of TAPs,
1528 the interface used for JTAG communication,
1529 and other basic setup.
1530 The server must leave the configuration stage before it
1531 may access or activate TAPs.
1532 After it leaves this stage, configuration commands may no
1535 The first thing OpenOCD does after leaving the configuration
1536 stage is to verify that it can talk to the scan chain
1537 (list of TAPs) which has been configured.
1538 It will warn if it doesn't find TAPs it expects to find,
1539 or finds TAPs that aren't supposed to be there.
1540 You should see no errors at this point.
1541 If you see errors, resolve them by correcting the
1542 commands you used to configure the server.
1543 Common errors include using an initial JTAG speed that's too
1544 fast, and not providing the right IDCODE values for the TAPs
1547 @deffn {Config Command} init
1548 This command terminates the configuration stage and
1549 enters the normal command mode. This can be useful to add commands to
1550 the startup scripts and commands such as resetting the target,
1551 programming flash, etc. To reset the CPU upon startup, add "init" and
1552 "reset" at the end of the config script or at the end of the OpenOCD
1553 command line using the @option{-c} command line switch.
1555 If this command does not appear in any startup/configuration file
1556 OpenOCD executes the command for you after processing all
1557 configuration files and/or command line options.
1559 @b{NOTE:} This command normally occurs at or near the end of your
1560 openocd.cfg file to force OpenOCD to ``initialize'' and make the
1561 targets ready. For example: If your openocd.cfg file needs to
1562 read/write memory on your target, @command{init} must occur before
1563 the memory read/write commands. This includes @command{nand probe}.
1566 @deffn {Overridable Procedure} jtag_init
1567 This is invoked at server startup to verify that it can talk
1568 to the scan chain (list of TAPs) which has been configured.
1570 The default implementation first tries @command{jtag arp_init},
1571 which uses only a lightweight JTAG reset before examining the
1573 If that fails, it tries again, using a harder reset
1574 from the overridable procedure @command{init_reset}.
1577 @anchor{TCP/IP Ports}
1578 @section TCP/IP Ports
1583 The OpenOCD server accepts remote commands in several syntaxes.
1584 Each syntax uses a different TCP/IP port, which you may specify
1585 only during configuration (before those ports are opened).
1587 For reasons including security, you may wish to prevent remote
1588 access using one or more of these ports.
1589 In such cases, just specify the relevant port number as zero.
1590 If you disable all access through TCP/IP, you will need to
1591 use the command line @option{-pipe} option.
1593 @deffn {Command} gdb_port (number)
1595 Specify or query the first port used for incoming GDB connections.
1596 The GDB port for the
1597 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
1598 When not specified during the configuration stage,
1599 the port @var{number} defaults to 3333.
1600 When specified as zero, this port is not activated.
1603 @deffn {Command} tcl_port (number)
1604 Specify or query the port used for a simplified RPC
1605 connection that can be used by clients to issue TCL commands and get the
1606 output from the Tcl engine.
1607 Intended as a machine interface.
1608 When not specified during the configuration stage,
1609 the port @var{number} defaults to 6666.
1610 When specified as zero, this port is not activated.
1613 @deffn {Command} telnet_port (number)
1614 Specify or query the
1615 port on which to listen for incoming telnet connections.
1616 This port is intended for interaction with one human through TCL commands.
1617 When not specified during the configuration stage,
1618 the port @var{number} defaults to 4444.
1619 When specified as zero, this port is not activated.
1622 @anchor{GDB Configuration}
1623 @section GDB Configuration
1625 @cindex GDB configuration
1626 You can reconfigure some GDB behaviors if needed.
1627 The ones listed here are static and global.
1628 @xref{Target Configuration}, about configuring individual targets.
1629 @xref{Target Events}, about configuring target-specific event handling.
1631 @anchor{gdb_breakpoint_override}
1632 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
1633 Force breakpoint type for gdb @command{break} commands.
1634 This option supports GDB GUIs which don't
1635 distinguish hard versus soft breakpoints, if the default OpenOCD and
1636 GDB behaviour is not sufficient. GDB normally uses hardware
1637 breakpoints if the memory map has been set up for flash regions.
1640 @deffn {Config Command} gdb_detach (@option{resume}|@option{reset}|@option{halt}|@option{nothing})
1641 Configures what OpenOCD will do when GDB detaches from the daemon.
1642 Default behaviour is @option{resume}.
1645 @anchor{gdb_flash_program}
1646 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
1647 Set to @option{enable} to cause OpenOCD to program the flash memory when a
1648 vFlash packet is received.
1649 The default behaviour is @option{enable}.
1652 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
1653 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
1654 requested. GDB will then know when to set hardware breakpoints, and program flash
1655 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
1656 for flash programming to work.
1657 Default behaviour is @option{enable}.
1658 @xref{gdb_flash_program}.
1661 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
1662 Specifies whether data aborts cause an error to be reported
1663 by GDB memory read packets.
1664 The default behaviour is @option{disable};
1665 use @option{enable} see these errors reported.
1668 @anchor{Event Polling}
1669 @section Event Polling
1671 Hardware debuggers are parts of asynchronous systems,
1672 where significant events can happen at any time.
1673 The OpenOCD server needs to detect some of these events,
1674 so it can report them to through TCL command line
1677 Examples of such events include:
1680 @item One of the targets can stop running ... maybe it triggers
1681 a code breakpoint or data watchpoint, or halts itself.
1682 @item Messages may be sent over ``debug message'' channels ... many
1683 targets support such messages sent over JTAG,
1684 for receipt by the person debugging or tools.
1685 @item Loss of power ... some adapters can detect these events.
1686 @item Resets not issued through JTAG ... such reset sources
1687 can include button presses or other system hardware, sometimes
1688 including the target itself (perhaps through a watchdog).
1689 @item Debug instrumentation sometimes supports event triggering
1690 such as ``trace buffer full'' (so it can quickly be emptied)
1691 or other signals (to correlate with code behavior).
1694 None of those events are signaled through standard JTAG signals.
1695 However, most conventions for JTAG connectors include voltage
1696 level and system reset (SRST) signal detection.
1697 Some connectors also include instrumentation signals, which
1698 can imply events when those signals are inputs.
1700 In general, OpenOCD needs to periodically check for those events,
1701 either by looking at the status of signals on the JTAG connector
1702 or by sending synchronous ``tell me your status'' JTAG requests
1703 to the various active targets.
1704 There is a command to manage and monitor that polling,
1705 which is normally done in the background.
1707 @deffn Command poll [@option{on}|@option{off}]
1708 Poll the current target for its current state.
1709 (Also, @pxref{target curstate}.)
1710 If that target is in debug mode, architecture
1711 specific information about the current state is printed.
1712 An optional parameter
1713 allows background polling to be enabled and disabled.
1715 You could use this from the TCL command shell, or
1716 from GDB using @command{monitor poll} command.
1719 background polling: on
1720 target state: halted
1721 target halted in ARM state due to debug-request, \
1722 current mode: Supervisor
1723 cpsr: 0x800000d3 pc: 0x11081bfc
1724 MMU: disabled, D-Cache: disabled, I-Cache: enabled
1729 @node Interface - Dongle Configuration
1730 @chapter Interface - Dongle Configuration
1731 @cindex config file, interface
1732 @cindex interface config file
1734 JTAG Adapters/Interfaces/Dongles are normally configured
1735 through commands in an interface configuration
1736 file which is sourced by your @file{openocd.cfg} file, or
1737 through a command line @option{-f interface/....cfg} option.
1740 source [find interface/olimex-jtag-tiny.cfg]
1744 OpenOCD what type of JTAG adapter you have, and how to talk to it.
1745 A few cases are so simple that you only need to say what driver to use:
1752 Most adapters need a bit more configuration than that.
1755 @section Interface Configuration
1757 The interface command tells OpenOCD what type of JTAG dongle you are
1758 using. Depending on the type of dongle, you may need to have one or
1759 more additional commands.
1761 @deffn {Config Command} {interface} name
1762 Use the interface driver @var{name} to connect to the
1766 @deffn Command {interface_list}
1767 List the interface drivers that have been built into
1768 the running copy of OpenOCD.
1771 @deffn Command {jtag interface}
1772 Returns the name of the interface driver being used.
1775 @section Interface Drivers
1777 Each of the interface drivers listed here must be explicitly
1778 enabled when OpenOCD is configured, in order to be made
1779 available at run time.
1781 @deffn {Interface Driver} {amt_jtagaccel}
1782 Amontec Chameleon in its JTAG Accelerator configuration,
1783 connected to a PC's EPP mode parallel port.
1784 This defines some driver-specific commands:
1786 @deffn {Config Command} {parport_port} number
1787 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
1788 the number of the @file{/dev/parport} device.
1791 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
1792 Displays status of RTCK option.
1793 Optionally sets that option first.
1797 @deffn {Interface Driver} {arm-jtag-ew}
1798 Olimex ARM-JTAG-EW USB adapter
1799 This has one driver-specific command:
1801 @deffn Command {armjtagew_info}
1806 @deffn {Interface Driver} {at91rm9200}
1807 Supports bitbanged JTAG from the local system,
1808 presuming that system is an Atmel AT91rm9200
1809 and a specific set of GPIOs is used.
1810 @c command: at91rm9200_device NAME
1811 @c chooses among list of bit configs ... only one option
1814 @deffn {Interface Driver} {dummy}
1815 A dummy software-only driver for debugging.
1818 @deffn {Interface Driver} {ep93xx}
1819 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
1822 @deffn {Interface Driver} {ft2232}
1823 FTDI FT2232 (USB) based devices over one of the userspace libraries.
1824 These interfaces have several commands, used to configure the driver
1825 before initializing the JTAG scan chain:
1827 @deffn {Config Command} {ft2232_device_desc} description
1828 Provides the USB device description (the @emph{iProduct string})
1829 of the FTDI FT2232 device. If not
1830 specified, the FTDI default value is used. This setting is only valid
1831 if compiled with FTD2XX support.
1834 @deffn {Config Command} {ft2232_serial} serial-number
1835 Specifies the @var{serial-number} of the FTDI FT2232 device to use,
1836 in case the vendor provides unique IDs and more than one FT2232 device
1837 is connected to the host.
1838 If not specified, serial numbers are not considered.
1839 (Note that USB serial numbers can be arbitrary Unicode strings,
1840 and are not restricted to containing only decimal digits.)
1843 @deffn {Config Command} {ft2232_layout} name
1844 Each vendor's FT2232 device can use different GPIO signals
1845 to control output-enables, reset signals, and LEDs.
1846 Currently valid layout @var{name} values include:
1848 @item @b{axm0432_jtag} Axiom AXM-0432
1849 @item @b{comstick} Hitex STR9 comstick
1850 @item @b{cortino} Hitex Cortino JTAG interface
1851 @item @b{evb_lm3s811} Luminary Micro EVB_LM3S811 as a JTAG interface,
1852 either for the local Cortex-M3 (SRST only)
1853 or in a passthrough mode (neither SRST nor TRST)
1854 @item @b{luminary_icdi} Luminary In-Circuit Debug Interface (ICDI) Board
1855 @item @b{flyswatter} Tin Can Tools Flyswatter
1856 @item @b{icebear} ICEbear JTAG adapter from Section 5
1857 @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
1858 @item @b{jtagkey2} Amontec JTAGkey2 (and compatibles)
1859 @item @b{m5960} American Microsystems M5960
1860 @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
1861 @item @b{oocdlink} OOCDLink
1862 @c oocdlink ~= jtagkey_prototype_v1
1863 @item @b{sheevaplug} Marvell Sheevaplug development kit
1864 @item @b{signalyzer} Xverve Signalyzer
1865 @item @b{stm32stick} Hitex STM32 Performance Stick
1866 @item @b{turtelizer2} egnite Software turtelizer2
1867 @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
1871 @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
1872 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
1873 default values are used.
1874 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
1876 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
1880 @deffn {Config Command} {ft2232_latency} ms
1881 On some systems using FT2232 based JTAG interfaces the FT_Read function call in
1882 ft2232_read() fails to return the expected number of bytes. This can be caused by
1883 USB communication delays and has proved hard to reproduce and debug. Setting the
1884 FT2232 latency timer to a larger value increases delays for short USB packets but it
1885 also reduces the risk of timeouts before receiving the expected number of bytes.
1886 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
1889 For example, the interface config file for a
1890 Turtelizer JTAG Adapter looks something like this:
1894 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
1895 ft2232_layout turtelizer2
1896 ft2232_vid_pid 0x0403 0xbdc8
1900 @deffn {Interface Driver} {gw16012}
1901 Gateworks GW16012 JTAG programmer.
1902 This has one driver-specific command:
1904 @deffn {Config Command} {parport_port} number
1905 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
1906 the number of the @file{/dev/parport} device.
1910 @deffn {Interface Driver} {jlink}
1911 Segger jlink USB adapter
1912 @c command: jlink_info
1914 @c command: jlink_hw_jtag (2|3)
1915 @c sets version 2 or 3
1918 @deffn {Interface Driver} {parport}
1919 Supports PC parallel port bit-banging cables:
1920 Wigglers, PLD download cable, and more.
1921 These interfaces have several commands, used to configure the driver
1922 before initializing the JTAG scan chain:
1924 @deffn {Config Command} {parport_cable} name
1925 The layout of the parallel port cable used to connect to the target.
1926 Currently valid cable @var{name} values include:
1929 @item @b{altium} Altium Universal JTAG cable.
1930 @item @b{arm-jtag} Same as original wiggler except SRST and
1931 TRST connections reversed and TRST is also inverted.
1932 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
1933 in configuration mode. This is only used to
1934 program the Chameleon itself, not a connected target.
1935 @item @b{dlc5} The Xilinx Parallel cable III.
1936 @item @b{flashlink} The ST Parallel cable.
1937 @item @b{lattice} Lattice ispDOWNLOAD Cable
1938 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
1940 Amontec's Chameleon Programmer. The new version available from
1941 the website uses the original Wiggler layout ('@var{wiggler}')
1942 @item @b{triton} The parallel port adapter found on the
1943 ``Karo Triton 1 Development Board''.
1944 This is also the layout used by the HollyGates design
1945 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
1946 @item @b{wiggler} The original Wiggler layout, also supported by
1947 several clones, such as the Olimex ARM-JTAG
1948 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
1949 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
1953 @deffn {Config Command} {parport_port} number
1954 Either the address of the I/O port (default: 0x378 for LPT1) or the number of
1955 the @file{/dev/parport} device
1957 When using PPDEV to access the parallel port, use the number of the parallel port:
1958 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
1959 you may encounter a problem.
1962 @deffn {Config Command} {parport_write_on_exit} (on|off)
1963 This will configure the parallel driver to write a known
1964 cable-specific value to the parallel interface on exiting OpenOCD
1967 For example, the interface configuration file for a
1968 classic ``Wiggler'' cable might look something like this:
1973 parport_cable wiggler
1977 @deffn {Interface Driver} {presto}
1978 ASIX PRESTO USB JTAG programmer.
1979 @c command: presto_serial str
1980 @c sets serial number
1983 @deffn {Interface Driver} {rlink}
1984 Raisonance RLink USB adapter
1987 @deffn {Interface Driver} {usbprog}
1988 usbprog is a freely programmable USB adapter.
1991 @deffn {Interface Driver} {vsllink}
1992 vsllink is part of Versaloon which is a versatile USB programmer.
1995 This defines quite a few driver-specific commands,
1996 which are not currently documented here.
2000 @deffn {Interface Driver} {ZY1000}
2001 This is the Zylin ZY1000 JTAG debugger.
2004 This defines some driver-specific commands,
2005 which are not currently documented here.
2008 @deffn Command power [@option{on}|@option{off}]
2009 Turn power switch to target on/off.
2010 No arguments: print status.
2017 JTAG clock setup is part of system setup.
2018 It @emph{does not belong with interface setup} since any interface
2019 only knows a few of the constraints for the JTAG clock speed.
2020 Sometimes the JTAG speed is
2021 changed during the target initialization process: (1) slow at
2022 reset, (2) program the CPU clocks, (3) run fast.
2023 Both the "slow" and "fast" clock rates are functions of the
2024 oscillators used, the chip, the board design, and sometimes
2025 power management software that may be active.
2027 The speed used during reset, and the scan chain verification which
2028 follows reset, can be adjusted using a @code{reset-start}
2029 target event handler.
2030 It can then be reconfigured to a faster speed by a
2031 @code{reset-init} target event handler after it reprograms those
2032 CPU clocks, or manually (if something else, such as a boot loader,
2033 sets up those clocks).
2034 @xref{Target Events}.
2035 When the initial low JTAG speed is a chip characteristic, perhaps
2036 because of a required oscillator speed, provide such a handler
2037 in the target config file.
2038 When that speed is a function of a board-specific characteristic
2039 such as which speed oscillator is used, it belongs in the board
2040 config file instead.
2041 In both cases it's safest to also set the initial JTAG clock rate
2042 to that same slow speed, so that OpenOCD never starts up using a
2043 clock speed that's faster than the scan chain can support.
2047 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
2050 If your system supports adaptive clocking (RTCK), configuring
2051 JTAG to use that is probably the most robust approach.
2052 However, it introduces delays to synchronize clocks; so it
2053 may not be the fastest solution.
2055 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
2056 instead of @command{jtag_khz}.
2058 @deffn {Command} jtag_khz max_speed_kHz
2059 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
2060 JTAG interfaces usually support a limited number of
2061 speeds. The speed actually used won't be faster
2062 than the speed specified.
2064 Chip data sheets generally include a top JTAG clock rate.
2065 The actual rate is often a function of a CPU core clock,
2066 and is normally less than that peak rate.
2067 For example, most ARM cores accept at most one sixth of the CPU clock.
2069 Speed 0 (khz) selects RTCK method.
2071 If your system uses RTCK, you won't need to change the
2072 JTAG clocking after setup.
2073 Not all interfaces, boards, or targets support ``rtck''.
2074 If the interface device can not
2075 support it, an error is returned when you try to use RTCK.
2078 @defun jtag_rclk fallback_speed_kHz
2079 @cindex adaptive clocking
2081 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
2082 If that fails (maybe the interface, board, or target doesn't
2083 support it), falls back to the specified frequency.
2085 # Fall back to 3mhz if RTCK is not supported
2090 @node Reset Configuration
2091 @chapter Reset Configuration
2092 @cindex Reset Configuration
2094 Every system configuration may require a different reset
2095 configuration. This can also be quite confusing.
2096 Resets also interact with @var{reset-init} event handlers,
2097 which do things like setting up clocks and DRAM, and
2098 JTAG clock rates. (@xref{JTAG Speed}.)
2099 They can also interact with JTAG routers.
2100 Please see the various board files for examples.
2103 To maintainers and integrators:
2104 Reset configuration touches several things at once.
2105 Normally the board configuration file
2106 should define it and assume that the JTAG adapter supports
2107 everything that's wired up to the board's JTAG connector.
2109 However, the target configuration file could also make note
2110 of something the silicon vendor has done inside the chip,
2111 which will be true for most (or all) boards using that chip.
2112 And when the JTAG adapter doesn't support everything, the
2113 user configuration file will need to override parts of
2114 the reset configuration provided by other files.
2117 @section Types of Reset
2119 There are many kinds of reset possible through JTAG, but
2120 they may not all work with a given board and adapter.
2121 That's part of why reset configuration can be error prone.
2125 @emph{System Reset} ... the @emph{SRST} hardware signal
2126 resets all chips connected to the JTAG adapter, such as processors,
2127 power management chips, and I/O controllers. Normally resets triggered
2128 with this signal behave exactly like pressing a RESET button.
2130 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
2131 just the TAP controllers connected to the JTAG adapter.
2132 Such resets should not be visible to the rest of the system; resetting a
2133 device's the TAP controller just puts that controller into a known state.
2135 @emph{Emulation Reset} ... many devices can be reset through JTAG
2136 commands. These resets are often distinguishable from system
2137 resets, either explicitly (a "reset reason" register says so)
2138 or implicitly (not all parts of the chip get reset).
2140 @emph{Other Resets} ... system-on-chip devices often support
2141 several other types of reset.
2142 You may need to arrange that a watchdog timer stops
2143 while debugging, preventing a watchdog reset.
2144 There may be individual module resets.
2147 In the best case, OpenOCD can hold SRST, then reset
2148 the TAPs via TRST and send commands through JTAG to halt the
2149 CPU at the reset vector before the 1st instruction is executed.
2150 Then when it finally releases the SRST signal, the system is
2151 halted under debugger control before any code has executed.
2152 This is the behavior required to support the @command{reset halt}
2153 and @command{reset init} commands; after @command{reset init} a
2154 board-specific script might do things like setting up DRAM.
2155 (@xref{Reset Command}.)
2157 @anchor{SRST and TRST Issues}
2158 @section SRST and TRST Issues
2160 Because SRST and TRST are hardware signals, they can have a
2161 variety of system-specific constraints. Some of the most
2166 @item @emph{Signal not available} ... Some boards don't wire
2167 SRST or TRST to the JTAG connector. Some JTAG adapters don't
2168 support such signals even if they are wired up.
2169 Use the @command{reset_config} @var{signals} options to say
2170 when either of those signals is not connected.
2171 When SRST is not available, your code might not be able to rely
2172 on controllers having been fully reset during code startup.
2173 Missing TRST is not a problem, since JTAG level resets can
2174 be triggered using with TMS signaling.
2176 @item @emph{Signals shorted} ... Sometimes a chip, board, or
2177 adapter will connect SRST to TRST, instead of keeping them separate.
2178 Use the @command{reset_config} @var{combination} options to say
2179 when those signals aren't properly independent.
2181 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
2182 delay circuit, reset supervisor, or on-chip features can extend
2183 the effect of a JTAG adapter's reset for some time after the adapter
2184 stops issuing the reset. For example, there may be chip or board
2185 requirements that all reset pulses last for at least a
2186 certain amount of time; and reset buttons commonly have
2187 hardware debouncing.
2188 Use the @command{jtag_nsrst_delay} and @command{jtag_ntrst_delay}
2189 commands to say when extra delays are needed.
2191 @item @emph{Drive type} ... Reset lines often have a pullup
2192 resistor, letting the JTAG interface treat them as open-drain
2193 signals. But that's not a requirement, so the adapter may need
2194 to use push/pull output drivers.
2195 Also, with weak pullups it may be advisable to drive
2196 signals to both levels (push/pull) to minimize rise times.
2197 Use the @command{reset_config} @var{trst_type} and
2198 @var{srst_type} parameters to say how to drive reset signals.
2200 @item @emph{Special initialization} ... Targets sometimes need
2201 special JTAG initialization sequences to handle chip-specific
2202 issues (not limited to errata).
2203 For example, certain JTAG commands might need to be issued while
2204 the system as a whole is in a reset state (SRST active)
2205 but the JTAG scan chain is usable (TRST inactive).
2206 Many systems treat combined assertion of SRST and TRST as a
2207 trigger for a harder reset than SRST alone.
2208 Such custom reset handling is discussed later in this chapter.
2211 There can also be other issues.
2212 Some devices don't fully conform to the JTAG specifications.
2213 Trivial system-specific differences are common, such as
2214 SRST and TRST using slightly different names.
2215 There are also vendors who distribute key JTAG documentation for
2216 their chips only to developers who have signed a Non-Disclosure
2219 Sometimes there are chip-specific extensions like a requirement to use
2220 the normally-optional TRST signal (precluding use of JTAG adapters which
2221 don't pass TRST through), or needing extra steps to complete a TAP reset.
2223 In short, SRST and especially TRST handling may be very finicky,
2224 needing to cope with both architecture and board specific constraints.
2226 @section Commands for Handling Resets
2228 @deffn {Command} jtag_nsrst_delay milliseconds
2229 How long (in milliseconds) OpenOCD should wait after deasserting
2230 nSRST (active-low system reset) before starting new JTAG operations.
2231 When a board has a reset button connected to SRST line it will
2232 probably have hardware debouncing, implying you should use this.
2235 @deffn {Command} jtag_ntrst_delay milliseconds
2236 How long (in milliseconds) OpenOCD should wait after deasserting
2237 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
2240 @deffn {Command} reset_config mode_flag ...
2241 This command displays or modifies the reset configuration
2242 of your combination of JTAG board and target in target
2243 configuration scripts.
2245 Information earlier in this section describes the kind of problems
2246 the command is intended to address (@pxref{SRST and TRST Issues}).
2247 As a rule this command belongs only in board config files,
2248 describing issues like @emph{board doesn't connect TRST};
2249 or in user config files, addressing limitations derived
2250 from a particular combination of interface and board.
2251 (An unlikely example would be using a TRST-only adapter
2252 with a board that only wires up SRST.)
2254 The @var{mode_flag} options can be specified in any order, but only one
2255 of each type -- @var{signals}, @var{combination},
2258 and @var{srst_type} -- may be specified at a time.
2259 If you don't provide a new value for a given type, its previous
2260 value (perhaps the default) is unchanged.
2261 For example, this means that you don't need to say anything at all about
2262 TRST just to declare that if the JTAG adapter should want to drive SRST,
2263 it must explicitly be driven high (@option{srst_push_pull}).
2267 @var{signals} can specify which of the reset signals are connected.
2268 For example, If the JTAG interface provides SRST, but the board doesn't
2269 connect that signal properly, then OpenOCD can't use it.
2270 Possible values are @option{none} (the default), @option{trst_only},
2271 @option{srst_only} and @option{trst_and_srst}.
2274 If your board provides SRST and/or TRST through the JTAG connector,
2275 you must declare that so those signals can be used.
2279 The @var{combination} is an optional value specifying broken reset
2280 signal implementations.
2281 The default behaviour if no option given is @option{separate},
2282 indicating everything behaves normally.
2283 @option{srst_pulls_trst} states that the
2284 test logic is reset together with the reset of the system (e.g. Philips
2285 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
2286 the system is reset together with the test logic (only hypothetical, I
2287 haven't seen hardware with such a bug, and can be worked around).
2288 @option{combined} implies both @option{srst_pulls_trst} and
2289 @option{trst_pulls_srst}.
2292 The @var{gates} tokens control flags that describe some cases where
2293 JTAG may be unvailable during reset.
2294 @option{srst_gates_jtag} (default)
2295 indicates that asserting SRST gates the
2296 JTAG clock. This means that no communication can happen on JTAG
2297 while SRST is asserted.
2298 Its converse is @option{srst_nogate}, indicating that JTAG commands
2299 can safely be issued while SRST is active.
2302 The optional @var{trst_type} and @var{srst_type} parameters allow the
2303 driver mode of each reset line to be specified. These values only affect
2304 JTAG interfaces with support for different driver modes, like the Amontec
2305 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
2306 relevant signal (TRST or SRST) is not connected.
2310 Possible @var{trst_type} driver modes for the test reset signal (TRST)
2311 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
2312 Most boards connect this signal to a pulldown, so the JTAG TAPs
2313 never leave reset unless they are hooked up to a JTAG adapter.
2316 Possible @var{srst_type} driver modes for the system reset signal (SRST)
2317 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
2318 Most boards connect this signal to a pullup, and allow the
2319 signal to be pulled low by various events including system
2320 powerup and pressing a reset button.
2324 @section Custom Reset Handling
2326 OpenOCD has several ways to help support the various reset
2327 mechanisms provided by chip and board vendors.
2328 The commands shown in the previous section give standard parameters.
2329 There are also @emph{event handlers} associated with TAPs or Targets.
2330 Those handlers are Tcl procedures you can provide, which are invoked
2331 at particular points in the reset sequence.
2333 After configuring those mechanisms, you might still
2334 find your board doesn't start up or reset correctly.
2335 For example, maybe it needs a slightly different sequence
2336 of SRST and/or TRST manipulations, because of quirks that
2337 the @command{reset_config} mechanism doesn't address;
2338 or asserting both might trigger a stronger reset, which
2339 needs special attention.
2341 Experiment with lower level operations, such as @command{jtag_reset}
2342 and the @command{jtag arp_*} operations shown here,
2343 to find a sequence of operations that works.
2344 @xref{JTAG Commands}.
2345 When you find a working sequence, it can be used to override
2346 @command{jtag_init}, which fires during OpenOCD startup
2347 (@pxref{Configuration Stage});
2348 or @command{init_reset}, which fires during reset processing.
2350 You might also want to provide some project-specific reset
2351 schemes. For example, on a multi-target board the standard
2352 @command{reset} command would reset all targets, but you
2353 may need the ability to reset only one target at time and
2354 thus want to avoid using the board-wide SRST signal.
2356 @deffn {Overridable Procedure} init_reset mode
2357 This is invoked near the beginning of the @command{reset} command,
2358 usually to provide as much of a cold (power-up) reset as practical.
2359 By default it is also invoked from @command{jtag_init} if
2360 the scan chain does not respond to pure JTAG operations.
2361 The @var{mode} parameter is the parameter given to the
2362 low level reset command (@option{halt},
2363 @option{init}, or @option{run}), @option{setup},
2364 or potentially some other value.
2366 The default implementation just invokes @command{jtag arp_init-reset}.
2367 Replacements will normally build on low level JTAG
2368 operations such as @command{jtag_reset}.
2369 Operations here must not address individual TAPs
2370 (or their associated targets)
2371 until the JTAG scan chain has first been verified to work.
2373 Implementations must have verified the JTAG scan chain before
2375 This is done by calling @command{jtag arp_init}
2376 (or @command{jtag arp_init-reset}).
2379 @deffn Command {jtag arp_init}
2380 This validates the scan chain using just the four
2381 standard JTAG signals (TMS, TCK, TDI, TDO).
2382 It starts by issuing a JTAG-only reset.
2383 Then it performs checks to verify that the scan chain configuration
2384 matches the TAPs it can observe.
2385 Those checks include checking IDCODE values for each active TAP,
2386 and verifying the length of their instruction registers using
2387 TAP @code{-ircapture} and @code{-irmask} values.
2388 If these tests all pass, TAP @code{setup} events are
2389 issued to all TAPs with handlers for that event.
2392 @deffn Command {jtag arp_init-reset}
2393 This uses TRST and SRST to try resetting
2394 everything on the JTAG scan chain
2395 (and anything else connected to SRST).
2396 It then invokes the logic of @command{jtag arp_init}.
2400 @node TAP Declaration
2401 @chapter TAP Declaration
2402 @cindex TAP declaration
2403 @cindex TAP configuration
2405 @emph{Test Access Ports} (TAPs) are the core of JTAG.
2406 TAPs serve many roles, including:
2409 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target
2410 @item @b{Flash Programing} Some chips program the flash directly via JTAG.
2411 Others do it indirectly, making a CPU do it.
2412 @item @b{Program Download} Using the same CPU support GDB uses,
2413 you can initialize a DRAM controller, download code to DRAM, and then
2414 start running that code.
2415 @item @b{Boundary Scan} Most chips support boundary scan, which
2416 helps test for board assembly problems like solder bridges
2417 and missing connections
2420 OpenOCD must know about the active TAPs on your board(s).
2421 Setting up the TAPs is the core task of your configuration files.
2422 Once those TAPs are set up, you can pass their names to code
2423 which sets up CPUs and exports them as GDB targets,
2424 probes flash memory, performs low-level JTAG operations, and more.
2426 @section Scan Chains
2429 TAPs are part of a hardware @dfn{scan chain},
2430 which is daisy chain of TAPs.
2431 They also need to be added to
2432 OpenOCD's software mirror of that hardware list,
2433 giving each member a name and associating other data with it.
2434 Simple scan chains, with a single TAP, are common in
2435 systems with a single microcontroller or microprocessor.
2436 More complex chips may have several TAPs internally.
2437 Very complex scan chains might have a dozen or more TAPs:
2438 several in one chip, more in the next, and connecting
2439 to other boards with their own chips and TAPs.
2441 You can display the list with the @command{scan_chain} command.
2442 (Don't confuse this with the list displayed by the @command{targets}
2443 command, presented in the next chapter.
2444 That only displays TAPs for CPUs which are configured as
2446 Here's what the scan chain might look like for a chip more than one TAP:
2449 TapName Enabled IdCode Expected IrLen IrCap IrMask Instr
2450 -- ------------------ ------- ---------- ---------- ----- ----- ------ -----
2451 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0 0 0x...
2452 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x1 0 0xc
2453 2 omap5912.unknown Y 0x00000000 0x00000000 8 0 0 0xff
2456 Unfortunately those TAPs can't always be autoconfigured,
2457 because not all devices provide good support for that.
2458 JTAG doesn't require supporting IDCODE instructions, and
2459 chips with JTAG routers may not link TAPs into the chain
2460 until they are told to do so.
2462 The configuration mechanism currently supported by OpenOCD
2463 requires explicit configuration of all TAP devices using
2464 @command{jtag newtap} commands, as detailed later in this chapter.
2465 A command like this would declare one tap and name it @code{chip1.cpu}:
2468 jtag newtap chip1 cpu -irlen 7 -ircapture 0x01 -irmask 0x55
2471 Each target configuration file lists the TAPs provided
2473 Board configuration files combine all the targets on a board,
2475 Note that @emph{the order in which TAPs are declared is very important.}
2476 It must match the order in the JTAG scan chain, both inside
2477 a single chip and between them.
2478 @xref{FAQ TAP Order}.
2480 For example, the ST Microsystems STR912 chip has
2481 three separate TAPs@footnote{See the ST
2482 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
2483 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
2484 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
2485 To configure those taps, @file{target/str912.cfg}
2486 includes commands something like this:
2489 jtag newtap str912 flash ... params ...
2490 jtag newtap str912 cpu ... params ...
2491 jtag newtap str912 bs ... params ...
2494 Actual config files use a variable instead of literals like
2495 @option{str912}, to support more than one chip of each type.
2496 @xref{Config File Guidelines}.
2498 @deffn Command {jtag names}
2499 Returns the names of all current TAPs in the scan chain.
2500 Use @command{jtag cget} or @command{jtag tapisenabled}
2501 to examine attributes and state of each TAP.
2503 foreach t [jtag names] @{
2504 puts [format "TAP: %s\n" $t]
2509 @deffn Command {scan_chain}
2510 Displays the TAPs in the scan chain configuration,
2512 The set of TAPs listed by this command is fixed by
2513 exiting the OpenOCD configuration stage,
2514 but systems with a JTAG router can
2515 enable or disable TAPs dynamically.
2516 In addition to the enable/disable status, the contents of
2517 each TAP's instruction register can also change.
2520 @c FIXME! "jtag cget" should be able to return all TAP
2521 @c attributes, like "$target_name cget" does for targets.
2523 @c Probably want "jtag eventlist", and a "tap-reset" event
2524 @c (on entry to RESET state).
2529 When TAP objects are declared with @command{jtag newtap},
2530 a @dfn{dotted.name} is created for the TAP, combining the
2531 name of a module (usually a chip) and a label for the TAP.
2532 For example: @code{xilinx.tap}, @code{str912.flash},
2533 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
2534 Many other commands use that dotted.name to manipulate or
2535 refer to the TAP. For example, CPU configuration uses the
2536 name, as does declaration of NAND or NOR flash banks.
2538 The components of a dotted name should follow ``C'' symbol
2539 name rules: start with an alphabetic character, then numbers
2540 and underscores are OK; while others (including dots!) are not.
2543 In older code, JTAG TAPs were numbered from 0..N.
2544 This feature is still present.
2545 However its use is highly discouraged, and
2546 should not be relied on; it will be removed by mid-2010.
2547 Update all of your scripts to use TAP names rather than numbers,
2548 by paying attention to the runtime warnings they trigger.
2549 Using TAP numbers in target configuration scripts prevents
2550 reusing those scripts on boards with multiple targets.
2553 @section TAP Declaration Commands
2555 @c shouldn't this be(come) a {Config Command}?
2556 @anchor{jtag newtap}
2557 @deffn Command {jtag newtap} chipname tapname configparams...
2558 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
2559 and configured according to the various @var{configparams}.
2561 The @var{chipname} is a symbolic name for the chip.
2562 Conventionally target config files use @code{$_CHIPNAME},
2563 defaulting to the model name given by the chip vendor but
2566 @cindex TAP naming convention
2567 The @var{tapname} reflects the role of that TAP,
2568 and should follow this convention:
2571 @item @code{bs} -- For boundary scan if this is a seperate TAP;
2572 @item @code{cpu} -- The main CPU of the chip, alternatively
2573 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
2574 @code{arm1} and @code{arm2} on chips two ARMs, and so forth;
2575 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
2576 @item @code{flash} -- If the chip has a flash TAP, like the str912;
2577 @item @code{jrc} -- For JTAG route controller (example: the ICEpick modules
2578 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
2579 @item @code{tap} -- Should be used only FPGA or CPLD like devices
2581 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
2582 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
2583 For example, the Freescale IMX31 has a SDMA (Smart DMA) with
2584 a JTAG TAP; that TAP should be named @code{sdma}.
2587 Every TAP requires at least the following @var{configparams}:
2590 @item @code{-irlen} @var{NUMBER}
2591 @*The length in bits of the
2592 instruction register, such as 4 or 5 bits.
2595 A TAP may also provide optional @var{configparams}:
2598 @item @code{-disable} (or @code{-enable})
2599 @*Use the @code{-disable} parameter to flag a TAP which is not
2600 linked in to the scan chain after a reset using either TRST
2601 or the JTAG state machine's @sc{reset} state.
2602 You may use @code{-enable} to highlight the default state
2603 (the TAP is linked in).
2604 @xref{Enabling and Disabling TAPs}.
2605 @item @code{-expected-id} @var{number}
2606 @*A non-zero @var{number} represents a 32-bit IDCODE
2607 which you expect to find when the scan chain is examined.
2608 These codes are not required by all JTAG devices.
2609 @emph{Repeat the option} as many times as required if more than one
2610 ID code could appear (for example, multiple versions).
2611 Specify @var{number} as zero to suppress warnings about IDCODE
2612 values that were found but not included in the list.
2613 @item @code{-ircapture} @var{NUMBER}
2614 @*The bit pattern loaded by the TAP into the JTAG shift register
2615 on entry to the @sc{ircapture} state, such as 0x01.
2616 JTAG requires the two LSBs of this value to be 01.
2617 By default, @code{-ircapture} and @code{-irmask} are set
2618 up to verify that two-bit value; but you may provide
2619 additional bits, if you know them.
2620 @item @code{-irmask} @var{NUMBER}
2621 @*A mask used with @code{-ircapture}
2622 to verify that instruction scans work correctly.
2623 Such scans are not used by OpenOCD except to verify that
2624 there seems to be no problems with JTAG scan chain operations.
2628 @section Other TAP commands
2630 @deffn Command {jtag cget} dotted.name @option{-event} name
2631 @deffnx Command {jtag configure} dotted.name @option{-event} name string
2632 At this writing this TAP attribute
2633 mechanism is used only for event handling.
2634 (It is not a direct analogue of the @code{cget}/@code{configure}
2635 mechanism for debugger targets.)
2636 See the next section for information about the available events.
2638 The @code{configure} subcommand assigns an event handler,
2639 a TCL string which is evaluated when the event is triggered.
2640 The @code{cget} subcommand returns that handler.
2648 OpenOCD includes two event mechanisms.
2649 The one presented here applies to all JTAG TAPs.
2650 The other applies to debugger targets,
2651 which are associated with certain TAPs.
2653 The TAP events currently defined are:
2656 @item @b{post-reset}
2657 @* The TAP has just completed a JTAG reset.
2658 The tap may still be in the JTAG @sc{reset} state.
2659 Handlers for these events might perform initialization sequences
2660 such as issuing TCK cycles, TMS sequences to ensure
2661 exit from the ARM SWD mode, and more.
2663 Because the scan chain has not yet been verified, handlers for these events
2664 @emph{should not issue commands which scan the JTAG IR or DR registers}
2665 of any particular target.
2666 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
2668 @* The scan chain has been reset and verified.
2669 This handler may enable TAPs as needed.
2670 @item @b{tap-disable}
2671 @* The TAP needs to be disabled. This handler should
2672 implement @command{jtag tapdisable}
2673 by issuing the relevant JTAG commands.
2674 @item @b{tap-enable}
2675 @* The TAP needs to be enabled. This handler should
2676 implement @command{jtag tapenable}
2677 by issuing the relevant JTAG commands.
2680 If you need some action after each JTAG reset, which isn't actually
2681 specific to any TAP (since you can't yet trust the scan chain's
2682 contents to be accurate), you might:
2685 jtag configure CHIP.jrc -event post-reset @{
2686 echo "JTAG Reset done"
2687 ... non-scan jtag operations to be done after reset
2692 @anchor{Enabling and Disabling TAPs}
2693 @section Enabling and Disabling TAPs
2694 @cindex JTAG Route Controller
2697 In some systems, a @dfn{JTAG Route Controller} (JRC)
2698 is used to enable and/or disable specific JTAG TAPs.
2699 Many ARM based chips from Texas Instruments include
2700 an ``ICEpick'' module, which is a JRC.
2701 Such chips include DaVinci and OMAP3 processors.
2703 A given TAP may not be visible until the JRC has been
2704 told to link it into the scan chain; and if the JRC
2705 has been told to unlink that TAP, it will no longer
2707 Such routers address problems that JTAG ``bypass mode''
2711 @item The scan chain can only go as fast as its slowest TAP.
2712 @item Having many TAPs slows instruction scans, since all
2713 TAPs receive new instructions.
2714 @item TAPs in the scan chain must be powered up, which wastes
2715 power and prevents debugging some power management mechanisms.
2718 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
2719 as implied by the existence of JTAG routers.
2720 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
2721 does include a kind of JTAG router functionality.
2723 @c (a) currently the event handlers don't seem to be able to
2724 @c fail in a way that could lead to no-change-of-state.
2726 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
2727 shown below, and is implemented using TAP event handlers.
2728 So for example, when defining a TAP for a CPU connected to
2729 a JTAG router, your @file{target.cfg} file
2730 should define TAP event handlers using
2731 code that looks something like this:
2734 jtag configure CHIP.cpu -event tap-enable @{
2735 ... jtag operations using CHIP.jrc
2737 jtag configure CHIP.cpu -event tap-disable @{
2738 ... jtag operations using CHIP.jrc
2742 Then you might want that CPU's TAP enabled almost all the time:
2745 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
2748 Note how that particular setup event handler declaration
2749 uses quotes to evaluate @code{$CHIP} when the event is configured.
2750 Using brackets @{ @} would cause it to be evaluated later,
2751 at runtime, when it might have a different value.
2753 @deffn Command {jtag tapdisable} dotted.name
2754 If necessary, disables the tap
2755 by sending it a @option{tap-disable} event.
2756 Returns the string "1" if the tap
2757 specified by @var{dotted.name} is enabled,
2758 and "0" if it is disabled.
2761 @deffn Command {jtag tapenable} dotted.name
2762 If necessary, enables the tap
2763 by sending it a @option{tap-enable} event.
2764 Returns the string "1" if the tap
2765 specified by @var{dotted.name} is enabled,
2766 and "0" if it is disabled.
2769 @deffn Command {jtag tapisenabled} dotted.name
2770 Returns the string "1" if the tap
2771 specified by @var{dotted.name} is enabled,
2772 and "0" if it is disabled.
2775 Humans will find the @command{scan_chain} command more helpful
2776 for querying the state of the JTAG taps.
2780 @node CPU Configuration
2781 @chapter CPU Configuration
2784 This chapter discusses how to set up GDB debug targets for CPUs.
2785 You can also access these targets without GDB
2786 (@pxref{Architecture and Core Commands},
2787 and @ref{Target State handling}) and
2788 through various kinds of NAND and NOR flash commands.
2789 If you have multiple CPUs you can have multiple such targets.
2791 We'll start by looking at how to examine the targets you have,
2792 then look at how to add one more target and how to configure it.
2794 @section Target List
2795 @cindex target, current
2796 @cindex target, list
2798 All targets that have been set up are part of a list,
2799 where each member has a name.
2800 That name should normally be the same as the TAP name.
2801 You can display the list with the @command{targets}
2803 This display often has only one CPU; here's what it might
2804 look like with more than one:
2806 TargetName Type Endian TapName State
2807 -- ------------------ ---------- ------ ------------------ ------------
2808 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
2809 1 MyTarget cortex_m3 little mychip.foo tap-disabled
2812 One member of that list is the @dfn{current target}, which
2813 is implicitly referenced by many commands.
2814 It's the one marked with a @code{*} near the target name.
2815 In particular, memory addresses often refer to the address
2816 space seen by that current target.
2817 Commands like @command{mdw} (memory display words)
2818 and @command{flash erase_address} (erase NOR flash blocks)
2819 are examples; and there are many more.
2821 Several commands let you examine the list of targets:
2823 @deffn Command {target count}
2824 @emph{Note: target numbers are deprecated; don't use them.
2825 They will be removed shortly after August 2010, including this command.
2826 Iterate target using @command{target names}, not by counting.}
2828 Returns the number of targets, @math{N}.
2829 The highest numbered target is @math{N - 1}.
2831 set c [target count]
2832 for @{ set x 0 @} @{ $x < $c @} @{ incr x @} @{
2833 # Assuming you have created this function
2834 print_target_details $x
2839 @deffn Command {target current}
2840 Returns the name of the current target.
2843 @deffn Command {target names}
2844 Lists the names of all current targets in the list.
2846 foreach t [target names] @{
2847 puts [format "Target: %s\n" $t]
2852 @deffn Command {target number} number
2853 @emph{Note: target numbers are deprecated; don't use them.
2854 They will be removed shortly after August 2010, including this command.}
2856 The list of targets is numbered starting at zero.
2857 This command returns the name of the target at index @var{number}.
2859 set thename [target number $x]
2860 puts [format "Target %d is: %s\n" $x $thename]
2864 @c yep, "target list" would have been better.
2865 @c plus maybe "target setdefault".
2867 @deffn Command targets [name]
2868 @emph{Note: the name of this command is plural. Other target
2869 command names are singular.}
2871 With no parameter, this command displays a table of all known
2872 targets in a user friendly form.
2874 With a parameter, this command sets the current target to
2875 the given target with the given @var{name}; this is
2876 only relevant on boards which have more than one target.
2879 @section Target CPU Types and Variants
2884 Each target has a @dfn{CPU type}, as shown in the output of
2885 the @command{targets} command. You need to specify that type
2886 when calling @command{target create}.
2887 The CPU type indicates more than just the instruction set.
2888 It also indicates how that instruction set is implemented,
2889 what kind of debug support it integrates,
2890 whether it has an MMU (and if so, what kind),
2891 what core-specific commands may be available
2892 (@pxref{Architecture and Core Commands}),
2895 For some CPU types, OpenOCD also defines @dfn{variants} which
2896 indicate differences that affect their handling.
2897 For example, a particular implementation bug might need to be
2898 worked around in some chip versions.
2900 It's easy to see what target types are supported,
2901 since there's a command to list them.
2902 However, there is currently no way to list what target variants
2903 are supported (other than by reading the OpenOCD source code).
2905 @anchor{target types}
2906 @deffn Command {target types}
2907 Lists all supported target types.
2908 At this writing, the supported CPU types and variants are:
2911 @item @code{arm11} -- this is a generation of ARMv6 cores
2912 @item @code{arm720t} -- this is an ARMv4 core
2913 @item @code{arm7tdmi} -- this is an ARMv4 core
2914 @item @code{arm920t} -- this is an ARMv5 core
2915 @item @code{arm926ejs} -- this is an ARMv5 core
2916 @item @code{arm966e} -- this is an ARMv5 core
2917 @item @code{arm9tdmi} -- this is an ARMv4 core
2918 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
2919 (Support for this is preliminary and incomplete.)
2920 @item @code{cortex_a8} -- this is an ARMv7 core
2921 @item @code{cortex_m3} -- this is an ARMv7 core, supporting only the
2922 compact Thumb2 instruction set. It supports one variant:
2924 @item @code{lm3s} ... Use this when debugging older Stellaris LM3S targets.
2925 This will cause OpenOCD to use a software reset rather than asserting
2926 SRST, to avoid a issue with clearing the debug registers.
2927 This is fixed in Fury Rev B, DustDevil Rev B, Tempest; these revisions will
2928 be detected and the normal reset behaviour used.
2930 @item @code{fa526} -- resembles arm920 (w/o Thumb)
2931 @item @code{feroceon} -- resembles arm926
2932 @item @code{mips_m4k} -- a MIPS core. This supports one variant:
2934 @item @code{ejtag_srst} ... Use this when debugging targets that do not
2935 provide a functional SRST line on the EJTAG connector. This causes
2936 OpenOCD to instead use an EJTAG software reset command to reset the
2938 You still need to enable @option{srst} on the @command{reset_config}
2939 command to enable OpenOCD hardware reset functionality.
2941 @item @code{xscale} -- this is actually an architecture,
2942 not a CPU type. It is based on the ARMv5 architecture.
2943 There are several variants defined:
2945 @item @code{ixp42x}, @code{ixp45x}, @code{ixp46x},
2946 @code{pxa27x} ... instruction register length is 7 bits
2947 @item @code{pxa250}, @code{pxa255},
2948 @code{pxa26x} ... instruction register length is 5 bits
2953 To avoid being confused by the variety of ARM based cores, remember
2954 this key point: @emph{ARM is a technology licencing company}.
2955 (See: @url{http://www.arm.com}.)
2956 The CPU name used by OpenOCD will reflect the CPU design that was
2957 licenced, not a vendor brand which incorporates that design.
2958 Name prefixes like arm7, arm9, arm11, and cortex
2959 reflect design generations;
2960 while names like ARMv4, ARMv5, ARMv6, and ARMv7
2961 reflect an architecture version implemented by a CPU design.
2963 @anchor{Target Configuration}
2964 @section Target Configuration
2966 Before creating a ``target'', you must have added its TAP to the scan chain.
2967 When you've added that TAP, you will have a @code{dotted.name}
2968 which is used to set up the CPU support.
2969 The chip-specific configuration file will normally configure its CPU(s)
2970 right after it adds all of the chip's TAPs to the scan chain.
2972 Although you can set up a target in one step, it's often clearer if you
2973 use shorter commands and do it in two steps: create it, then configure
2975 All operations on the target after it's created will use a new
2976 command, created as part of target creation.
2978 The two main things to configure after target creation are
2979 a work area, which usually has target-specific defaults even
2980 if the board setup code overrides them later;
2981 and event handlers (@pxref{Target Events}), which tend
2982 to be much more board-specific.
2983 The key steps you use might look something like this
2986 target create MyTarget cortex_m3 -chain-position mychip.cpu
2987 $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
2988 $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
2989 $MyTarget configure -event reset-init @{ myboard_reinit @}
2992 You should specify a working area if you can; typically it uses some
2994 Such a working area can speed up many things, including bulk
2995 writes to target memory;
2996 flash operations like checking to see if memory needs to be erased;
2997 GDB memory checksumming;
3001 On more complex chips, the work area can become
3002 inaccessible when application code
3003 (such as an operating system)
3004 enables or disables the MMU.
3005 For example, the particular MMU context used to acess the virtual
3006 address will probably matter ... and that context might not have
3007 easy access to other addresses needed.
3008 At this writing, OpenOCD doesn't have much MMU intelligence.
3011 It's often very useful to define a @code{reset-init} event handler.
3012 For systems that are normally used with a boot loader,
3013 common tasks include updating clocks and initializing memory
3015 That may be needed to let you write the boot loader into flash,
3016 in order to ``de-brick'' your board; or to load programs into
3017 external DDR memory without having run the boot loader.
3019 @deffn Command {target create} target_name type configparams...
3020 This command creates a GDB debug target that refers to a specific JTAG tap.
3021 It enters that target into a list, and creates a new
3022 command (@command{@var{target_name}}) which is used for various
3023 purposes including additional configuration.
3026 @item @var{target_name} ... is the name of the debug target.
3027 By convention this should be the same as the @emph{dotted.name}
3028 of the TAP associated with this target, which must be specified here
3029 using the @code{-chain-position @var{dotted.name}} configparam.
3031 This name is also used to create the target object command,
3032 referred to here as @command{$target_name},
3033 and in other places the target needs to be identified.
3034 @item @var{type} ... specifies the target type. @xref{target types}.
3035 @item @var{configparams} ... all parameters accepted by
3036 @command{$target_name configure} are permitted.
3037 If the target is big-endian, set it here with @code{-endian big}.
3038 If the variant matters, set it here with @code{-variant}.
3040 You @emph{must} set the @code{-chain-position @var{dotted.name}} here.
3044 @deffn Command {$target_name configure} configparams...
3045 The options accepted by this command may also be
3046 specified as parameters to @command{target create}.
3047 Their values can later be queried one at a time by
3048 using the @command{$target_name cget} command.
3050 @emph{Warning:} changing some of these after setup is dangerous.
3051 For example, moving a target from one TAP to another;
3052 and changing its endianness or variant.
3056 @item @code{-chain-position} @var{dotted.name} -- names the TAP
3057 used to access this target.
3059 @item @code{-endian} (@option{big}|@option{little}) -- specifies
3060 whether the CPU uses big or little endian conventions
3062 @item @code{-event} @var{event_name} @var{event_body} --
3063 @xref{Target Events}.
3064 Note that this updates a list of named event handlers.
3065 Calling this twice with two different event names assigns
3066 two different handlers, but calling it twice with the
3067 same event name assigns only one handler.
3069 @item @code{-variant} @var{name} -- specifies a variant of the target,
3070 which OpenOCD needs to know about.
3072 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
3073 whether the work area gets backed up; by default,
3074 @emph{it is not backed up.}
3075 When possible, use a working_area that doesn't need to be backed up,
3076 since performing a backup slows down operations.
3077 For example, the beginning of an SRAM block is likely to
3078 be used by most build systems, but the end is often unused.
3080 @item @code{-work-area-size} @var{size} -- specify/set the work area
3082 @item @code{-work-area-phys} @var{address} -- set the work area
3083 base @var{address} to be used when no MMU is active.
3085 @item @code{-work-area-virt} @var{address} -- set the work area
3086 base @var{address} to be used when an MMU is active.
3091 @section Other $target_name Commands
3092 @cindex object command
3094 The Tcl/Tk language has the concept of object commands,
3095 and OpenOCD adopts that same model for targets.
3097 A good Tk example is a on screen button.
3098 Once a button is created a button
3099 has a name (a path in Tk terms) and that name is useable as a first
3100 class command. For example in Tk, one can create a button and later
3101 configure it like this:
3105 button .foobar -background red -command @{ foo @}
3107 .foobar configure -foreground blue
3109 set x [.foobar cget -background]
3111 puts [format "The button is %s" $x]
3114 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
3115 button, and its object commands are invoked the same way.
3118 str912.cpu mww 0x1234 0x42
3119 omap3530.cpu mww 0x5555 123
3122 The commands supported by OpenOCD target objects are:
3124 @deffn Command {$target_name arp_examine}
3125 @deffnx Command {$target_name arp_halt}
3126 @deffnx Command {$target_name arp_poll}
3127 @deffnx Command {$target_name arp_reset}
3128 @deffnx Command {$target_name arp_waitstate}
3129 Internal OpenOCD scripts (most notably @file{startup.tcl})
3130 use these to deal with specific reset cases.
3131 They are not otherwise documented here.
3134 @deffn Command {$target_name array2mem} arrayname width address count
3135 @deffnx Command {$target_name mem2array} arrayname width address count
3136 These provide an efficient script-oriented interface to memory.
3137 The @code{array2mem} primitive writes bytes, halfwords, or words;
3138 while @code{mem2array} reads them.
3139 In both cases, the TCL side uses an array, and
3140 the target side uses raw memory.
3142 The efficiency comes from enabling the use of
3143 bulk JTAG data transfer operations.
3144 The script orientation comes from working with data
3145 values that are packaged for use by TCL scripts;
3146 @command{mdw} type primitives only print data they retrieve,
3147 and neither store nor return those values.
3150 @item @var{arrayname} ... is the name of an array variable
3151 @item @var{width} ... is 8/16/32 - indicating the memory access size
3152 @item @var{address} ... is the target memory address
3153 @item @var{count} ... is the number of elements to process
3157 @deffn Command {$target_name cget} queryparm
3158 Each configuration parameter accepted by
3159 @command{$target_name configure}
3160 can be individually queried, to return its current value.
3161 The @var{queryparm} is a parameter name
3162 accepted by that command, such as @code{-work-area-phys}.
3163 There are a few special cases:
3166 @item @code{-event} @var{event_name} -- returns the handler for the
3167 event named @var{event_name}.
3168 This is a special case because setting a handler requires
3170 @item @code{-type} -- returns the target type.
3171 This is a special case because this is set using
3172 @command{target create} and can't be changed
3173 using @command{$target_name configure}.
3176 For example, if you wanted to summarize information about
3177 all the targets you might use something like this:
3180 foreach name [target names] @{
3181 set y [$name cget -endian]
3182 set z [$name cget -type]
3183 puts [format "Chip %d is %s, Endian: %s, type: %s" \
3189 @anchor{target curstate}
3190 @deffn Command {$target_name curstate}
3191 Displays the current target state:
3192 @code{debug-running},
3195 @code{running}, or @code{unknown}.
3196 (Also, @pxref{Event Polling}.)
3199 @deffn Command {$target_name eventlist}
3200 Displays a table listing all event handlers
3201 currently associated with this target.
3202 @xref{Target Events}.
3205 @deffn Command {$target_name invoke-event} event_name
3206 Invokes the handler for the event named @var{event_name}.
3207 (This is primarily intended for use by OpenOCD framework
3208 code, for example by the reset code in @file{startup.tcl}.)
3211 @deffn Command {$target_name mdw} addr [count]
3212 @deffnx Command {$target_name mdh} addr [count]
3213 @deffnx Command {$target_name mdb} addr [count]
3214 Display contents of address @var{addr}, as
3215 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
3216 or 8-bit bytes (@command{mdb}).
3217 If @var{count} is specified, displays that many units.
3218 (If you want to manipulate the data instead of displaying it,
3219 see the @code{mem2array} primitives.)
3222 @deffn Command {$target_name mww} addr word
3223 @deffnx Command {$target_name mwh} addr halfword
3224 @deffnx Command {$target_name mwb} addr byte
3225 Writes the specified @var{word} (32 bits),
3226 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
3227 at the specified address @var{addr}.
3230 @anchor{Target Events}
3231 @section Target Events
3232 @cindex target events
3234 At various times, certain things can happen, or you want them to happen.
3237 @item What should happen when GDB connects? Should your target reset?
3238 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
3239 @item During reset, do you need to write to certain memory locations
3240 to set up system clocks or
3241 to reconfigure the SDRAM?
3244 All of the above items can be addressed by target event handlers.
3245 These are set up by @command{$target_name configure -event} or
3246 @command{target create ... -event}.
3248 The programmer's model matches the @code{-command} option used in Tcl/Tk
3249 buttons and events. The two examples below act the same, but one creates
3250 and invokes a small procedure while the other inlines it.
3253 proc my_attach_proc @{ @} @{
3257 mychip.cpu configure -event gdb-attach my_attach_proc
3258 mychip.cpu configure -event gdb-attach @{
3264 The following target events are defined:
3267 @item @b{debug-halted}
3268 @* The target has halted for debug reasons (i.e.: breakpoint)
3269 @item @b{debug-resumed}
3270 @* The target has resumed (i.e.: gdb said run)
3271 @item @b{early-halted}
3272 @* Occurs early in the halt process
3274 @item @b{examine-end}
3275 @* Currently not used (goal: when JTAG examine completes)
3276 @item @b{examine-start}
3277 @* Currently not used (goal: when JTAG examine starts)
3279 @item @b{gdb-attach}
3280 @* When GDB connects
3281 @item @b{gdb-detach}
3282 @* When GDB disconnects
3284 @* When the target has halted and GDB is not doing anything (see early halt)
3285 @item @b{gdb-flash-erase-start}
3286 @* Before the GDB flash process tries to erase the flash
3287 @item @b{gdb-flash-erase-end}
3288 @* After the GDB flash process has finished erasing the flash
3289 @item @b{gdb-flash-write-start}
3290 @* Before GDB writes to the flash
3291 @item @b{gdb-flash-write-end}
3292 @* After GDB writes to the flash
3294 @* Before the target steps, gdb is trying to start/resume the target
3296 @* The target has halted
3298 @item @b{old-gdb_program_config}
3299 @* DO NOT USE THIS: Used internally
3300 @item @b{old-pre_resume}
3301 @* DO NOT USE THIS: Used internally
3303 @item @b{reset-assert-pre}
3304 @* Issued as part of @command{reset} processing
3305 after @command{reset_init} was triggered
3306 but before SRST alone is re-asserted on the tap.
3307 @item @b{reset-assert-post}
3308 @* Issued as part of @command{reset} processing
3309 when SRST is asserted on the tap.
3310 @item @b{reset-deassert-pre}
3311 @* Issued as part of @command{reset} processing
3312 when SRST is about to be released on the tap.
3313 @item @b{reset-deassert-post}
3314 @* Issued as part of @command{reset} processing
3315 when SRST has been released on the tap.
3317 @* Issued as the final step in @command{reset} processing.
3319 @item @b{reset-halt-post}
3320 @* Currently not used
3321 @item @b{reset-halt-pre}
3322 @* Currently not used
3324 @item @b{reset-init}
3325 @* Used by @b{reset init} command for board-specific initialization.
3326 This event fires after @emph{reset-deassert-post}.
3328 This is where you would configure PLLs and clocking, set up DRAM so
3329 you can download programs that don't fit in on-chip SRAM, set up pin
3330 multiplexing, and so on.
3331 (You may be able to switch to a fast JTAG clock rate here, after
3332 the target clocks are fully set up.)
3333 @item @b{reset-start}
3334 @* Issued as part of @command{reset} processing
3335 before @command{reset_init} is called.
3337 This is the most robust place to use @command{jtag_rclk}
3338 or @command{jtag_khz} to switch to a low JTAG clock rate,
3339 when reset disables PLLs needed to use a fast clock.
3341 @item @b{reset-wait-pos}
3342 @* Currently not used
3343 @item @b{reset-wait-pre}
3344 @* Currently not used
3346 @item @b{resume-start}
3347 @* Before any target is resumed
3348 @item @b{resume-end}
3349 @* After all targets have resumed
3353 @* Target has resumed
3357 @node Flash Commands
3358 @chapter Flash Commands
3360 OpenOCD has different commands for NOR and NAND flash;
3361 the ``flash'' command works with NOR flash, while
3362 the ``nand'' command works with NAND flash.
3363 This partially reflects different hardware technologies:
3364 NOR flash usually supports direct CPU instruction and data bus access,
3365 while data from a NAND flash must be copied to memory before it can be
3366 used. (SPI flash must also be copied to memory before use.)
3367 However, the documentation also uses ``flash'' as a generic term;
3368 for example, ``Put flash configuration in board-specific files''.
3372 @item Configure via the command @command{flash bank}
3373 @* Do this in a board-specific configuration file,
3374 passing parameters as needed by the driver.
3375 @item Operate on the flash via @command{flash subcommand}
3376 @* Often commands to manipulate the flash are typed by a human, or run
3377 via a script in some automated way. Common tasks include writing a
3378 boot loader, operating system, or other data.
3380 @* Flashing via GDB requires the flash be configured via ``flash
3381 bank'', and the GDB flash features be enabled.
3382 @xref{GDB Configuration}.
3385 Many CPUs have the ablity to ``boot'' from the first flash bank.
3386 This means that misprogramming that bank can ``brick'' a system,
3387 so that it can't boot.
3388 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
3389 board by (re)installing working boot firmware.
3391 @anchor{NOR Configuration}
3392 @section Flash Configuration Commands
3393 @cindex flash configuration
3395 @deffn {Config Command} {flash bank} driver base size chip_width bus_width target [driver_options]
3396 Configures a flash bank which provides persistent storage
3397 for addresses from @math{base} to @math{base + size - 1}.
3398 These banks will often be visible to GDB through the target's memory map.
3399 In some cases, configuring a flash bank will activate extra commands;
3400 see the driver-specific documentation.
3403 @item @var{driver} ... identifies the controller driver
3404 associated with the flash bank being declared.
3405 This is usually @code{cfi} for external flash, or else
3406 the name of a microcontroller with embedded flash memory.
3407 @xref{Flash Driver List}.
3408 @item @var{base} ... Base address of the flash chip.
3409 @item @var{size} ... Size of the chip, in bytes.
3410 For some drivers, this value is detected from the hardware.
3411 @item @var{chip_width} ... Width of the flash chip, in bytes;
3412 ignored for most microcontroller drivers.
3413 @item @var{bus_width} ... Width of the data bus used to access the
3414 chip, in bytes; ignored for most microcontroller drivers.
3415 @item @var{target} ... Names the target used to issue
3416 commands to the flash controller.
3417 @comment Actually, it's currently a controller-specific parameter...
3418 @item @var{driver_options} ... drivers may support, or require,
3419 additional parameters. See the driver-specific documentation
3420 for more information.
3423 This command is not available after OpenOCD initialization has completed.
3424 Use it in board specific configuration files, not interactively.
3428 @comment the REAL name for this command is "ocd_flash_banks"
3429 @comment less confusing would be: "flash list" (like "nand list")
3430 @deffn Command {flash banks}
3431 Prints a one-line summary of each device declared
3432 using @command{flash bank}, numbered from zero.
3433 Note that this is the @emph{plural} form;
3434 the @emph{singular} form is a very different command.
3437 @deffn Command {flash probe} num
3438 Identify the flash, or validate the parameters of the configured flash. Operation
3439 depends on the flash type.
3440 The @var{num} parameter is a value shown by @command{flash banks}.
3441 Most flash commands will implicitly @emph{autoprobe} the bank;
3442 flash drivers can distinguish between probing and autoprobing,
3443 but most don't bother.
3446 @section Erasing, Reading, Writing to Flash
3447 @cindex flash erasing
3448 @cindex flash reading
3449 @cindex flash writing
3450 @cindex flash programming
3452 One feature distinguishing NOR flash from NAND or serial flash technologies
3453 is that for read access, it acts exactly like any other addressible memory.
3454 This means you can use normal memory read commands like @command{mdw} or
3455 @command{dump_image} with it, with no special @command{flash} subcommands.
3456 @xref{Memory access}, and @ref{Image access}.
3458 Write access works differently. Flash memory normally needs to be erased
3459 before it's written. Erasing a sector turns all of its bits to ones, and
3460 writing can turn ones into zeroes. This is why there are special commands
3461 for interactive erasing and writing, and why GDB needs to know which parts
3462 of the address space hold NOR flash memory.
3465 Most of these erase and write commands leverage the fact that NOR flash
3466 chips consume target address space. They implicitly refer to the current
3467 JTAG target, and map from an address in that target's address space
3468 back to a flash bank.
3469 @comment In May 2009, those mappings may fail if any bank associated
3470 @comment with that target doesn't succesfuly autoprobe ... bug worth fixing?
3471 A few commands use abstract addressing based on bank and sector numbers,
3472 and don't depend on searching the current target and its address space.
3473 Avoid confusing the two command models.
3476 Some flash chips implement software protection against accidental writes,
3477 since such buggy writes could in some cases ``brick'' a system.
3478 For such systems, erasing and writing may require sector protection to be
3480 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
3481 and AT91SAM7 on-chip flash.
3482 @xref{flash protect}.
3484 @anchor{flash erase_sector}
3485 @deffn Command {flash erase_sector} num first last
3486 Erase sectors in bank @var{num}, starting at sector @var{first}
3487 up to and including @var{last}.
3488 Sector numbering starts at 0.
3489 Providing a @var{last} sector of @option{last}
3490 specifies "to the end of the flash bank".
3491 The @var{num} parameter is a value shown by @command{flash banks}.
3494 @deffn Command {flash erase_address} address length
3495 Erase sectors starting at @var{address} for @var{length} bytes.
3496 The flash bank to use is inferred from the @var{address}, and
3497 the specified length must stay within that bank.
3498 As a special case, when @var{length} is zero and @var{address} is
3499 the start of the bank, the whole flash is erased.
3502 @deffn Command {flash fillw} address word length
3503 @deffnx Command {flash fillh} address halfword length
3504 @deffnx Command {flash fillb} address byte length
3505 Fills flash memory with the specified @var{word} (32 bits),
3506 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
3507 starting at @var{address} and continuing
3508 for @var{length} units (word/halfword/byte).
3509 No erasure is done before writing; when needed, that must be done
3510 before issuing this command.
3511 Writes are done in blocks of up to 1024 bytes, and each write is
3512 verified by reading back the data and comparing it to what was written.
3513 The flash bank to use is inferred from the @var{address} of
3514 each block, and the specified length must stay within that bank.
3516 @comment no current checks for errors if fill blocks touch multiple banks!
3518 @anchor{flash write_bank}
3519 @deffn Command {flash write_bank} num filename offset
3520 Write the binary @file{filename} to flash bank @var{num},
3521 starting at @var{offset} bytes from the beginning of the bank.
3522 The @var{num} parameter is a value shown by @command{flash banks}.
3525 @anchor{flash write_image}
3526 @deffn Command {flash write_image} [erase] filename [offset] [type]
3527 Write the image @file{filename} to the current target's flash bank(s).
3528 A relocation @var{offset} may be specified, in which case it is added
3529 to the base address for each section in the image.
3530 The file [@var{type}] can be specified
3531 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
3532 @option{elf} (ELF file), @option{s19} (Motorola s19).
3533 @option{mem}, or @option{builder}.
3534 The relevant flash sectors will be erased prior to programming
3535 if the @option{erase} parameter is given.
3536 The flash bank to use is inferred from the @var{address} of
3540 @section Other Flash commands
3541 @cindex flash protection
3543 @deffn Command {flash erase_check} num
3544 Check erase state of sectors in flash bank @var{num},
3545 and display that status.
3546 The @var{num} parameter is a value shown by @command{flash banks}.
3547 This is the only operation that
3548 updates the erase state information displayed by @option{flash info}. That means you have
3549 to issue a @command{flash erase_check} command after erasing or programming the device
3550 to get updated information.
3551 (Code execution may have invalidated any state records kept by OpenOCD.)
3554 @deffn Command {flash info} num
3555 Print info about flash bank @var{num}
3556 The @var{num} parameter is a value shown by @command{flash banks}.
3557 The information includes per-sector protect status.
3560 @anchor{flash protect}
3561 @deffn Command {flash protect} num first last (@option{on}|@option{off})
3562 Enable (@option{on}) or disable (@option{off}) protection of flash sectors
3563 in flash bank @var{num}, starting at sector @var{first}
3564 and continuing up to and including @var{last}.
3565 Providing a @var{last} sector of @option{last}
3566 specifies "to the end of the flash bank".
3567 The @var{num} parameter is a value shown by @command{flash banks}.
3570 @deffn Command {flash protect_check} num
3571 Check protection state of sectors in flash bank @var{num}.
3572 The @var{num} parameter is a value shown by @command{flash banks}.
3573 @comment @option{flash erase_sector} using the same syntax.
3576 @anchor{Flash Driver List}
3577 @section Flash Drivers, Options, and Commands
3578 As noted above, the @command{flash bank} command requires a driver name,
3579 and allows driver-specific options and behaviors.
3580 Some drivers also activate driver-specific commands.
3582 @subsection External Flash
3584 @deffn {Flash Driver} cfi
3585 @cindex Common Flash Interface
3587 The ``Common Flash Interface'' (CFI) is the main standard for
3588 external NOR flash chips, each of which connects to a
3589 specific external chip select on the CPU.
3590 Frequently the first such chip is used to boot the system.
3591 Your board's @code{reset-init} handler might need to
3592 configure additional chip selects using other commands (like: @command{mww} to
3593 configure a bus and its timings) , or
3594 perhaps configure a GPIO pin that controls the ``write protect'' pin
3596 The CFI driver can use a target-specific working area to significantly
3599 The CFI driver can accept the following optional parameters, in any order:
3602 @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
3603 like AM29LV010 and similar types.
3604 @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
3607 To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
3608 wide on a sixteen bit bus:
3611 flash bank cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
3612 flash bank cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
3614 @c "cfi part_id" disabled
3617 @subsection Internal Flash (Microcontrollers)
3619 @deffn {Flash Driver} aduc702x
3620 The ADUC702x analog microcontrollers from Analog Devices
3621 include internal flash and use ARM7TDMI cores.
3622 The aduc702x flash driver works with models ADUC7019 through ADUC7028.
3623 The setup command only requires the @var{target} argument
3624 since all devices in this family have the same memory layout.
3627 flash bank aduc702x 0 0 0 0 $_TARGETNAME
3631 @deffn {Flash Driver} at91sam3
3633 All members of the AT91SAM3 microcontroller family from
3634 Atmel include internal flash and use ARM's Cortex-M3 core. The driver
3635 currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
3636 that the driver was orginaly developed and tested using the
3637 AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in
3638 the family was cribbed from the data sheet. @emph{Note to future
3639 readers/updaters: Please remove this worrysome comment after other
3640 chips are confirmed.}
3642 The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
3643 have one flash bank. In all cases the flash banks are at
3644 the following fixed locations:
3647 # Flash bank 0 - all chips
3648 flash bank at91sam3 0x00080000 0 1 1 $_TARGETNAME
3649 # Flash bank 1 - only 256K chips
3650 flash bank at91sam3 0x00100000 0 1 1 $_TARGETNAME
3653 Internally, the AT91SAM3 flash memory is organized as follows.
3654 Unlike the AT91SAM7 chips, these are not used as parameters
3655 to the @command{flash bank} command:
3658 @item @emph{N-Banks:} 256K chips have 2 banks, others have 1 bank.
3659 @item @emph{Bank Size:} 128K/64K Per flash bank
3660 @item @emph{Sectors:} 16 or 8 per bank
3661 @item @emph{SectorSize:} 8K Per Sector
3662 @item @emph{PageSize:} 256 bytes per page. Note that OpenOCD operates on 'sector' sizes, not page sizes.
3665 The AT91SAM3 driver adds some additional commands:
3667 @deffn Command {at91sam3 gpnvm}
3668 @deffnx Command {at91sam3 gpnvm clear} number
3669 @deffnx Command {at91sam3 gpnvm set} number
3670 @deffnx Command {at91sam3 gpnvm show} [@option{all}|number]
3671 With no parameters, @command{show} or @command{show all},
3672 shows the status of all GPNVM bits.
3673 With @command{show} @var{number}, displays that bit.
3675 With @command{set} @var{number} or @command{clear} @var{number},
3676 modifies that GPNVM bit.
3679 @deffn Command {at91sam3 info}
3680 This command attempts to display information about the AT91SAM3
3681 chip. @emph{First} it read the @code{CHIPID_CIDR} [address 0x400e0740, see
3682 Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
3683 document id: doc6430A] and decodes the values. @emph{Second} it reads the
3684 various clock configuration registers and attempts to display how it
3685 believes the chip is configured. By default, the SLOWCLK is assumed to
3686 be 32768 Hz, see the command @command{at91sam3 slowclk}.
3689 @deffn Command {at91sam3 slowclk} [value]
3690 This command shows/sets the slow clock frequency used in the
3691 @command{at91sam3 info} command calculations above.
3695 @deffn {Flash Driver} at91sam7
3696 All members of the AT91SAM7 microcontroller family from Atmel include
3697 internal flash and use ARM7TDMI cores. The driver automatically
3698 recognizes a number of these chips using the chip identification
3699 register, and autoconfigures itself.
3702 flash bank at91sam7 0 0 0 0 $_TARGETNAME
3705 For chips which are not recognized by the controller driver, you must
3706 provide additional parameters in the following order:
3709 @item @var{chip_model} ... label used with @command{flash info}
3711 @item @var{sectors_per_bank}
3712 @item @var{pages_per_sector}
3713 @item @var{pages_size}
3714 @item @var{num_nvm_bits}
3715 @item @var{freq_khz} ... required if an external clock is provided,
3716 optional (but recommended) when the oscillator frequency is known
3719 It is recommended that you provide zeroes for all of those values
3720 except the clock frequency, so that everything except that frequency
3721 will be autoconfigured.
3722 Knowing the frequency helps ensure correct timings for flash access.
3724 The flash controller handles erases automatically on a page (128/256 byte)
3725 basis, so explicit erase commands are not necessary for flash programming.
3726 However, there is an ``EraseAll`` command that can erase an entire flash
3727 plane (of up to 256KB), and it will be used automatically when you issue
3728 @command{flash erase_sector} or @command{flash erase_address} commands.
3730 @deffn Command {at91sam7 gpnvm} bitnum (@option{set}|@option{clear})
3731 Set or clear a ``General Purpose Non-Volatle Memory'' (GPNVM)
3732 bit for the processor. Each processor has a number of such bits,
3733 used for controlling features such as brownout detection (so they
3734 are not truly general purpose).
3736 This assumes that the first flash bank (number 0) is associated with
3737 the appropriate at91sam7 target.
3742 @deffn {Flash Driver} avr
3743 The AVR 8-bit microcontrollers from Atmel integrate flash memory.
3744 @emph{The current implementation is incomplete.}
3745 @comment - defines mass_erase ... pointless given flash_erase_address
3748 @deffn {Flash Driver} ecosflash
3749 @emph{No idea what this is...}
3750 The @var{ecosflash} driver defines one mandatory parameter,
3751 the name of a modules of target code which is downloaded
3755 @deffn {Flash Driver} lpc2000
3756 Most members of the LPC1700 and LPC2000 microcontroller families from NXP
3757 include internal flash and use Cortex-M3 (LPC1700) or ARM7TDMI (LPC2000) cores.
3760 There are LPC2000 devices which are not supported by the @var{lpc2000}
3762 The LPC2888 is supported by the @var{lpc288x} driver.
3763 The LPC29xx family is supported by the @var{lpc2900} driver.
3766 The @var{lpc2000} driver defines two mandatory and one optional parameters,
3767 which must appear in the following order:
3770 @item @var{variant} ... required, may be
3771 @var{lpc2000_v1} (older LPC21xx and LPC22xx)
3772 @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
3773 or @var{lpc1700} (LPC175x and LPC176x)
3774 @item @var{clock_kHz} ... the frequency, in kiloHertz,
3775 at which the core is running
3776 @item @var{calc_checksum} ... optional (but you probably want to provide this!),
3777 telling the driver to calculate a valid checksum for the exception vector table.
3780 LPC flashes don't require the chip and bus width to be specified.
3783 flash bank lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
3784 lpc2000_v2 14765 calc_checksum
3787 @deffn {Command} {lpc2000 part_id} bank
3788 Displays the four byte part identifier associated with
3789 the specified flash @var{bank}.
3793 @deffn {Flash Driver} lpc288x
3794 The LPC2888 microcontroller from NXP needs slightly different flash
3795 support from its lpc2000 siblings.
3796 The @var{lpc288x} driver defines one mandatory parameter,
3797 the programming clock rate in Hz.
3798 LPC flashes don't require the chip and bus width to be specified.
3801 flash bank lpc288x 0 0 0 0 $_TARGETNAME 12000000
3805 @deffn {Flash Driver} lpc2900
3806 This driver supports the LPC29xx ARM968E based microcontroller family
3809 The predefined parameters @var{base}, @var{size}, @var{chip_width} and
3810 @var{bus_width} of the @code{flash bank} command are ignored. Flash size and
3811 sector layout are auto-configured by the driver.
3812 The driver has one additional mandatory parameter: The CPU clock rate
3813 (in kHz) at the time the flash operations will take place. Most of the time this
3814 will not be the crystal frequency, but a higher PLL frequency. The
3815 @code{reset-init} event handler in the board script is usually the place where
3818 The driver rejects flashless devices (currently the LPC2930).
3820 The EEPROM in LPC2900 devices is not mapped directly into the address space.
3821 It must be handled much more like NAND flash memory, and will therefore be
3822 handled by a separate @code{lpc2900_eeprom} driver (not yet available).
3824 Sector protection in terms of the LPC2900 is handled transparently. Every time a
3825 sector needs to be erased or programmed, it is automatically unprotected.
3826 What is shown as protection status in the @code{flash info} command, is
3827 actually the LPC2900 @emph{sector security}. This is a mechanism to prevent a
3828 sector from ever being erased or programmed again. As this is an irreversible
3829 mechanism, it is handled by a special command (@code{lpc2900 secure_sector}),
3830 and not by the standard @code{flash protect} command.
3832 Example for a 125 MHz clock frequency:
3834 flash bank lpc2900 0 0 0 0 $_TARGETNAME 125000
3837 Some @code{lpc2900}-specific commands are defined. In the following command list,
3838 the @var{bank} parameter is the bank number as obtained by the
3839 @code{flash banks} command.
3841 @deffn Command {lpc2900 signature} bank
3842 Calculates a 128-bit hash value, the @emph{signature}, from the whole flash
3843 content. This is a hardware feature of the flash block, hence the calculation is
3844 very fast. You may use this to verify the content of a programmed device against
3849 signature: 0x5f40cdc8:0xc64e592e:0x10490f89:0x32a0f317
3853 @deffn Command {lpc2900 read_custom} bank filename
3854 Reads the 912 bytes of customer information from the flash index sector, and
3855 saves it to a file in binary format.
3858 lpc2900 read_custom 0 /path_to/customer_info.bin
3862 The index sector of the flash is a @emph{write-only} sector. It cannot be
3863 erased! In order to guard against unintentional write access, all following
3864 commands need to be preceeded by a successful call to the @code{password}
3867 @deffn Command {lpc2900 password} bank password
3868 You need to use this command right before each of the following commands:
3869 @code{lpc2900 write_custom}, @code{lpc2900 secure_sector},
3870 @code{lpc2900 secure_jtag}.
3872 The password string is fixed to "I_know_what_I_am_doing".
3875 lpc2900 password 0 I_know_what_I_am_doing
3876 Potentially dangerous operation allowed in next command!
3880 @deffn Command {lpc2900 write_custom} bank filename type
3881 Writes the content of the file into the customer info space of the flash index
3882 sector. The filetype can be specified with the @var{type} field. Possible values
3883 for @var{type} are: @var{bin} (binary), @var{ihex} (Intel hex format),
3884 @var{elf} (ELF binary) or @var{s19} (Motorola S-records). The file must
3885 contain a single section, and the contained data length must be exactly
3887 @quotation Attention
3888 This cannot be reverted! Be careful!
3892 lpc2900 write_custom 0 /path_to/customer_info.bin bin
3896 @deffn Command {lpc2900 secure_sector} bank first last
3897 Secures the sector range from @var{first} to @var{last} (including) against
3898 further program and erase operations. The sector security will be effective
3899 after the next power cycle.
3900 @quotation Attention
3901 This cannot be reverted! Be careful!
3903 Secured sectors appear as @emph{protected} in the @code{flash info} command.
3906 lpc2900 secure_sector 0 1 1
3908 #0 : lpc2900 at 0x20000000, size 0x000c0000, (...)
3909 # 0: 0x00000000 (0x2000 8kB) not protected
3910 # 1: 0x00002000 (0x2000 8kB) protected
3911 # 2: 0x00004000 (0x2000 8kB) not protected
3915 @deffn Command {lpc2900 secure_jtag} bank
3916 Irreversibly disable the JTAG port. The new JTAG security setting will be
3917 effective after the next power cycle.
3918 @quotation Attention
3919 This cannot be reverted! Be careful!
3923 lpc2900 secure_jtag 0
3928 @deffn {Flash Driver} ocl
3929 @emph{No idea what this is, other than using some arm7/arm9 core.}
3932 flash bank ocl 0 0 0 0 $_TARGETNAME
3936 @deffn {Flash Driver} pic32mx
3937 The PIC32MX microcontrollers are based on the MIPS 4K cores,
3938 and integrate flash memory.
3939 @emph{The current implementation is incomplete.}
3942 flash bank pix32mx 0 0 0 0 $_TARGETNAME
3945 @comment numerous *disabled* commands are defined:
3946 @comment - chip_erase ... pointless given flash_erase_address
3947 @comment - lock, unlock ... pointless given protect on/off (yes?)
3948 @comment - pgm_word ... shouldn't bank be deduced from address??
3949 Some pic32mx-specific commands are defined:
3950 @deffn Command {pic32mx pgm_word} address value bank
3951 Programs the specified 32-bit @var{value} at the given @var{address}
3952 in the specified chip @var{bank}.
3956 @deffn {Flash Driver} stellaris
3957 All members of the Stellaris LM3Sxxx microcontroller family from
3959 include internal flash and use ARM Cortex M3 cores.
3960 The driver automatically recognizes a number of these chips using
3961 the chip identification register, and autoconfigures itself.
3962 @footnote{Currently there is a @command{stellaris mass_erase} command.
3963 That seems pointless since the same effect can be had using the
3964 standard @command{flash erase_address} command.}
3967 flash bank stellaris 0 0 0 0 $_TARGETNAME
3971 @deffn {Flash Driver} stm32x
3972 All members of the STM32 microcontroller family from ST Microelectronics
3973 include internal flash and use ARM Cortex M3 cores.
3974 The driver automatically recognizes a number of these chips using
3975 the chip identification register, and autoconfigures itself.
3978 flash bank stm32x 0 0 0 0 $_TARGETNAME
3981 Some stm32x-specific commands
3982 @footnote{Currently there is a @command{stm32x mass_erase} command.
3983 That seems pointless since the same effect can be had using the
3984 standard @command{flash erase_address} command.}
3987 @deffn Command {stm32x lock} num
3988 Locks the entire stm32 device.
3989 The @var{num} parameter is a value shown by @command{flash banks}.
3992 @deffn Command {stm32x unlock} num
3993 Unlocks the entire stm32 device.
3994 The @var{num} parameter is a value shown by @command{flash banks}.
3997 @deffn Command {stm32x options_read} num
3998 Read and display the stm32 option bytes written by
3999 the @command{stm32x options_write} command.
4000 The @var{num} parameter is a value shown by @command{flash banks}.
4003 @deffn Command {stm32x options_write} num (@option{SWWDG}|@option{HWWDG}) (@option{RSTSTNDBY}|@option{NORSTSTNDBY}) (@option{RSTSTOP}|@option{NORSTSTOP})
4004 Writes the stm32 option byte with the specified values.
4005 The @var{num} parameter is a value shown by @command{flash banks}.
4009 @deffn {Flash Driver} str7x
4010 All members of the STR7 microcontroller family from ST Microelectronics
4011 include internal flash and use ARM7TDMI cores.
4012 The @var{str7x} driver defines one mandatory parameter, @var{variant},
4013 which is either @code{STR71x}, @code{STR73x} or @code{STR75x}.
4016 flash bank str7x 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
4019 @deffn Command {str7x disable_jtag} bank
4020 Activate the Debug/Readout protection mechanism
4021 for the specified flash bank.
4025 @deffn {Flash Driver} str9x
4026 Most members of the STR9 microcontroller family from ST Microelectronics
4027 include internal flash and use ARM966E cores.
4028 The str9 needs the flash controller to be configured using
4029 the @command{str9x flash_config} command prior to Flash programming.
4032 flash bank str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
4033 str9x flash_config 0 4 2 0 0x80000
4036 @deffn Command {str9x flash_config} num bbsr nbbsr bbadr nbbadr
4037 Configures the str9 flash controller.
4038 The @var{num} parameter is a value shown by @command{flash banks}.
4041 @item @var{bbsr} - Boot Bank Size register
4042 @item @var{nbbsr} - Non Boot Bank Size register
4043 @item @var{bbadr} - Boot Bank Start Address register
4044 @item @var{nbbadr} - Boot Bank Start Address register
4050 @deffn {Flash Driver} tms470
4051 Most members of the TMS470 microcontroller family from Texas Instruments
4052 include internal flash and use ARM7TDMI cores.
4053 This driver doesn't require the chip and bus width to be specified.
4055 Some tms470-specific commands are defined:
4057 @deffn Command {tms470 flash_keyset} key0 key1 key2 key3
4058 Saves programming keys in a register, to enable flash erase and write commands.
4061 @deffn Command {tms470 osc_mhz} clock_mhz
4062 Reports the clock speed, which is used to calculate timings.
4065 @deffn Command {tms470 plldis} (0|1)
4066 Disables (@var{1}) or enables (@var{0}) use of the PLL to speed up
4071 @subsection str9xpec driver
4074 Here is some background info to help
4075 you better understand how this driver works. OpenOCD has two flash drivers for
4079 Standard driver @option{str9x} programmed via the str9 core. Normally used for
4080 flash programming as it is faster than the @option{str9xpec} driver.
4082 Direct programming @option{str9xpec} using the flash controller. This is an
4083 ISC compilant (IEEE 1532) tap connected in series with the str9 core. The str9
4084 core does not need to be running to program using this flash driver. Typical use
4085 for this driver is locking/unlocking the target and programming the option bytes.
4088 Before we run any commands using the @option{str9xpec} driver we must first disable
4089 the str9 core. This example assumes the @option{str9xpec} driver has been
4090 configured for flash bank 0.
4092 # assert srst, we do not want core running
4093 # while accessing str9xpec flash driver
4095 # turn off target polling
4098 str9xpec enable_turbo 0
4100 str9xpec options_read 0
4101 # re-enable str9 core
4102 str9xpec disable_turbo 0
4106 The above example will read the str9 option bytes.
4107 When performing a unlock remember that you will not be able to halt the str9 - it
4108 has been locked. Halting the core is not required for the @option{str9xpec} driver
4109 as mentioned above, just issue the commands above manually or from a telnet prompt.
4111 @deffn {Flash Driver} str9xpec
4112 Only use this driver for locking/unlocking the device or configuring the option bytes.
4113 Use the standard str9 driver for programming.
4114 Before using the flash commands the turbo mode must be enabled using the
4115 @command{str9xpec enable_turbo} command.
4117 Several str9xpec-specific commands are defined:
4119 @deffn Command {str9xpec disable_turbo} num
4120 Restore the str9 into JTAG chain.
4123 @deffn Command {str9xpec enable_turbo} num
4124 Enable turbo mode, will simply remove the str9 from the chain and talk
4125 directly to the embedded flash controller.
4128 @deffn Command {str9xpec lock} num
4129 Lock str9 device. The str9 will only respond to an unlock command that will
4133 @deffn Command {str9xpec part_id} num
4134 Prints the part identifier for bank @var{num}.
4137 @deffn Command {str9xpec options_cmap} num (@option{bank0}|@option{bank1})
4138 Configure str9 boot bank.
4141 @deffn Command {str9xpec options_lvdsel} num (@option{vdd}|@option{vdd_vddq})
4142 Configure str9 lvd source.
4145 @deffn Command {str9xpec options_lvdthd} num (@option{2.4v}|@option{2.7v})
4146 Configure str9 lvd threshold.
4149 @deffn Command {str9xpec options_lvdwarn} bank (@option{vdd}|@option{vdd_vddq})
4150 Configure str9 lvd reset warning source.
4153 @deffn Command {str9xpec options_read} num
4154 Read str9 option bytes.
4157 @deffn Command {str9xpec options_write} num
4158 Write str9 option bytes.
4161 @deffn Command {str9xpec unlock} num
4170 @subsection mFlash Configuration
4171 @cindex mFlash Configuration
4173 @deffn {Config Command} {mflash bank} soc base RST_pin target
4174 Configures a mflash for @var{soc} host bank at
4176 The pin number format depends on the host GPIO naming convention.
4177 Currently, the mflash driver supports s3c2440 and pxa270.
4179 Example for s3c2440 mflash where @var{RST pin} is GPIO B1:
4182 mflash bank s3c2440 0x10000000 1b 0
4185 Example for pxa270 mflash where @var{RST pin} is GPIO 43:
4188 mflash bank pxa270 0x08000000 43 0
4192 @subsection mFlash commands
4193 @cindex mFlash commands
4195 @deffn Command {mflash config pll} frequency
4196 Configure mflash PLL.
4197 The @var{frequency} is the mflash input frequency, in Hz.
4198 Issuing this command will erase mflash's whole internal nand and write new pll.
4199 After this command, mflash needs power-on-reset for normal operation.
4200 If pll was newly configured, storage and boot(optional) info also need to be update.
4203 @deffn Command {mflash config boot}
4204 Configure bootable option.
4205 If bootable option is set, mflash offer the first 8 sectors
4209 @deffn Command {mflash config storage}
4210 Configure storage information.
4211 For the normal storage operation, this information must be
4215 @deffn Command {mflash dump} num filename offset size
4216 Dump @var{size} bytes, starting at @var{offset} bytes from the
4217 beginning of the bank @var{num}, to the file named @var{filename}.
4220 @deffn Command {mflash probe}
4224 @deffn Command {mflash write} num filename offset
4225 Write the binary file @var{filename} to mflash bank @var{num}, starting at
4226 @var{offset} bytes from the beginning of the bank.
4229 @node NAND Flash Commands
4230 @chapter NAND Flash Commands
4233 Compared to NOR or SPI flash, NAND devices are inexpensive
4234 and high density. Today's NAND chips, and multi-chip modules,
4235 commonly hold multiple GigaBytes of data.
4237 NAND chips consist of a number of ``erase blocks'' of a given
4238 size (such as 128 KBytes), each of which is divided into a
4239 number of pages (of perhaps 512 or 2048 bytes each). Each
4240 page of a NAND flash has an ``out of band'' (OOB) area to hold
4241 Error Correcting Code (ECC) and other metadata, usually 16 bytes
4242 of OOB for every 512 bytes of page data.
4244 One key characteristic of NAND flash is that its error rate
4245 is higher than that of NOR flash. In normal operation, that
4246 ECC is used to correct and detect errors. However, NAND
4247 blocks can also wear out and become unusable; those blocks
4248 are then marked "bad". NAND chips are even shipped from the
4249 manufacturer with a few bad blocks. The highest density chips
4250 use a technology (MLC) that wears out more quickly, so ECC
4251 support is increasingly important as a way to detect blocks
4252 that have begun to fail, and help to preserve data integrity
4253 with techniques such as wear leveling.
4255 Software is used to manage the ECC. Some controllers don't
4256 support ECC directly; in those cases, software ECC is used.
4257 Other controllers speed up the ECC calculations with hardware.
4258 Single-bit error correction hardware is routine. Controllers
4259 geared for newer MLC chips may correct 4 or more errors for
4260 every 512 bytes of data.
4262 You will need to make sure that any data you write using
4263 OpenOCD includes the apppropriate kind of ECC. For example,
4264 that may mean passing the @code{oob_softecc} flag when
4265 writing NAND data, or ensuring that the correct hardware
4268 The basic steps for using NAND devices include:
4270 @item Declare via the command @command{nand device}
4271 @* Do this in a board-specific configuration file,
4272 passing parameters as needed by the controller.
4273 @item Configure each device using @command{nand probe}.
4274 @* Do this only after the associated target is set up,
4275 such as in its reset-init script or in procures defined
4276 to access that device.
4277 @item Operate on the flash via @command{nand subcommand}
4278 @* Often commands to manipulate the flash are typed by a human, or run
4279 via a script in some automated way. Common task include writing a
4280 boot loader, operating system, or other data needed to initialize or
4284 @b{NOTE:} At the time this text was written, the largest NAND
4285 flash fully supported by OpenOCD is 2 GiBytes (16 GiBits).
4286 This is because the variables used to hold offsets and lengths
4287 are only 32 bits wide.
4288 (Larger chips may work in some cases, unless an offset or length
4289 is larger than 0xffffffff, the largest 32-bit unsigned integer.)
4290 Some larger devices will work, since they are actually multi-chip
4291 modules with two smaller chips and individual chipselect lines.
4293 @anchor{NAND Configuration}
4294 @section NAND Configuration Commands
4295 @cindex NAND configuration
4297 NAND chips must be declared in configuration scripts,
4298 plus some additional configuration that's done after
4299 OpenOCD has initialized.
4301 @deffn {Config Command} {nand device} controller target [configparams...]
4302 Declares a NAND device, which can be read and written to
4303 after it has been configured through @command{nand probe}.
4304 In OpenOCD, devices are single chips; this is unlike some
4305 operating systems, which may manage multiple chips as if
4306 they were a single (larger) device.
4307 In some cases, configuring a device will activate extra
4308 commands; see the controller-specific documentation.
4310 @b{NOTE:} This command is not available after OpenOCD
4311 initialization has completed. Use it in board specific
4312 configuration files, not interactively.
4315 @item @var{controller} ... identifies the controller driver
4316 associated with the NAND device being declared.
4317 @xref{NAND Driver List}.
4318 @item @var{target} ... names the target used when issuing
4319 commands to the NAND controller.
4320 @comment Actually, it's currently a controller-specific parameter...
4321 @item @var{configparams} ... controllers may support, or require,
4322 additional parameters. See the controller-specific documentation
4323 for more information.
4327 @deffn Command {nand list}
4328 Prints a summary of each device declared
4329 using @command{nand device}, numbered from zero.
4330 Note that un-probed devices show no details.
4333 #0: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
4334 blocksize: 131072, blocks: 8192
4335 #1: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
4336 blocksize: 131072, blocks: 8192
4341 @deffn Command {nand probe} num
4342 Probes the specified device to determine key characteristics
4343 like its page and block sizes, and how many blocks it has.
4344 The @var{num} parameter is the value shown by @command{nand list}.
4345 You must (successfully) probe a device before you can use
4346 it with most other NAND commands.
4349 @section Erasing, Reading, Writing to NAND Flash
4351 @deffn Command {nand dump} num filename offset length [oob_option]
4352 @cindex NAND reading
4353 Reads binary data from the NAND device and writes it to the file,
4354 starting at the specified offset.
4355 The @var{num} parameter is the value shown by @command{nand list}.
4357 Use a complete path name for @var{filename}, so you don't depend
4358 on the directory used to start the OpenOCD server.
4360 The @var{offset} and @var{length} must be exact multiples of the
4361 device's page size. They describe a data region; the OOB data
4362 associated with each such page may also be accessed.
4364 @b{NOTE:} At the time this text was written, no error correction
4365 was done on the data that's read, unless raw access was disabled
4366 and the underlying NAND controller driver had a @code{read_page}
4367 method which handled that error correction.
4369 By default, only page data is saved to the specified file.
4370 Use an @var{oob_option} parameter to save OOB data:
4372 @item no oob_* parameter
4373 @*Output file holds only page data; OOB is discarded.
4374 @item @code{oob_raw}
4375 @*Output file interleaves page data and OOB data;
4376 the file will be longer than "length" by the size of the
4377 spare areas associated with each data page.
4378 Note that this kind of "raw" access is different from
4379 what's implied by @command{nand raw_access}, which just
4380 controls whether a hardware-aware access method is used.
4381 @item @code{oob_only}
4382 @*Output file has only raw OOB data, and will
4383 be smaller than "length" since it will contain only the
4384 spare areas associated with each data page.
4388 @deffn Command {nand erase} num [offset length]
4389 @cindex NAND erasing
4390 @cindex NAND programming
4391 Erases blocks on the specified NAND device, starting at the
4392 specified @var{offset} and continuing for @var{length} bytes.
4393 Both of those values must be exact multiples of the device's
4394 block size, and the region they specify must fit entirely in the chip.
4395 If those parameters are not specified,
4396 the whole NAND chip will be erased.
4397 The @var{num} parameter is the value shown by @command{nand list}.
4399 @b{NOTE:} This command will try to erase bad blocks, when told
4400 to do so, which will probably invalidate the manufacturer's bad
4402 For the remainder of the current server session, @command{nand info}
4403 will still report that the block ``is'' bad.
4406 @deffn Command {nand write} num filename offset [option...]
4407 @cindex NAND writing
4408 @cindex NAND programming
4409 Writes binary data from the file into the specified NAND device,
4410 starting at the specified offset. Those pages should already
4411 have been erased; you can't change zero bits to one bits.
4412 The @var{num} parameter is the value shown by @command{nand list}.
4414 Use a complete path name for @var{filename}, so you don't depend
4415 on the directory used to start the OpenOCD server.
4417 The @var{offset} must be an exact multiple of the device's page size.
4418 All data in the file will be written, assuming it doesn't run
4419 past the end of the device.
4420 Only full pages are written, and any extra space in the last
4421 page will be filled with 0xff bytes. (That includes OOB data,
4422 if that's being written.)
4424 @b{NOTE:} At the time this text was written, bad blocks are
4425 ignored. That is, this routine will not skip bad blocks,
4426 but will instead try to write them. This can cause problems.
4428 Provide at most one @var{option} parameter. With some
4429 NAND drivers, the meanings of these parameters may change
4430 if @command{nand raw_access} was used to disable hardware ECC.
4432 @item no oob_* parameter
4433 @*File has only page data, which is written.
4434 If raw acccess is in use, the OOB area will not be written.
4435 Otherwise, if the underlying NAND controller driver has
4436 a @code{write_page} routine, that routine may write the OOB
4437 with hardware-computed ECC data.
4438 @item @code{oob_only}
4439 @*File has only raw OOB data, which is written to the OOB area.
4440 Each page's data area stays untouched. @i{This can be a dangerous
4441 option}, since it can invalidate the ECC data.
4442 You may need to force raw access to use this mode.
4443 @item @code{oob_raw}
4444 @*File interleaves data and OOB data, both of which are written
4445 If raw access is enabled, the data is written first, then the
4447 Otherwise, if the underlying NAND controller driver has
4448 a @code{write_page} routine, that routine may modify the OOB
4449 before it's written, to include hardware-computed ECC data.
4450 @item @code{oob_softecc}
4451 @*File has only page data, which is written.
4452 The OOB area is filled with 0xff, except for a standard 1-bit
4453 software ECC code stored in conventional locations.
4454 You might need to force raw access to use this mode, to prevent
4455 the underlying driver from applying hardware ECC.
4456 @item @code{oob_softecc_kw}
4457 @*File has only page data, which is written.
4458 The OOB area is filled with 0xff, except for a 4-bit software ECC
4459 specific to the boot ROM in Marvell Kirkwood SoCs.
4460 You might need to force raw access to use this mode, to prevent
4461 the underlying driver from applying hardware ECC.
4465 @section Other NAND commands
4466 @cindex NAND other commands
4468 @deffn Command {nand check_bad_blocks} [offset length]
4469 Checks for manufacturer bad block markers on the specified NAND
4470 device. If no parameters are provided, checks the whole
4471 device; otherwise, starts at the specified @var{offset} and
4472 continues for @var{length} bytes.
4473 Both of those values must be exact multiples of the device's
4474 block size, and the region they specify must fit entirely in the chip.
4475 The @var{num} parameter is the value shown by @command{nand list}.
4477 @b{NOTE:} Before using this command you should force raw access
4478 with @command{nand raw_access enable} to ensure that the underlying
4479 driver will not try to apply hardware ECC.
4482 @deffn Command {nand info} num
4483 The @var{num} parameter is the value shown by @command{nand list}.
4484 This prints the one-line summary from "nand list", plus for
4485 devices which have been probed this also prints any known
4486 status for each block.
4489 @deffn Command {nand raw_access} num (@option{enable}|@option{disable})
4490 Sets or clears an flag affecting how page I/O is done.
4491 The @var{num} parameter is the value shown by @command{nand list}.
4493 This flag is cleared (disabled) by default, but changing that
4494 value won't affect all NAND devices. The key factor is whether
4495 the underlying driver provides @code{read_page} or @code{write_page}
4496 methods. If it doesn't provide those methods, the setting of
4497 this flag is irrelevant; all access is effectively ``raw''.
4499 When those methods exist, they are normally used when reading
4500 data (@command{nand dump} or reading bad block markers) or
4501 writing it (@command{nand write}). However, enabling
4502 raw access (setting the flag) prevents use of those methods,
4503 bypassing hardware ECC logic.
4504 @i{This can be a dangerous option}, since writing blocks
4505 with the wrong ECC data can cause them to be marked as bad.
4508 @anchor{NAND Driver List}
4509 @section NAND Drivers, Options, and Commands
4510 As noted above, the @command{nand device} command allows
4511 driver-specific options and behaviors.
4512 Some controllers also activate controller-specific commands.
4514 @deffn {NAND Driver} davinci
4515 This driver handles the NAND controllers found on DaVinci family
4516 chips from Texas Instruments.
4517 It takes three extra parameters:
4518 address of the NAND chip;
4519 hardware ECC mode to use (@option{hwecc1},
4520 @option{hwecc4}, @option{hwecc4_infix});
4521 address of the AEMIF controller on this processor.
4523 nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000
4525 All DaVinci processors support the single-bit ECC hardware,
4526 and newer ones also support the four-bit ECC hardware.
4527 The @code{write_page} and @code{read_page} methods are used
4528 to implement those ECC modes, unless they are disabled using
4529 the @command{nand raw_access} command.
4532 @deffn {NAND Driver} lpc3180
4533 These controllers require an extra @command{nand device}
4534 parameter: the clock rate used by the controller.
4535 @deffn Command {lpc3180 select} num [mlc|slc]
4536 Configures use of the MLC or SLC controller mode.
4537 MLC implies use of hardware ECC.
4538 The @var{num} parameter is the value shown by @command{nand list}.
4541 At this writing, this driver includes @code{write_page}
4542 and @code{read_page} methods. Using @command{nand raw_access}
4543 to disable those methods will prevent use of hardware ECC
4544 in the MLC controller mode, but won't change SLC behavior.
4546 @comment current lpc3180 code won't issue 5-byte address cycles
4548 @deffn {NAND Driver} orion
4549 These controllers require an extra @command{nand device}
4550 parameter: the address of the controller.
4552 nand device orion 0xd8000000
4554 These controllers don't define any specialized commands.
4555 At this writing, their drivers don't include @code{write_page}
4556 or @code{read_page} methods, so @command{nand raw_access} won't
4557 change any behavior.
4560 @deffn {NAND Driver} s3c2410
4561 @deffnx {NAND Driver} s3c2412
4562 @deffnx {NAND Driver} s3c2440
4563 @deffnx {NAND Driver} s3c2443
4564 These S3C24xx family controllers don't have any special
4565 @command{nand device} options, and don't define any
4566 specialized commands.
4567 At this writing, their drivers don't include @code{write_page}
4568 or @code{read_page} methods, so @command{nand raw_access} won't
4569 change any behavior.
4572 @node PLD/FPGA Commands
4573 @chapter PLD/FPGA Commands
4577 Programmable Logic Devices (PLDs) and the more flexible
4578 Field Programmable Gate Arrays (FPGAs) are both types of programmable hardware.
4579 OpenOCD can support programming them.
4580 Although PLDs are generally restrictive (cells are less functional, and
4581 there are no special purpose cells for memory or computational tasks),
4582 they share the same OpenOCD infrastructure.
4583 Accordingly, both are called PLDs here.
4585 @section PLD/FPGA Configuration and Commands
4587 As it does for JTAG TAPs, debug targets, and flash chips (both NOR and NAND),
4588 OpenOCD maintains a list of PLDs available for use in various commands.
4589 Also, each such PLD requires a driver.
4591 They are referenced by the number shown by the @command{pld devices} command,
4592 and new PLDs are defined by @command{pld device driver_name}.
4594 @deffn {Config Command} {pld device} driver_name tap_name [driver_options]
4595 Defines a new PLD device, supported by driver @var{driver_name},
4596 using the TAP named @var{tap_name}.
4597 The driver may make use of any @var{driver_options} to configure its
4601 @deffn {Command} {pld devices}
4602 Lists the PLDs and their numbers.
4605 @deffn {Command} {pld load} num filename
4606 Loads the file @file{filename} into the PLD identified by @var{num}.
4607 The file format must be inferred by the driver.
4610 @section PLD/FPGA Drivers, Options, and Commands
4612 Drivers may support PLD-specific options to the @command{pld device}
4613 definition command, and may also define commands usable only with
4614 that particular type of PLD.
4616 @deffn {FPGA Driver} virtex2
4617 Virtex-II is a family of FPGAs sold by Xilinx.
4618 It supports the IEEE 1532 standard for In-System Configuration (ISC).
4619 No driver-specific PLD definition options are used,
4620 and one driver-specific command is defined.
4622 @deffn {Command} {virtex2 read_stat} num
4623 Reads and displays the Virtex-II status register (STAT)
4628 @node General Commands
4629 @chapter General Commands
4632 The commands documented in this chapter here are common commands that
4633 you, as a human, may want to type and see the output of. Configuration type
4634 commands are documented elsewhere.
4638 @item @b{Source Of Commands}
4639 @* OpenOCD commands can occur in a configuration script (discussed
4640 elsewhere) or typed manually by a human or supplied programatically,
4641 or via one of several TCP/IP Ports.
4643 @item @b{From the human}
4644 @* A human should interact with the telnet interface (default port: 4444)
4645 or via GDB (default port 3333).
4647 To issue commands from within a GDB session, use the @option{monitor}
4648 command, e.g. use @option{monitor poll} to issue the @option{poll}
4649 command. All output is relayed through the GDB session.
4651 @item @b{Machine Interface}
4652 The Tcl interface's intent is to be a machine interface. The default Tcl
4657 @section Daemon Commands
4659 @deffn {Command} exit
4660 Exits the current telnet session.
4663 @c note EXTREMELY ANNOYING word wrap at column 75
4664 @c even when lines are e.g. 100+ columns ...
4665 @c coded in startup.tcl
4666 @deffn {Command} help [string]
4667 With no parameters, prints help text for all commands.
4668 Otherwise, prints each helptext containing @var{string}.
4669 Not every command provides helptext.
4672 @deffn Command sleep msec [@option{busy}]
4673 Wait for at least @var{msec} milliseconds before resuming.
4674 If @option{busy} is passed, busy-wait instead of sleeping.
4675 (This option is strongly discouraged.)
4676 Useful in connection with script files
4677 (@command{script} command and @command{target_name} configuration).
4680 @deffn Command shutdown
4681 Close the OpenOCD daemon, disconnecting all clients (GDB, telnet, other).
4684 @anchor{debug_level}
4685 @deffn Command debug_level [n]
4686 @cindex message level
4687 Display debug level.
4688 If @var{n} (from 0..3) is provided, then set it to that level.
4689 This affects the kind of messages sent to the server log.
4690 Level 0 is error messages only;
4691 level 1 adds warnings;
4692 level 2 adds informational messages;
4693 and level 3 adds debugging messages.
4694 The default is level 2, but that can be overridden on
4695 the command line along with the location of that log
4696 file (which is normally the server's standard output).
4700 @deffn Command fast (@option{enable}|@option{disable})
4702 Set default behaviour of OpenOCD to be "fast and dangerous".
4704 At this writing, this only affects the defaults for two ARM7/ARM9 parameters:
4705 fast memory access, and DCC downloads. Those parameters may still be
4706 individually overridden.
4708 The target specific "dangerous" optimisation tweaking options may come and go
4709 as more robust and user friendly ways are found to ensure maximum throughput
4710 and robustness with a minimum of configuration.
4712 Typically the "fast enable" is specified first on the command line:
4715 openocd -c "fast enable" -c "interface dummy" -f target/str710.cfg
4719 @deffn Command echo message
4720 Logs a message at "user" priority.
4721 Output @var{message} to stdout.
4723 echo "Downloading kernel -- please wait"
4727 @deffn Command log_output [filename]
4728 Redirect logging to @var{filename};
4729 the initial log output channel is stderr.
4732 @anchor{Target State handling}
4733 @section Target State handling
4736 @cindex target initialization
4738 In this section ``target'' refers to a CPU configured as
4739 shown earlier (@pxref{CPU Configuration}).
4740 These commands, like many, implicitly refer to
4741 a current target which is used to perform the
4742 various operations. The current target may be changed
4743 by using @command{targets} command with the name of the
4744 target which should become current.
4746 @deffn Command reg [(number|name) [value]]
4747 Access a single register by @var{number} or by its @var{name}.
4749 @emph{With no arguments}:
4750 list all available registers for the current target,
4751 showing number, name, size, value, and cache status.
4753 @emph{With number/name}: display that register's value.
4755 @emph{With both number/name and value}: set register's value.
4757 Cores may have surprisingly many registers in their
4758 Debug and trace infrastructure:
4762 (0) r0 (/32): 0x0000D3C2 (dirty: 1, valid: 1)
4763 (1) r1 (/32): 0xFD61F31C (dirty: 0, valid: 1)
4764 (2) r2 (/32): 0x00022551 (dirty: 0, valid: 1)
4766 (164) ETM_CONTEXTID_COMPARATOR_MASK (/32): \
4767 0x00000000 (dirty: 0, valid: 0)
4772 @deffn Command halt [ms]
4773 @deffnx Command wait_halt [ms]
4774 The @command{halt} command first sends a halt request to the target,
4775 which @command{wait_halt} doesn't.
4776 Otherwise these behave the same: wait up to @var{ms} milliseconds,
4777 or 5 seconds if there is no parameter, for the target to halt
4778 (and enter debug mode).
4779 Using 0 as the @var{ms} parameter prevents OpenOCD from waiting.
4782 On ARM cores, software using the @emph{wait for interrupt} operation
4783 often blocks the JTAG access needed by a @command{halt} command.
4784 This is because that operation also puts the core into a low
4785 power mode by gating the core clock;
4786 but the core clock is needed to detect JTAG clock transitions.
4788 One partial workaround uses adaptive clocking: when the core is
4789 interrupted the operation completes, then JTAG clocks are accepted
4790 at least until the interrupt handler completes.
4791 However, this workaround is often unusable since the processor, board,
4792 and JTAG adapter must all support adaptive JTAG clocking.
4793 Also, it can't work until an interrupt is issued.
4795 A more complete workaround is to not use that operation while you
4796 work with a JTAG debugger.
4797 Tasking environments generaly have idle loops where the body is the
4798 @emph{wait for interrupt} operation.
4799 (On older cores, it is a coprocessor action;
4800 newer cores have a @option{wfi} instruction.)
4801 Such loops can just remove that operation, at the cost of higher
4802 power consumption (because the CPU is needlessly clocked).
4807 @deffn Command resume [address]
4808 Resume the target at its current code position,
4809 or the optional @var{address} if it is provided.
4810 OpenOCD will wait 5 seconds for the target to resume.
4813 @deffn Command step [address]
4814 Single-step the target at its current code position,
4815 or the optional @var{address} if it is provided.
4818 @anchor{Reset Command}
4819 @deffn Command reset
4820 @deffnx Command {reset run}
4821 @deffnx Command {reset halt}
4822 @deffnx Command {reset init}
4823 Perform as hard a reset as possible, using SRST if possible.
4824 @emph{All defined targets will be reset, and target
4825 events will fire during the reset sequence.}
4827 The optional parameter specifies what should
4828 happen after the reset.
4829 If there is no parameter, a @command{reset run} is executed.
4830 The other options will not work on all systems.
4831 @xref{Reset Configuration}.
4834 @item @b{run} Let the target run
4835 @item @b{halt} Immediately halt the target
4836 @item @b{init} Immediately halt the target, and execute the reset-init script
4840 @deffn Command soft_reset_halt
4841 Requesting target halt and executing a soft reset. This is often used
4842 when a target cannot be reset and halted. The target, after reset is
4843 released begins to execute code. OpenOCD attempts to stop the CPU and
4844 then sets the program counter back to the reset vector. Unfortunately
4845 the code that was executed may have left the hardware in an unknown
4849 @section I/O Utilities
4851 These commands are available when
4852 OpenOCD is built with @option{--enable-ioutil}.
4853 They are mainly useful on embedded targets,
4855 Hosts with operating systems have complementary tools.
4857 @emph{Note:} there are several more such commands.
4859 @deffn Command append_file filename [string]*
4860 Appends the @var{string} parameters to
4861 the text file @file{filename}.
4862 Each string except the last one is followed by one space.
4863 The last string is followed by a newline.
4866 @deffn Command cat filename
4867 Reads and displays the text file @file{filename}.
4870 @deffn Command cp src_filename dest_filename
4871 Copies contents from the file @file{src_filename}
4872 into @file{dest_filename}.
4876 @emph{No description provided.}
4880 @emph{No description provided.}
4884 @emph{No description provided.}
4887 @deffn Command meminfo
4888 Display available RAM memory on OpenOCD host.
4889 Used in OpenOCD regression testing scripts.
4893 @emph{No description provided.}
4897 @emph{No description provided.}
4900 @deffn Command rm filename
4901 @c "rm" has both normal and Jim-level versions??
4902 Unlinks the file @file{filename}.
4905 @deffn Command trunc filename
4906 Removes all data in the file @file{filename}.
4909 @anchor{Memory access}
4910 @section Memory access commands
4911 @cindex memory access
4913 These commands allow accesses of a specific size to the memory
4914 system. Often these are used to configure the current target in some
4915 special way. For example - one may need to write certain values to the
4916 SDRAM controller to enable SDRAM.
4919 @item Use the @command{targets} (plural) command
4920 to change the current target.
4921 @item In system level scripts these commands are deprecated.
4922 Please use their TARGET object siblings to avoid making assumptions
4923 about what TAP is the current target, or about MMU configuration.
4926 @deffn Command mdw addr [count]
4927 @deffnx Command mdh addr [count]
4928 @deffnx Command mdb addr [count]
4929 Display contents of address @var{addr}, as
4930 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
4931 or 8-bit bytes (@command{mdb}).
4932 If @var{count} is specified, displays that many units.
4933 (If you want to manipulate the data instead of displaying it,
4934 see the @code{mem2array} primitives.)
4937 @deffn Command mww addr word
4938 @deffnx Command mwh addr halfword
4939 @deffnx Command mwb addr byte
4940 Writes the specified @var{word} (32 bits),
4941 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4942 at the specified address @var{addr}.
4946 @anchor{Image access}
4947 @section Image loading commands
4948 @cindex image loading
4949 @cindex image dumping
4952 @deffn Command {dump_image} filename address size
4953 Dump @var{size} bytes of target memory starting at @var{address} to the
4954 binary file named @var{filename}.
4957 @deffn Command {fast_load}
4958 Loads an image stored in memory by @command{fast_load_image} to the
4959 current target. Must be preceeded by fast_load_image.
4962 @deffn Command {fast_load_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
4963 Normally you should be using @command{load_image} or GDB load. However, for
4964 testing purposes or when I/O overhead is significant(OpenOCD running on an embedded
4965 host), storing the image in memory and uploading the image to the target
4966 can be a way to upload e.g. multiple debug sessions when the binary does not change.
4967 Arguments are the same as @command{load_image}, but the image is stored in OpenOCD host
4968 memory, i.e. does not affect target. This approach is also useful when profiling
4969 target programming performance as I/O and target programming can easily be profiled
4974 @deffn Command {load_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
4975 Load image from file @var{filename} to target memory at @var{address}.
4976 The file format may optionally be specified
4977 (@option{bin}, @option{ihex}, or @option{elf})
4980 @deffn Command {test_image} filename [address [@option{bin}|@option{ihex}|@option{elf}]]
4981 Displays image section sizes and addresses
4982 as if @var{filename} were loaded into target memory
4983 starting at @var{address} (defaults to zero).
4984 The file format may optionally be specified
4985 (@option{bin}, @option{ihex}, or @option{elf})
4988 @deffn Command {verify_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
4989 Verify @var{filename} against target memory starting at @var{address}.
4990 The file format may optionally be specified
4991 (@option{bin}, @option{ihex}, or @option{elf})
4992 This will first attempt a comparison using a CRC checksum, if this fails it will try a binary compare.
4996 @section Breakpoint and Watchpoint commands
5000 CPUs often make debug modules accessible through JTAG, with
5001 hardware support for a handful of code breakpoints and data
5003 In addition, CPUs almost always support software breakpoints.
5005 @deffn Command {bp} [address len [@option{hw}]]
5006 With no parameters, lists all active breakpoints.
5007 Else sets a breakpoint on code execution starting
5008 at @var{address} for @var{length} bytes.
5009 This is a software breakpoint, unless @option{hw} is specified
5010 in which case it will be a hardware breakpoint.
5012 (@xref{arm9tdmi vector_catch}, or @pxref{xscale vector_catch},
5013 for similar mechanisms that do not consume hardware breakpoints.)
5016 @deffn Command {rbp} address
5017 Remove the breakpoint at @var{address}.
5020 @deffn Command {rwp} address
5021 Remove data watchpoint on @var{address}
5024 @deffn Command {wp} [address len [(@option{r}|@option{w}|@option{a}) [value [mask]]]]
5025 With no parameters, lists all active watchpoints.
5026 Else sets a data watchpoint on data from @var{address} for @var{length} bytes.
5027 The watch point is an "access" watchpoint unless
5028 the @option{r} or @option{w} parameter is provided,
5029 defining it as respectively a read or write watchpoint.
5030 If a @var{value} is provided, that value is used when determining if
5031 the watchpoint should trigger. The value may be first be masked
5032 using @var{mask} to mark ``don't care'' fields.
5035 @section Misc Commands
5038 @deffn Command {profile} seconds filename
5039 Profiling samples the CPU's program counter as quickly as possible,
5040 which is useful for non-intrusive stochastic profiling.
5041 Saves up to 10000 sampines in @file{filename} using ``gmon.out'' format.
5044 @deffn Command {version}
5045 Displays a string identifying the version of this OpenOCD server.
5048 @deffn Command {virt2phys} virtual_address
5049 Requests the current target to map the specified @var{virtual_address}
5050 to its corresponding physical address, and displays the result.
5053 @node Architecture and Core Commands
5054 @chapter Architecture and Core Commands
5055 @cindex Architecture Specific Commands
5056 @cindex Core Specific Commands
5058 Most CPUs have specialized JTAG operations to support debugging.
5059 OpenOCD packages most such operations in its standard command framework.
5060 Some of those operations don't fit well in that framework, so they are
5061 exposed here as architecture or implementation (core) specific commands.
5063 @anchor{ARM Hardware Tracing}
5064 @section ARM Hardware Tracing
5069 CPUs based on ARM cores may include standard tracing interfaces,
5070 based on an ``Embedded Trace Module'' (ETM) which sends voluminous
5071 address and data bus trace records to a ``Trace Port''.
5075 Development-oriented boards will sometimes provide a high speed
5076 trace connector for collecting that data, when the particular CPU
5077 supports such an interface.
5078 (The standard connector is a 38-pin Mictor, with both JTAG
5079 and trace port support.)
5080 Those trace connectors are supported by higher end JTAG adapters
5081 and some logic analyzer modules; frequently those modules can
5082 buffer several megabytes of trace data.
5083 Configuring an ETM coupled to such an external trace port belongs
5084 in the board-specific configuration file.
5086 If the CPU doesn't provide an external interface, it probably
5087 has an ``Embedded Trace Buffer'' (ETB) on the chip, which is a
5088 dedicated SRAM. 4KBytes is one common ETB size.
5089 Configuring an ETM coupled only to an ETB belongs in the CPU-specific
5090 (target) configuration file, since it works the same on all boards.
5093 ETM support in OpenOCD doesn't seem to be widely used yet.
5096 ETM support may be buggy, and at least some @command{etm config}
5097 parameters should be detected by asking the ETM for them.
5098 It seems like a GDB hookup should be possible,
5099 as well as triggering trace on specific events
5100 (perhaps @emph{handling IRQ 23} or @emph{calls foo()}).
5101 There should be GUI tools to manipulate saved trace data and help
5102 analyse it in conjunction with the source code.
5103 It's unclear how much of a common interface is shared
5104 with the current XScale trace support, or should be
5105 shared with eventual Nexus-style trace module support.
5106 At this writing (September 2009) only ARM7 and ARM9 support
5107 for ETM modules is available. The code should be able to
5108 work with some newer cores; but not all of them support
5109 this original style of JTAG access.
5112 @subsection ETM Configuration
5113 ETM setup is coupled with the trace port driver configuration.
5115 @deffn {Config Command} {etm config} target width mode clocking driver
5116 Declares the ETM associated with @var{target}, and associates it
5117 with a given trace port @var{driver}. @xref{Trace Port Drivers}.
5119 Several of the parameters must reflect the trace port configuration.
5120 The @var{width} must be either 4, 8, or 16.
5121 The @var{mode} must be @option{normal}, @option{multiplexted},
5122 or @option{demultiplexted}.
5123 The @var{clocking} must be @option{half} or @option{full}.
5126 You can see the ETM registers using the @command{reg} command.
5127 Not all possible registers are present in every ETM.
5128 Most of the registers are write-only, and are used to configure
5129 what CPU activities are traced.
5133 @deffn Command {etm info}
5134 Displays information about the current target's ETM.
5137 @deffn Command {etm status}
5138 Displays status of the current target's ETM and trace port driver:
5139 is the ETM idle, or is it collecting data?
5140 Did trace data overflow?
5144 @deffn Command {etm tracemode} [type context_id_bits cycle_accurate branch_output]
5145 Displays what data that ETM will collect.
5146 If arguments are provided, first configures that data.
5147 When the configuration changes, tracing is stopped
5148 and any buffered trace data is invalidated.
5151 @item @var{type} ... describing how data accesses are traced,
5152 when they pass any ViewData filtering that that was set up.
5154 @option{none} (save nothing),
5155 @option{data} (save data),
5156 @option{address} (save addresses),
5157 @option{all} (save data and addresses)
5158 @item @var{context_id_bits} ... 0, 8, 16, or 32
5159 @item @var{cycle_accurate} ... @option{enable} or @option{disable}
5160 cycle-accurate instruction tracing.
5161 Before ETMv3, enabling this causes much extra data to be recorded.
5162 @item @var{branch_output} ... @option{enable} or @option{disable}.
5163 Disable this unless you need to try reconstructing the instruction
5164 trace stream without an image of the code.
5168 @deffn Command {etm trigger_percent} [percent]
5169 This displays, or optionally changes, the trace port driver's
5170 behavior after the ETM's configured @emph{trigger} event fires.
5171 It controls how much more trace data is saved after the (single)
5172 trace trigger becomes active.
5175 @item The default corresponds to @emph{trace around} usage,
5176 recording 50 percent data before the event and the rest
5178 @item The minimum value of @var{percent} is 2 percent,
5179 recording almost exclusively data before the trigger.
5180 Such extreme @emph{trace before} usage can help figure out
5181 what caused that event to happen.
5182 @item The maximum value of @var{percent} is 100 percent,
5183 recording data almost exclusively after the event.
5184 This extreme @emph{trace after} usage might help sort out
5185 how the event caused trouble.
5187 @c REVISIT allow "break" too -- enter debug mode.
5190 @subsection ETM Trace Operation
5192 After setting up the ETM, you can use it to collect data.
5193 That data can be exported to files for later analysis.
5194 It can also be parsed with OpenOCD, for basic sanity checking.
5196 To configure what is being traced, you will need to write
5197 various trace registers using @command{reg ETM_*} commands.
5198 For the definitions of these registers, read ARM publication
5199 @emph{IHI 0014, ``Embedded Trace Macrocell, Architecture Specification''}.
5200 Be aware that most of the relevant registers are write-only,
5201 and that ETM resources are limited. There are only a handful
5202 of address comparators, data comparators, counters, and so on.
5204 Examples of scenarios you might arrange to trace include:
5207 @item Code flow within a function, @emph{excluding} subroutines
5208 it calls. Use address range comparators to enable tracing
5209 for instruction access within that function's body.
5210 @item Code flow within a function, @emph{including} subroutines
5211 it calls. Use the sequencer and address comparators to activate
5212 tracing on an ``entered function'' state, then deactivate it by
5213 exiting that state when the function's exit code is invoked.
5214 @item Code flow starting at the fifth invocation of a function,
5215 combining one of the above models with a counter.
5216 @item CPU data accesses to the registers for a particular device,
5217 using address range comparators and the ViewData logic.
5218 @item Such data accesses only during IRQ handling, combining the above
5219 model with sequencer triggers which on entry and exit to the IRQ handler.
5220 @item @emph{... more}
5223 At this writing, September 2009, there are no Tcl utility
5224 procedures to help set up any common tracing scenarios.
5226 @deffn Command {etm analyze}
5227 Reads trace data into memory, if it wasn't already present.
5228 Decodes and prints the data that was collected.
5231 @deffn Command {etm dump} filename
5232 Stores the captured trace data in @file{filename}.
5235 @deffn Command {etm image} filename [base_address] [type]
5236 Opens an image file.
5239 @deffn Command {etm load} filename
5240 Loads captured trace data from @file{filename}.
5243 @deffn Command {etm start}
5244 Starts trace data collection.
5247 @deffn Command {etm stop}
5248 Stops trace data collection.
5251 @anchor{Trace Port Drivers}
5252 @subsection Trace Port Drivers
5254 To use an ETM trace port it must be associated with a driver.
5256 @deffn {Trace Port Driver} dummy
5257 Use the @option{dummy} driver if you are configuring an ETM that's
5258 not connected to anything (on-chip ETB or off-chip trace connector).
5259 @emph{This driver lets OpenOCD talk to the ETM, but it does not expose
5260 any trace data collection.}
5261 @deffn {Config Command} {etm_dummy config} target
5262 Associates the ETM for @var{target} with a dummy driver.
5266 @deffn {Trace Port Driver} etb
5267 Use the @option{etb} driver if you are configuring an ETM
5268 to use on-chip ETB memory.
5269 @deffn {Config Command} {etb config} target etb_tap
5270 Associates the ETM for @var{target} with the ETB at @var{etb_tap}.
5271 You can see the ETB registers using the @command{reg} command.
5275 @deffn {Trace Port Driver} oocd_trace
5276 This driver isn't available unless OpenOCD was explicitly configured
5277 with the @option{--enable-oocd_trace} option. You probably don't want
5278 to configure it unless you've built the appropriate prototype hardware;
5279 it's @emph{proof-of-concept} software.
5281 Use the @option{oocd_trace} driver if you are configuring an ETM that's
5282 connected to an off-chip trace connector.
5284 @deffn {Config Command} {oocd_trace config} target tty
5285 Associates the ETM for @var{target} with a trace driver which
5286 collects data through the serial port @var{tty}.
5289 @deffn Command {oocd_trace resync}
5290 Re-synchronizes with the capture clock.
5293 @deffn Command {oocd_trace status}
5294 Reports whether the capture clock is locked or not.
5299 @section ARMv4 and ARMv5 Architecture
5303 These commands are specific to ARM architecture v4 and v5,
5304 including all ARM7 or ARM9 systems and Intel XScale.
5305 They are available in addition to other core-specific
5306 commands that may be available.
5308 @deffn Command {armv4_5 core_state} [@option{arm}|@option{thumb}]
5309 Displays the core_state, optionally changing it to process
5310 either @option{arm} or @option{thumb} instructions.
5311 The target may later be resumed in the currently set core_state.
5312 (Processors may also support the Jazelle state, but
5313 that is not currently supported in OpenOCD.)
5316 @deffn Command {armv4_5 disassemble} address [count [@option{thumb}]]
5318 Disassembles @var{count} instructions starting at @var{address}.
5319 If @var{count} is not specified, a single instruction is disassembled.
5320 If @option{thumb} is specified, or the low bit of the address is set,
5321 Thumb (16-bit) instructions are used;
5322 else ARM (32-bit) instructions are used.
5323 (Processors may also support the Jazelle state, but
5324 those instructions are not currently understood by OpenOCD.)
5327 @deffn Command {armv4_5 reg}
5328 Display a table of all banked core registers, fetching the current value from every
5329 core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
5333 @subsection ARM7 and ARM9 specific commands
5337 These commands are specific to ARM7 and ARM9 cores, like ARM7TDMI, ARM720T,
5338 ARM9TDMI, ARM920T or ARM926EJ-S.
5339 They are available in addition to the ARMv4/5 commands,
5340 and any other core-specific commands that may be available.
5342 @deffn Command {arm7_9 dbgrq} (@option{enable}|@option{disable})
5343 Control use of the EmbeddedIce DBGRQ signal to force entry into debug mode,
5344 instead of breakpoints. This should be
5345 safe for all but ARM7TDMI--S cores (like Philips LPC).
5346 This feature is enabled by default on most ARM9 cores,
5347 including ARM9TDMI, ARM920T, and ARM926EJ-S.
5350 @deffn Command {arm7_9 dcc_downloads} (@option{enable}|@option{disable})
5352 Control the use of the debug communications channel (DCC) to write larger (>128 byte)
5353 amounts of memory. DCC downloads offer a huge speed increase, but might be
5354 unsafe, especially with targets running at very low speeds. This command was introduced
5355 with OpenOCD rev. 60, and requires a few bytes of working area.
5358 @anchor{arm7_9 fast_memory_access}
5359 @deffn Command {arm7_9 fast_memory_access} (@option{enable}|@option{disable})
5360 Enable or disable memory writes and reads that don't check completion of
5361 the operation. This provides a huge speed increase, especially with USB JTAG
5362 cables (FT2232), but might be unsafe if used with targets running at very low
5363 speeds, like the 32kHz startup clock of an AT91RM9200.
5366 @deffn {Debug Command} {arm7_9 write_core_reg} num mode word
5367 @emph{This is intended for use while debugging OpenOCD; you probably
5370 Writes a 32-bit @var{word} to register @var{num} (from 0 to 16)
5371 as used in the specified @var{mode}
5372 (where e.g. mode 16 is "user" and mode 19 is "supervisor";
5373 the M4..M0 bits of the PSR).
5374 Registers 0..15 are the normal CPU registers such as r0(0), r1(1) ... pc(15).
5375 Register 16 is the mode-specific SPSR,
5376 unless the specified mode is 0xffffffff (32-bit all-ones)
5377 in which case register 16 is the CPSR.
5378 The write goes directly to the CPU, bypassing the register cache.
5381 @deffn {Debug Command} {arm7_9 write_xpsr} word (@option{0}|@option{1})
5382 @emph{This is intended for use while debugging OpenOCD; you probably
5385 If the second parameter is zero, writes @var{word} to the
5386 Current Program Status register (CPSR).
5387 Else writes @var{word} to the current mode's Saved PSR (SPSR).
5388 In both cases, this bypasses the register cache.
5391 @deffn {Debug Command} {arm7_9 write_xpsr_im8} byte rotate (@option{0}|@option{1})
5392 @emph{This is intended for use while debugging OpenOCD; you probably
5395 Writes eight bits to the CPSR or SPSR,
5396 first rotating them by @math{2*rotate} bits,
5397 and bypassing the register cache.
5398 This has lower JTAG overhead than writing the entire CPSR or SPSR
5399 with @command{arm7_9 write_xpsr}.
5402 @subsection ARM720T specific commands
5405 These commands are available to ARM720T based CPUs,
5406 which are implementations of the ARMv4T architecture
5407 based on the ARM7TDMI-S integer core.
5408 They are available in addition to the ARMv4/5 and ARM7/ARM9 commands.
5410 @deffn Command {arm720t cp15} regnum [value]
5411 Display cp15 register @var{regnum};
5412 else if a @var{value} is provided, that value is written to that register.
5415 @deffn Command {arm720t mdw_phys} addr [count]
5416 @deffnx Command {arm720t mdh_phys} addr [count]
5417 @deffnx Command {arm720t mdb_phys} addr [count]
5418 Display contents of physical address @var{addr}, as
5419 32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
5420 or 8-bit bytes (@command{mdb_phys}).
5421 If @var{count} is specified, displays that many units.
5424 @deffn Command {arm720t mww_phys} addr word
5425 @deffnx Command {arm720t mwh_phys} addr halfword
5426 @deffnx Command {arm720t mwb_phys} addr byte
5427 Writes the specified @var{word} (32 bits),
5428 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
5429 at the specified physical address @var{addr}.
5432 @deffn Command {arm720t virt2phys} va
5433 Translate a virtual address @var{va} to a physical address
5434 and display the result.
5437 @subsection ARM9 specific commands
5440 ARM9-family cores are built around ARM9TDMI or ARM9E (including ARM9EJS)
5442 Such cores include the ARM920T, ARM926EJ-S, and ARM966.
5444 For historical reasons, one command shared by these cores starts
5445 with the @command{arm9tdmi} prefix.
5446 This is true even for ARM9E based processors, which implement the
5447 ARMv5TE architecture instead of ARMv4T.
5449 @c 9-june-2009: tried this on arm920t, it didn't work.
5450 @c no-params always lists nothing caught, and that's how it acts.
5452 @anchor{arm9tdmi vector_catch}
5453 @deffn Command {arm9tdmi vector_catch} [@option{all}|@option{none}|list]
5454 @cindex vector_catch
5455 Vector Catch hardware provides a sort of dedicated breakpoint
5456 for hardware events such as reset, interrupt, and abort.
5457 You can use this to conserve normal breakpoint resources,
5458 so long as you're not concerned with code that branches directly
5459 to those hardware vectors.
5461 This always finishes by listing the current configuration.
5462 If parameters are provided, it first reconfigures the
5463 vector catch hardware to intercept
5464 @option{all} of the hardware vectors,
5465 @option{none} of them,
5466 or a list with one or more of the following:
5467 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt} @option{reserved}
5468 @option{irq} @option{fiq}.
5471 @subsection ARM920T specific commands
5474 These commands are available to ARM920T based CPUs,
5475 which are implementations of the ARMv4T architecture
5476 built using the ARM9TDMI integer core.
5477 They are available in addition to the ARMv4/5, ARM7/ARM9,
5478 and ARM9TDMI commands.
5480 @deffn Command {arm920t cache_info}
5481 Print information about the caches found. This allows to see whether your target
5482 is an ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
5485 @deffn Command {arm920t cp15} regnum [value]
5486 Display cp15 register @var{regnum};
5487 else if a @var{value} is provided, that value is written to that register.
5490 @deffn Command {arm920t cp15i} opcode [value [address]]
5491 Interpreted access using cp15 @var{opcode}.
5492 If no @var{value} is provided, the result is displayed.
5493 Else if that value is written using the specified @var{address},
5494 or using zero if no other address is not provided.
5497 @deffn Command {arm920t mdw_phys} addr [count]
5498 @deffnx Command {arm920t mdh_phys} addr [count]
5499 @deffnx Command {arm920t mdb_phys} addr [count]
5500 Display contents of physical address @var{addr}, as
5501 32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
5502 or 8-bit bytes (@command{mdb_phys}).
5503 If @var{count} is specified, displays that many units.
5506 @deffn Command {arm920t mww_phys} addr word
5507 @deffnx Command {arm920t mwh_phys} addr halfword
5508 @deffnx Command {arm920t mwb_phys} addr byte
5509 Writes the specified @var{word} (32 bits),
5510 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
5511 at the specified physical address @var{addr}.
5514 @deffn Command {arm920t read_cache} filename
5515 Dump the content of ICache and DCache to a file named @file{filename}.
5518 @deffn Command {arm920t read_mmu} filename
5519 Dump the content of the ITLB and DTLB to a file named @file{filename}.
5522 @deffn Command {arm920t virt2phys} va
5523 Translate a virtual address @var{va} to a physical address
5524 and display the result.
5527 @subsection ARM926ej-s specific commands
5530 These commands are available to ARM926ej-s based CPUs,
5531 which are implementations of the ARMv5TEJ architecture
5532 based on the ARM9EJ-S integer core.
5533 They are available in addition to the ARMv4/5, ARM7/ARM9,
5534 and ARM9TDMI commands.
5536 The Feroceon cores also support these commands, although
5537 they are not built from ARM926ej-s designs.
5539 @deffn Command {arm926ejs cache_info}
5540 Print information about the caches found.
5543 @deffn Command {arm926ejs cp15} opcode1 opcode2 CRn CRm regnum [value]
5544 Accesses cp15 register @var{regnum} using
5545 @var{opcode1}, @var{opcode2}, @var{CRn}, and @var{CRm}.
5546 If a @var{value} is provided, that value is written to that register.
5547 Else that register is read and displayed.
5550 @deffn Command {arm926ejs mdw_phys} addr [count]
5551 @deffnx Command {arm926ejs mdh_phys} addr [count]
5552 @deffnx Command {arm926ejs mdb_phys} addr [count]
5553 Display contents of physical address @var{addr}, as
5554 32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
5555 or 8-bit bytes (@command{mdb_phys}).
5556 If @var{count} is specified, displays that many units.
5559 @deffn Command {arm926ejs mww_phys} addr word
5560 @deffnx Command {arm926ejs mwh_phys} addr halfword
5561 @deffnx Command {arm926ejs mwb_phys} addr byte
5562 Writes the specified @var{word} (32 bits),
5563 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
5564 at the specified physical address @var{addr}.
5567 @deffn Command {arm926ejs virt2phys} va
5568 Translate a virtual address @var{va} to a physical address
5569 and display the result.
5572 @subsection ARM966E specific commands
5575 These commands are available to ARM966 based CPUs,
5576 which are implementations of the ARMv5TE architecture.
5577 They are available in addition to the ARMv4/5, ARM7/ARM9,
5578 and ARM9TDMI commands.
5580 @deffn Command {arm966e cp15} regnum [value]
5581 Display cp15 register @var{regnum};
5582 else if a @var{value} is provided, that value is written to that register.
5585 @subsection XScale specific commands
5588 Some notes about the debug implementation on the XScale CPUs:
5590 The XScale CPU provides a special debug-only mini-instruction cache
5591 (mini-IC) in which exception vectors and target-resident debug handler
5592 code are placed by OpenOCD. In order to get access to the CPU, OpenOCD
5593 must point vector 0 (the reset vector) to the entry of the debug
5594 handler. However, this means that the complete first cacheline in the
5595 mini-IC is marked valid, which makes the CPU fetch all exception
5596 handlers from the mini-IC, ignoring the code in RAM.
5598 OpenOCD currently does not sync the mini-IC entries with the RAM
5599 contents (which would fail anyway while the target is running), so
5600 the user must provide appropriate values using the @code{xscale
5601 vector_table} command.
5603 It is recommended to place a pc-relative indirect branch in the vector
5604 table, and put the branch destination somewhere in memory. Doing so
5605 makes sure the code in the vector table stays constant regardless of
5606 code layout in memory:
5609 ldr pc,[pc,#0x100-8]
5610 ldr pc,[pc,#0x100-8]
5611 ldr pc,[pc,#0x100-8]
5612 ldr pc,[pc,#0x100-8]
5613 ldr pc,[pc,#0x100-8]
5614 ldr pc,[pc,#0x100-8]
5615 ldr pc,[pc,#0x100-8]
5616 ldr pc,[pc,#0x100-8]
5618 .long real_reset_vector
5619 .long real_ui_handler
5620 .long real_swi_handler
5622 .long real_data_abort
5623 .long 0 /* unused */
5624 .long real_irq_handler
5625 .long real_fiq_handler
5628 The debug handler must be placed somewhere in the address space using
5629 the @code{xscale debug_handler} command. The allowed locations for the
5630 debug handler are either (0x800 - 0x1fef800) or (0xfe000800 -
5631 0xfffff800). The default value is 0xfe000800.
5634 These commands are available to XScale based CPUs,
5635 which are implementations of the ARMv5TE architecture.
5637 @deffn Command {xscale analyze_trace}
5638 Displays the contents of the trace buffer.
5641 @deffn Command {xscale cache_clean_address} address
5642 Changes the address used when cleaning the data cache.
5645 @deffn Command {xscale cache_info}
5646 Displays information about the CPU caches.
5649 @deffn Command {xscale cp15} regnum [value]
5650 Display cp15 register @var{regnum};
5651 else if a @var{value} is provided, that value is written to that register.
5654 @deffn Command {xscale debug_handler} target address
5655 Changes the address used for the specified target's debug handler.
5658 @deffn Command {xscale dcache} (@option{enable}|@option{disable})
5659 Enables or disable the CPU's data cache.
5662 @deffn Command {xscale dump_trace} filename
5663 Dumps the raw contents of the trace buffer to @file{filename}.
5666 @deffn Command {xscale icache} (@option{enable}|@option{disable})
5667 Enables or disable the CPU's instruction cache.
5670 @deffn Command {xscale mmu} (@option{enable}|@option{disable})
5671 Enables or disable the CPU's memory management unit.
5674 @deffn Command {xscale trace_buffer} (@option{enable}|@option{disable}) [@option{fill} [n] | @option{wrap}]
5675 Enables or disables the trace buffer,
5676 and controls how it is emptied.
5679 @deffn Command {xscale trace_image} filename [offset [type]]
5680 Opens a trace image from @file{filename}, optionally rebasing
5681 its segment addresses by @var{offset}.
5682 The image @var{type} may be one of
5683 @option{bin} (binary), @option{ihex} (Intel hex),
5684 @option{elf} (ELF file), @option{s19} (Motorola s19),
5685 @option{mem}, or @option{builder}.
5688 @anchor{xscale vector_catch}
5689 @deffn Command {xscale vector_catch} [mask]
5690 @cindex vector_catch
5691 Display a bitmask showing the hardware vectors to catch.
5692 If the optional parameter is provided, first set the bitmask to that value.
5694 The mask bits correspond with bit 16..23 in the DCSR:
5697 0x02 Trap Undefined Instructions
5698 0x04 Trap Software Interrupt
5699 0x08 Trap Prefetch Abort
5700 0x10 Trap Data Abort
5707 @anchor{xscale vector_table}
5708 @deffn Command {xscale vector_table} [<low|high> <index> <value>]
5709 @cindex vector_table
5711 Set an entry in the mini-IC vector table. There are two tables: one for
5712 low vectors (at 0x00000000), and one for high vectors (0xFFFF0000), each
5713 holding the 8 exception vectors. @var{index} can be 1-7, because vector 0
5714 points to the debug handler entry and can not be overwritten.
5715 @var{value} holds the 32-bit opcode that is placed in the mini-IC.
5717 Without arguments, the current settings are displayed.
5721 @section ARMv6 Architecture
5724 @subsection ARM11 specific commands
5727 @deffn Command {arm11 mcr} pX opc1 CRn CRm opc2 value
5728 Write @var{value} to a coprocessor @var{pX} register
5729 passing parameters @var{CRn},
5730 @var{CRm}, opcodes @var{opc1} and @var{opc2},
5731 and the MCR instruction.
5732 (The difference beween this and the MCR2 instruction is
5733 one bit in the encoding, effecively a fifth parameter.)
5736 @deffn Command {arm11 memwrite burst} [value]
5737 Displays the value of the memwrite burst-enable flag,
5738 which is enabled by default.
5739 If @var{value} is defined, first assigns that.
5742 @deffn Command {arm11 memwrite error_fatal} [value]
5743 Displays the value of the memwrite error_fatal flag,
5744 which is enabled by default.
5745 If @var{value} is defined, first assigns that.
5748 @deffn Command {arm11 mrc} pX opc1 CRn CRm opc2
5749 Read a coprocessor @var{pX} register passing parameters @var{CRn},
5750 @var{CRm}, opcodes @var{opc1} and @var{opc2},
5751 and the MRC instruction.
5752 (The difference beween this and the MRC2 instruction is
5753 one bit in the encoding, effecively a fifth parameter.)
5754 Displays the result.
5757 @deffn Command {arm11 no_increment} [value]
5758 Displays the value of the flag controlling whether
5759 some read or write operations increment the pointer
5760 (the default behavior) or not (acting like a FIFO).
5761 If @var{value} is defined, first assigns that.
5764 @deffn Command {arm11 step_irq_enable} [value]
5765 Displays the value of the flag controlling whether
5766 IRQs are enabled during single stepping;
5767 they are disabled by default.
5768 If @var{value} is defined, first assigns that.
5771 @deffn Command {arm11 vcr} [value]
5772 @cindex vector_catch
5773 Displays the value of the @emph{Vector Catch Register (VCR)},
5774 coprocessor 14 register 7.
5775 If @var{value} is defined, first assigns that.
5777 Vector Catch hardware provides dedicated breakpoints
5778 for certain hardware events.
5779 The specific bit values are core-specific (as in fact is using
5780 coprocessor 14 register 7 itself) but all current ARM11
5781 cores @emph{except the ARM1176} use the same six bits.
5784 @section ARMv7 Architecture
5787 @subsection ARMv7 Debug Access Port (DAP) specific commands
5788 @cindex Debug Access Port
5790 These commands are specific to ARM architecture v7 Debug Access Port (DAP),
5791 included on cortex-m3 and cortex-a8 systems.
5792 They are available in addition to other core-specific commands that may be available.
5794 @deffn Command {dap info} [num]
5795 Displays dap info for ap @var{num}, defaulting to the currently selected AP.
5798 @deffn Command {dap apsel} [num]
5799 Select AP @var{num}, defaulting to 0.
5802 @deffn Command {dap apid} [num]
5803 Displays id register from AP @var{num},
5804 defaulting to the currently selected AP.
5807 @deffn Command {dap baseaddr} [num]
5808 Displays debug base address from AP @var{num},
5809 defaulting to the currently selected AP.
5812 @deffn Command {dap memaccess} [value]
5813 Displays the number of extra tck for mem-ap memory bus access [0-255].
5814 If @var{value} is defined, first assigns that.
5817 @subsection ARMv7-A specific commands
5820 @deffn Command {armv7a disassemble} address [count [@option{thumb}]]
5822 Disassembles @var{count} instructions starting at @var{address}.
5823 If @var{count} is not specified, a single instruction is disassembled.
5824 If @option{thumb} is specified, or the low bit of the address is set,
5825 Thumb2 (mixed 16/32-bit) instructions are used;
5826 else ARM (32-bit) instructions are used.
5827 With a handful of exceptions, ThumbEE instructions are the same as Thumb2;
5828 ThumbEE disassembly currently has no explicit support.
5829 (Processors may also support the Jazelle state, but
5830 those instructions are not currently understood by OpenOCD.)
5834 @subsection Cortex-M3 specific commands
5837 @deffn Command {cortex_m3 disassemble} address [count]
5839 Disassembles @var{count} Thumb2 instructions starting at @var{address}.
5840 If @var{count} is not specified, a single instruction is disassembled.
5843 @deffn Command {cortex_m3 maskisr} (@option{on}|@option{off})
5844 Control masking (disabling) interrupts during target step/resume.
5847 @deffn Command {cortex_m3 vector_catch} [@option{all}|@option{none}|list]
5848 @cindex vector_catch
5849 Vector Catch hardware provides dedicated breakpoints
5850 for certain hardware events.
5852 Parameters request interception of
5853 @option{all} of these hardware event vectors,
5854 @option{none} of them,
5855 or one or more of the following:
5856 @option{hard_err} for a HardFault exception;
5857 @option{mm_err} for a MemManage exception;
5858 @option{bus_err} for a BusFault exception;
5861 @option{chk_err}, or
5862 @option{nocp_err} for various UsageFault exceptions; or
5864 If NVIC setup code does not enable them,
5865 MemManage, BusFault, and UsageFault exceptions
5866 are mapped to HardFault.
5867 UsageFault checks for
5868 divide-by-zero and unaligned access
5869 must also be explicitly enabled.
5871 This finishes by listing the current vector catch configuration.
5874 @anchor{Software Debug Messages and Tracing}
5875 @section Software Debug Messages and Tracing
5876 @cindex Linux-ARM DCC support
5880 OpenOCD can process certain requests from target software. Currently
5881 @command{target_request debugmsgs}
5882 is supported only for @option{arm7_9} and @option{cortex_m3} cores.
5883 These messages are received as part of target polling, so
5884 you need to have @command{poll on} active to receive them.
5885 They are intrusive in that they will affect program execution
5886 times. If that is a problem, @pxref{ARM Hardware Tracing}.
5888 See @file{libdcc} in the contrib dir for more details.
5889 In addition to sending strings, characters, and
5890 arrays of various size integers from the target,
5891 @file{libdcc} also exports a software trace point mechanism.
5892 The target being debugged may
5893 issue trace messages which include a 24-bit @dfn{trace point} number.
5894 Trace point support includes two distinct mechanisms,
5895 each supported by a command:
5898 @item @emph{History} ... A circular buffer of trace points
5899 can be set up, and then displayed at any time.
5900 This tracks where code has been, which can be invaluable in
5901 finding out how some fault was triggered.
5903 The buffer may overflow, since it collects records continuously.
5904 It may be useful to use some of the 24 bits to represent a
5905 particular event, and other bits to hold data.
5907 @item @emph{Counting} ... An array of counters can be set up,
5908 and then displayed at any time.
5909 This can help establish code coverage and identify hot spots.
5911 The array of counters is directly indexed by the trace point
5912 number, so trace points with higher numbers are not counted.
5915 Linux-ARM kernels have a ``Kernel low-level debugging
5916 via EmbeddedICE DCC channel'' option (CONFIG_DEBUG_ICEDCC,
5917 depends on CONFIG_DEBUG_LL) which uses this mechanism to
5918 deliver messages before a serial console can be activated.
5919 This is not the same format used by @file{libdcc}.
5920 Other software, such as the U-Boot boot loader, sometimes
5921 does the same thing.
5923 @deffn Command {target_request debugmsgs} [@option{enable}|@option{disable}|@option{charmsg}]
5924 Displays current handling of target DCC message requests.
5925 These messages may be sent to the debugger while the target is running.
5926 The optional @option{enable} and @option{charmsg} parameters
5927 both enable the messages, while @option{disable} disables them.
5929 With @option{charmsg} the DCC words each contain one character,
5930 as used by Linux with CONFIG_DEBUG_ICEDCC;
5931 otherwise the libdcc format is used.
5934 @deffn Command {trace history} [@option{clear}|count]
5935 With no parameter, displays all the trace points that have triggered
5936 in the order they triggered.
5937 With the parameter @option{clear}, erases all current trace history records.
5938 With a @var{count} parameter, allocates space for that many
5942 @deffn Command {trace point} [@option{clear}|identifier]
5943 With no parameter, displays all trace point identifiers and how many times
5944 they have been triggered.
5945 With the parameter @option{clear}, erases all current trace point counters.
5946 With a numeric @var{identifier} parameter, creates a new a trace point counter
5947 and associates it with that identifier.
5949 @emph{Important:} The identifier and the trace point number
5950 are not related except by this command.
5951 These trace point numbers always start at zero (from server startup,
5952 or after @command{trace point clear}) and count up from there.
5957 @chapter JTAG Commands
5958 @cindex JTAG Commands
5959 Most general purpose JTAG commands have been presented earlier.
5960 (@xref{JTAG Speed}, @ref{Reset Configuration}, and @ref{TAP Declaration}.)
5961 Lower level JTAG commands, as presented here,
5962 may be needed to work with targets which require special
5963 attention during operations such as reset or initialization.
5965 To use these commands you will need to understand some
5966 of the basics of JTAG, including:
5969 @item A JTAG scan chain consists of a sequence of individual TAP
5970 devices such as a CPUs.
5971 @item Control operations involve moving each TAP through the same
5972 standard state machine (in parallel)
5973 using their shared TMS and clock signals.
5974 @item Data transfer involves shifting data through the chain of
5975 instruction or data registers of each TAP, writing new register values
5976 while the reading previous ones.
5977 @item Data register sizes are a function of the instruction active in
5978 a given TAP, while instruction register sizes are fixed for each TAP.
5979 All TAPs support a BYPASS instruction with a single bit data register.
5980 @item The way OpenOCD differentiates between TAP devices is by
5981 shifting different instructions into (and out of) their instruction
5985 @section Low Level JTAG Commands
5987 These commands are used by developers who need to access
5988 JTAG instruction or data registers, possibly controlling
5989 the order of TAP state transitions.
5990 If you're not debugging OpenOCD internals, or bringing up a
5991 new JTAG adapter or a new type of TAP device (like a CPU or
5992 JTAG router), you probably won't need to use these commands.
5994 @deffn Command {drscan} tap [numbits value]+ [@option{-endstate} tap_state]
5995 Loads the data register of @var{tap} with a series of bit fields
5996 that specify the entire register.
5997 Each field is @var{numbits} bits long with
5998 a numeric @var{value} (hexadecimal encouraged).
5999 The return value holds the original value of each
6002 For example, a 38 bit number might be specified as one
6003 field of 32 bits then one of 6 bits.
6004 @emph{For portability, never pass fields which are more
6005 than 32 bits long. Many OpenOCD implementations do not
6006 support 64-bit (or larger) integer values.}
6008 All TAPs other than @var{tap} must be in BYPASS mode.
6009 The single bit in their data registers does not matter.
6011 When @var{tap_state} is specified, the JTAG state machine is left
6013 For example @sc{drpause} might be specified, so that more
6014 instructions can be issued before re-entering the @sc{run/idle} state.
6015 If the end state is not specified, the @sc{run/idle} state is entered.
6018 OpenOCD does not record information about data register lengths,
6019 so @emph{it is important that you get the bit field lengths right}.
6020 Remember that different JTAG instructions refer to different
6021 data registers, which may have different lengths.
6022 Moreover, those lengths may not be fixed;
6023 the SCAN_N instruction can change the length of
6024 the register accessed by the INTEST instruction
6025 (by connecting a different scan chain).
6029 @deffn Command {flush_count}
6030 Returns the number of times the JTAG queue has been flushed.
6031 This may be used for performance tuning.
6033 For example, flushing a queue over USB involves a
6034 minimum latency, often several milliseconds, which does
6035 not change with the amount of data which is written.
6036 You may be able to identify performance problems by finding
6037 tasks which waste bandwidth by flushing small transfers too often,
6038 instead of batching them into larger operations.
6041 @deffn Command {irscan} [tap instruction]+ [@option{-endstate} tap_state]
6042 For each @var{tap} listed, loads the instruction register
6043 with its associated numeric @var{instruction}.
6044 (The number of bits in that instruction may be displayed
6045 using the @command{scan_chain} command.)
6046 For other TAPs, a BYPASS instruction is loaded.
6048 When @var{tap_state} is specified, the JTAG state machine is left
6050 For example @sc{irpause} might be specified, so the data register
6051 can be loaded before re-entering the @sc{run/idle} state.
6052 If the end state is not specified, the @sc{run/idle} state is entered.
6055 OpenOCD currently supports only a single field for instruction
6056 register values, unlike data register values.
6057 For TAPs where the instruction register length is more than 32 bits,
6058 portable scripts currently must issue only BYPASS instructions.
6062 @deffn Command {jtag_reset} trst srst
6063 Set values of reset signals.
6064 The @var{trst} and @var{srst} parameter values may be
6065 @option{0}, indicating that reset is inactive (pulled or driven high),
6066 or @option{1}, indicating it is active (pulled or driven low).
6067 The @command{reset_config} command should already have been used
6068 to configure how the board and JTAG adapter treat these two
6069 signals, and to say if either signal is even present.
6070 @xref{Reset Configuration}.
6072 Note that TRST is specially handled.
6073 It actually signifies JTAG's @sc{reset} state.
6074 So if the board doesn't support the optional TRST signal,
6075 or it doesn't support it along with the specified SRST value,
6076 JTAG reset is triggered with TMS and TCK signals
6077 instead of the TRST signal.
6078 And no matter how that JTAG reset is triggered, once
6079 the scan chain enters @sc{reset} with TRST inactive,
6080 TAP @code{post-reset} events are delivered to all TAPs
6081 with handlers for that event.
6084 @deffn Command {runtest} @var{num_cycles}
6085 Move to the @sc{run/idle} state, and execute at least
6086 @var{num_cycles} of the JTAG clock (TCK).
6087 Instructions often need some time
6088 to execute before they take effect.
6091 @c tms_sequence (short|long)
6092 @c ... temporary, debug-only, probably gone before 0.2 ships
6094 @deffn Command {verify_ircapture} (@option{enable}|@option{disable})
6095 Verify values captured during @sc{ircapture} and returned
6096 during IR scans. Default is enabled, but this can be
6097 overridden by @command{verify_jtag}.
6100 @deffn Command {verify_jtag} (@option{enable}|@option{disable})
6101 Enables verification of DR and IR scans, to help detect
6102 programming errors. For IR scans, @command{verify_ircapture}
6103 must also be enabled.
6107 @section TAP state names
6108 @cindex TAP state names
6110 The @var{tap_state} names used by OpenOCD in the @command{drscan},
6111 and @command{irscan} commands are:
6114 @item @b{RESET} ... acts as if TRST were pulsed
6115 @item @b{RUN/IDLE} ... don't assume this always means IDLE
6118 @item @b{DRSHIFT} ... TDI/TDO shifting through the data register
6120 @item @b{DRPAUSE} ... data register ready for update or more shifting
6125 @item @b{IRSHIFT} ... TDI/TDO shifting through the instruction register
6127 @item @b{IRPAUSE} ... instruction register ready for update or more shifting
6132 Note that only six of those states are fully ``stable'' in the
6133 face of TMS fixed (low except for @sc{reset})
6134 and a free-running JTAG clock. For all the
6135 others, the next TCK transition changes to a new state.
6138 @item From @sc{drshift} and @sc{irshift}, clock transitions will
6139 produce side effects by changing register contents. The values
6140 to be latched in upcoming @sc{drupdate} or @sc{irupdate} states
6141 may not be as expected.
6142 @item @sc{run/idle}, @sc{drpause}, and @sc{irpause} are reasonable
6143 choices after @command{drscan} or @command{irscan} commands,
6144 since they are free of JTAG side effects.
6145 @item @sc{run/idle} may have side effects that appear at non-JTAG
6146 levels, such as advancing the ARM9E-S instruction pipeline.
6147 Consult the documentation for the TAP(s) you are working with.
6150 @node Boundary Scan Commands
6151 @chapter Boundary Scan Commands
6153 One of the original purposes of JTAG was to support
6154 boundary scan based hardware testing.
6155 Although its primary focus is to support On-Chip Debugging,
6156 OpenOCD also includes some boundary scan commands.
6158 @section SVF: Serial Vector Format
6159 @cindex Serial Vector Format
6162 The Serial Vector Format, better known as @dfn{SVF}, is a
6163 way to represent JTAG test patterns in text files.
6164 OpenOCD supports running such test files.
6166 @deffn Command {svf} filename [@option{quiet}]
6167 This issues a JTAG reset (Test-Logic-Reset) and then
6168 runs the SVF script from @file{filename}.
6169 Unless the @option{quiet} option is specified,
6170 each command is logged before it is executed.
6173 @section XSVF: Xilinx Serial Vector Format
6174 @cindex Xilinx Serial Vector Format
6177 The Xilinx Serial Vector Format, better known as @dfn{XSVF}, is a
6178 binary representation of SVF which is optimized for use with
6180 OpenOCD supports running such test files.
6182 @quotation Important
6183 Not all XSVF commands are supported.
6186 @deffn Command {xsvf} (tapname|@option{plain}) filename [@option{virt2}] [@option{quiet}]
6187 This issues a JTAG reset (Test-Logic-Reset) and then
6188 runs the XSVF script from @file{filename}.
6189 When a @var{tapname} is specified, the commands are directed at
6191 When @option{virt2} is specified, the @sc{xruntest} command counts
6192 are interpreted as TCK cycles instead of microseconds.
6193 Unless the @option{quiet} option is specified,
6194 messages are logged for comments and some retries.
6200 If OpenOCD runs on an embedded host(as ZY1000 does), then TFTP can
6201 be used to access files on PCs (either the developer's PC or some other PC).
6203 The way this works on the ZY1000 is to prefix a filename by
6204 "/tftp/ip/" and append the TFTP path on the TFTP
6205 server (tftpd). For example,
6208 load_image /tftp/10.0.0.96/c:\temp\abc.elf
6211 will load c:\temp\abc.elf from the developer pc (10.0.0.96) into memory as
6212 if the file was hosted on the embedded host.
6214 In order to achieve decent performance, you must choose a TFTP server
6215 that supports a packet size bigger than the default packet size (512 bytes). There
6216 are numerous TFTP servers out there (free and commercial) and you will have to do
6217 a bit of googling to find something that fits your requirements.
6219 @node GDB and OpenOCD
6220 @chapter GDB and OpenOCD
6222 OpenOCD complies with the remote gdbserver protocol, and as such can be used
6223 to debug remote targets.
6225 @anchor{Connecting to GDB}
6226 @section Connecting to GDB
6227 @cindex Connecting to GDB
6228 Use GDB 6.7 or newer with OpenOCD if you run into trouble. For
6229 instance GDB 6.3 has a known bug that produces bogus memory access
6230 errors, which has since been fixed: look up 1836 in
6231 @url{http://sourceware.org/cgi-bin/gnatsweb.pl?database=gdb}
6233 OpenOCD can communicate with GDB in two ways:
6237 A socket (TCP/IP) connection is typically started as follows:
6239 target remote localhost:3333
6241 This would cause GDB to connect to the gdbserver on the local pc using port 3333.
6243 A pipe connection is typically started as follows:
6245 target remote | openocd --pipe
6247 This would cause GDB to run OpenOCD and communicate using pipes (stdin/stdout).
6248 Using this method has the advantage of GDB starting/stopping OpenOCD for the debug
6252 To list the available OpenOCD commands type @command{monitor help} on the
6255 OpenOCD supports the gdb @option{qSupported} packet, this enables information
6256 to be sent by the GDB remote server (i.e. OpenOCD) to GDB. Typical information includes
6257 packet size and the device's memory map.
6259 Previous versions of OpenOCD required the following GDB options to increase
6260 the packet size and speed up GDB communication:
6262 set remote memory-write-packet-size 1024
6263 set remote memory-write-packet-size fixed
6264 set remote memory-read-packet-size 1024
6265 set remote memory-read-packet-size fixed
6267 This is now handled in the @option{qSupported} PacketSize and should not be required.
6269 @section Programming using GDB
6270 @cindex Programming using GDB
6272 By default the target memory map is sent to GDB. This can be disabled by
6273 the following OpenOCD configuration option:
6275 gdb_memory_map disable
6277 For this to function correctly a valid flash configuration must also be set
6278 in OpenOCD. For faster performance you should also configure a valid
6281 Informing GDB of the memory map of the target will enable GDB to protect any
6282 flash areas of the target and use hardware breakpoints by default. This means
6283 that the OpenOCD option @command{gdb_breakpoint_override} is not required when
6284 using a memory map. @xref{gdb_breakpoint_override}.
6286 To view the configured memory map in GDB, use the GDB command @option{info mem}
6287 All other unassigned addresses within GDB are treated as RAM.
6289 GDB 6.8 and higher set any memory area not in the memory map as inaccessible.
6290 This can be changed to the old behaviour by using the following GDB command
6292 set mem inaccessible-by-default off
6295 If @command{gdb_flash_program enable} is also used, GDB will be able to
6296 program any flash memory using the vFlash interface.
6298 GDB will look at the target memory map when a load command is given, if any
6299 areas to be programmed lie within the target flash area the vFlash packets
6302 If the target needs configuring before GDB programming, an event
6303 script can be executed:
6305 $_TARGETNAME configure -event EVENTNAME BODY
6308 To verify any flash programming the GDB command @option{compare-sections}
6311 @node Tcl Scripting API
6312 @chapter Tcl Scripting API
6313 @cindex Tcl Scripting API
6317 The commands are stateless. E.g. the telnet command line has a concept
6318 of currently active target, the Tcl API proc's take this sort of state
6319 information as an argument to each proc.
6321 There are three main types of return values: single value, name value
6322 pair list and lists.
6324 Name value pair. The proc 'foo' below returns a name/value pair
6330 > set foo(you) Oyvind
6331 > set foo(mouse) Micky
6332 > set foo(duck) Donald
6340 me Duane you Oyvind mouse Micky duck Donald
6342 Thus, to get the names of the associative array is easy:
6344 foreach { name value } [set foo] {
6345 puts "Name: $name, Value: $value"
6349 Lists returned must be relatively small. Otherwise a range
6350 should be passed in to the proc in question.
6352 @section Internal low-level Commands
6354 By low-level, the intent is a human would not directly use these commands.
6356 Low-level commands are (should be) prefixed with "ocd_", e.g.
6357 @command{ocd_flash_banks}
6358 is the low level API upon which @command{flash banks} is implemented.
6361 @item @b{ocd_mem2array} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
6363 Read memory and return as a Tcl array for script processing
6364 @item @b{ocd_array2mem} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
6366 Convert a Tcl array to memory locations and write the values
6367 @item @b{ocd_flash_banks} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}> <@var{target}> [@option{driver options} ...]
6369 Return information about the flash banks
6372 OpenOCD commands can consist of two words, e.g. "flash banks". The
6373 @file{startup.tcl} "unknown" proc will translate this into a Tcl proc
6374 called "flash_banks".
6376 @section OpenOCD specific Global Variables
6380 Real Tcl has ::tcl_platform(), and platform::identify, and many other
6381 variables. JimTCL, as implemented in OpenOCD creates $HostOS which
6382 holds one of the following values:
6385 @item @b{winxx} Built using Microsoft Visual Studio
6386 @item @b{linux} Linux is the underlying operating sytem
6387 @item @b{darwin} Darwin (mac-os) is the underlying operating sytem.
6388 @item @b{cygwin} Running under Cygwin
6389 @item @b{mingw32} Running under MingW32
6390 @item @b{other} Unknown, none of the above.
6393 Note: 'winxx' was choosen because today (March-2009) no distinction is made between Win32 and Win64.
6396 We should add support for a variable like Tcl variable
6397 @code{tcl_platform(platform)}, it should be called
6398 @code{jim_platform} (because it
6399 is jim, not real tcl).
6403 @chapter Deprecated/Removed Commands
6404 @cindex Deprecated/Removed Commands
6405 Certain OpenOCD commands have been deprecated or
6406 removed during the various revisions.
6408 Upgrade your scripts as soon as possible.
6409 These descriptions for old commands may be removed
6410 a year after the command itself was removed.
6411 This means that in January 2010 this chapter may
6412 become much shorter.
6415 @item @b{arm7_9 fast_writes}
6416 @cindex arm7_9 fast_writes
6417 @*Use @command{arm7_9 fast_memory_access} instead.
6418 @xref{arm7_9 fast_memory_access}.
6421 @*An buggy old command that would not really work since background polling would wipe out the global endstate
6422 @item @b{arm7_9 force_hw_bkpts}
6423 @*Use @command{gdb_breakpoint_override} instead. Note that GDB will use hardware breakpoints
6424 for flash if the GDB memory map has been set up(default when flash is declared in
6425 target configuration). @xref{gdb_breakpoint_override}.
6426 @item @b{arm7_9 sw_bkpts}
6427 @*On by default. @xref{gdb_breakpoint_override}.
6428 @item @b{daemon_startup}
6429 @*this config option has been removed, simply adding @option{init} and @option{reset halt} to
6430 the end of your config script will give the same behaviour as using @option{daemon_startup reset}
6431 and @option{target cortex_m3 little reset_halt 0}.
6432 @item @b{dump_binary}
6433 @*use @option{dump_image} command with same args. @xref{dump_image}.
6434 @item @b{flash erase}
6435 @*use @option{flash erase_sector} command with same args. @xref{flash erase_sector}.
6436 @item @b{flash write}
6437 @*use @option{flash write_bank} command with same args. @xref{flash write_bank}.
6438 @item @b{flash write_binary}
6439 @*use @option{flash write_bank} command with same args. @xref{flash write_bank}.
6440 @item @b{flash auto_erase}
6441 @*use @option{flash write_image} command passing @option{erase} as the first parameter. @xref{flash write_image}.
6443 @item @b{jtag_device}
6444 @*use the @command{jtag newtap} command, converting from positional syntax
6445 to named prefixes, and naming the TAP.
6447 Note that if you try to use the old command, a message will tell you the
6448 right new command to use; and that the fourth parameter in the old syntax
6449 was never actually used.
6451 OLD: jtag_device 8 0x01 0xe3 0xfe
6452 NEW: jtag newtap CHIPNAME TAPNAME \
6453 -irlen 8 -ircapture 0x01 -irmask 0xe3
6456 @item @b{jtag_speed} value
6457 @*@xref{JTAG Speed}.
6458 Usually, a value of zero means maximum
6459 speed. The actual effect of this option depends on the JTAG interface used.
6461 @item wiggler: maximum speed / @var{number}
6462 @item ft2232: 6MHz / (@var{number}+1)
6463 @item amt jtagaccel: 8 / 2**@var{number}
6464 @item jlink: maximum speed in kHz (0-12000), 0 will use RTCK
6465 @item rlink: 24MHz / @var{number}, but only for certain values of @var{number}
6466 @comment end speed list.
6469 @item @b{load_binary}
6470 @*use @option{load_image} command with same args. @xref{load_image}.
6471 @item @b{run_and_halt_time}
6472 @*This command has been removed for simpler reset behaviour, it can be simulated with the
6479 @item @b{target} <@var{type}> <@var{endian}> <@var{jtag-position}>
6480 @*use the create subcommand of @option{target}.
6481 @item @b{target_script} <@var{target#}> <@var{eventname}> <@var{scriptname}>
6482 @*use <@var{target_name}> configure -event <@var{eventname}> "script <@var{scriptname}>"
6483 @item @b{working_area}
6484 @*use the @option{configure} subcommand of @option{target} to set the work-area-virt, work-area-phy, work-area-size, and work-area-backup properties of the target.
6492 @item @b{RTCK, also known as: Adaptive Clocking - What is it?}
6494 @cindex adaptive clocking
6497 In digital circuit design it is often refered to as ``clock
6498 synchronisation'' the JTAG interface uses one clock (TCK or TCLK)
6499 operating at some speed, your target is operating at another. The two
6500 clocks are not synchronised, they are ``asynchronous''
6502 In order for the two to work together they must be synchronised. Otherwise
6503 the two systems will get out of sync with each other and nothing will
6504 work. There are 2 basic options:
6507 Use a special circuit.
6509 One clock must be some multiple slower than the other.
6512 @b{Does this really matter?} For some chips and some situations, this
6513 is a non-issue (i.e.: A 500MHz ARM926) but for others - for example some
6514 Atmel SAM7 and SAM9 chips start operation from reset at 32kHz -
6515 program/enable the oscillators and eventually the main clock. It is in
6516 those critical times you must slow the JTAG clock to sometimes 1 to
6519 Imagine debugging a 500MHz ARM926 hand held battery powered device
6520 that ``deep sleeps'' at 32kHz between every keystroke. It can be
6523 @b{Solution #1 - A special circuit}
6525 In order to make use of this, your JTAG dongle must support the RTCK
6526 feature. Not all dongles support this - keep reading!
6528 The RTCK signal often found in some ARM chips is used to help with
6529 this problem. ARM has a good description of the problem described at
6530 this link: @url{http://www.arm.com/support/faqdev/4170.html} [checked
6531 28/nov/2008]. Link title: ``How does the JTAG synchronisation logic
6532 work? / how does adaptive clocking work?''.
6534 The nice thing about adaptive clocking is that ``battery powered hand
6535 held device example'' - the adaptiveness works perfectly all the
6536 time. One can set a break point or halt the system in the deep power
6537 down code, slow step out until the system speeds up.
6539 Note that adaptive clocking may also need to work at the board level,
6540 when a board-level scan chain has multiple chips.
6541 Parallel clock voting schemes are good way to implement this,
6542 both within and between chips, and can easily be implemented
6544 It's not difficult to have logic fan a module's input TCK signal out
6545 to each TAP in the scan chain, and then wait until each TAP's RTCK comes
6546 back with the right polarity before changing the output RTCK signal.
6547 Texas Instruments makes some clock voting logic available
6548 for free (with no support) in VHDL form; see
6549 @url{http://tiexpressdsp.com/index.php/Adaptive_Clocking}
6551 @b{Solution #2 - Always works - but may be slower}
6553 Often this is a perfectly acceptable solution.
6555 In most simple terms: Often the JTAG clock must be 1/10 to 1/12 of
6556 the target clock speed. But what that ``magic division'' is varies
6557 depending on the chips on your board.
6558 @b{ARM rule of thumb} Most ARM based systems require an 6:1 division;
6559 ARM11 cores use an 8:1 division.
6560 @b{Xilinx rule of thumb} is 1/12 the clock speed.
6562 Note: Many FTDI2232C based JTAG dongles are limited to 6MHz.
6564 You can still debug the 'low power' situations - you just need to
6565 manually adjust the clock speed at every step. While painful and
6566 tedious, it is not always practical.
6568 It is however easy to ``code your way around it'' - i.e.: Cheat a little,
6569 have a special debug mode in your application that does a ``high power
6570 sleep''. If you are careful - 98% of your problems can be debugged
6573 Note that on ARM you may need to avoid using the @emph{wait for interrupt}
6574 operation in your idle loops even if you don't otherwise change the CPU
6576 That operation gates the CPU clock, and thus the JTAG clock; which
6577 prevents JTAG access. One consequence is not being able to @command{halt}
6578 cores which are executing that @emph{wait for interrupt} operation.
6580 To set the JTAG frequency use the command:
6588 @item @b{Win32 Pathnames} Why don't backslashes work in Windows paths?
6590 OpenOCD uses Tcl and a backslash is an escape char. Use @{ and @}
6591 around Windows filenames.
6604 @item @b{Missing: cygwin1.dll} OpenOCD complains about a missing cygwin1.dll.
6606 Make sure you have Cygwin installed, or at least a version of OpenOCD that
6607 claims to come with all the necessary DLLs. When using Cygwin, try launching
6608 OpenOCD from the Cygwin shell.
6610 @item @b{Breakpoint Issue} I'm trying to set a breakpoint using GDB (or a frontend like Insight or
6611 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
6612 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
6614 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
6615 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720T or ARM920T,
6616 software breakpoints consume one of the two available hardware breakpoints.
6618 @item @b{LPC2000 Flash} When erasing or writing LPC2000 on-chip flash, the operation fails at random.
6620 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
6621 clock at the time you're programming the flash. If you've specified the crystal's
6622 frequency, make sure the PLL is disabled. If you've specified the full core speed
6623 (e.g. 60MHz), make sure the PLL is enabled.
6625 @item @b{Amontec Chameleon} When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
6626 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
6627 out while waiting for end of scan, rtck was disabled".
6629 Make sure your PC's parallel port operates in EPP mode. You might have to try several
6630 settings in your PC BIOS (ECP, EPP, and different versions of those).
6632 @item @b{Data Aborts} When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
6633 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
6634 memory read caused data abort".
6636 The errors are non-fatal, and are the result of GDB trying to trace stack frames
6637 beyond the last valid frame. It might be possible to prevent this by setting up
6638 a proper "initial" stack frame, if you happen to know what exactly has to
6639 be done, feel free to add this here.
6641 @b{Simple:} In your startup code - push 8 registers of zeros onto the
6642 stack before calling main(). What GDB is doing is ``climbing'' the run
6643 time stack by reading various values on the stack using the standard
6644 call frame for the target. GDB keeps going - until one of 2 things
6645 happen @b{#1} an invalid frame is found, or @b{#2} some huge number of
6646 stackframes have been processed. By pushing zeros on the stack, GDB
6649 @b{Debugging Interrupt Service Routines} - In your ISR before you call
6650 your C code, do the same - artifically push some zeros onto the stack,
6651 remember to pop them off when the ISR is done.
6653 @b{Also note:} If you have a multi-threaded operating system, they
6654 often do not @b{in the intrest of saving memory} waste these few
6658 @item @b{JTAG Reset Config} I get the following message in the OpenOCD console (or log file):
6659 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
6661 This warning doesn't indicate any serious problem, as long as you don't want to
6662 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
6663 trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
6664 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
6665 independently. With this setup, it's not possible to halt the core right out of
6666 reset, everything else should work fine.
6668 @item @b{USB Power} When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
6669 toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
6670 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
6671 quit with an error message. Is there a stability issue with OpenOCD?
6673 No, this is not a stability issue concerning OpenOCD. Most users have solved
6674 this issue by simply using a self-powered USB hub, which they connect their
6675 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
6676 supply stable enough for the Amontec JTAGkey to be operated.
6678 @b{Laptops running on battery have this problem too...}
6680 @item @b{USB Power} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
6681 following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
6682 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
6683 What does that mean and what might be the reason for this?
6685 First of all, the reason might be the USB power supply. Try using a self-powered
6686 hub instead of a direct connection to your computer. Secondly, the error code 4
6687 corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
6688 chip ran into some sort of error - this points us to a USB problem.
6690 @item @b{GDB Disconnects} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
6691 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
6692 What does that mean and what might be the reason for this?
6694 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
6695 has closed the connection to OpenOCD. This might be a GDB issue.
6697 @item @b{LPC2000 Flash} In the configuration file in the section where flash device configurations
6698 are described, there is a parameter for specifying the clock frequency
6699 for LPC2000 internal flash devices (e.g. @option{flash bank lpc2000
6700 0x0 0x40000 0 0 0 lpc2000_v1 14746 calc_checksum}), which must be
6701 specified in kilohertz. However, I do have a quartz crystal of a
6702 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz,
6703 i.e. 14,745.600 kHz). Is it possible to specify real numbers for the
6706 No. The clock frequency specified here must be given as an integral number.
6707 However, this clock frequency is used by the In-Application-Programming (IAP)
6708 routines of the LPC2000 family only, which seems to be very tolerant concerning
6709 the given clock frequency, so a slight difference between the specified clock
6710 frequency and the actual clock frequency will not cause any trouble.
6712 @item @b{Command Order} Do I have to keep a specific order for the commands in the configuration file?
6714 Well, yes and no. Commands can be given in arbitrary order, yet the
6715 devices listed for the JTAG scan chain must be given in the right
6716 order (jtag newdevice), with the device closest to the TDO-Pin being
6717 listed first. In general, whenever objects of the same type exist
6718 which require an index number, then these objects must be given in the
6719 right order (jtag newtap, targets and flash banks - a target
6720 references a jtag newtap and a flash bank references a target).
6722 You can use the ``scan_chain'' command to verify and display the tap order.
6724 Also, some commands can't execute until after @command{init} has been
6725 processed. Such commands include @command{nand probe} and everything
6726 else that needs to write to controller registers, perhaps for setting
6727 up DRAM and loading it with code.
6729 @anchor{FAQ TAP Order}
6730 @item @b{JTAG TAP Order} Do I have to declare the TAPS in some
6733 Yes; whenever you have more than one, you must declare them in
6734 the same order used by the hardware.
6736 Many newer devices have multiple JTAG TAPs. For example: ST
6737 Microsystems STM32 chips have two TAPs, a ``boundary scan TAP'' and
6738 ``Cortex-M3'' TAP. Example: The STM32 reference manual, Document ID:
6739 RM0008, Section 26.5, Figure 259, page 651/681, the ``TDI'' pin is
6740 connected to the boundary scan TAP, which then connects to the
6741 Cortex-M3 TAP, which then connects to the TDO pin.
6743 Thus, the proper order for the STM32 chip is: (1) The Cortex-M3, then
6744 (2) The boundary scan TAP. If your board includes an additional JTAG
6745 chip in the scan chain (for example a Xilinx CPLD or FPGA) you could
6746 place it before or after the STM32 chip in the chain. For example:
6749 @item OpenOCD_TDI(output) -> STM32 TDI Pin (BS Input)
6750 @item STM32 BS TDO (output) -> STM32 Cortex-M3 TDI (input)
6751 @item STM32 Cortex-M3 TDO (output) -> SM32 TDO Pin
6752 @item STM32 TDO Pin (output) -> Xilinx TDI Pin (input)
6753 @item Xilinx TDO Pin -> OpenOCD TDO (input)
6756 The ``jtag device'' commands would thus be in the order shown below. Note:
6759 @item jtag newtap Xilinx tap -irlen ...
6760 @item jtag newtap stm32 cpu -irlen ...
6761 @item jtag newtap stm32 bs -irlen ...
6762 @item # Create the debug target and say where it is
6763 @item target create stm32.cpu -chain-position stm32.cpu ...
6767 @item @b{SYSCOMP} Sometimes my debugging session terminates with an error. When I look into the
6768 log file, I can see these error messages: Error: arm7_9_common.c:561
6769 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP
6775 @node Tcl Crash Course
6776 @chapter Tcl Crash Course
6779 Not everyone knows Tcl - this is not intended to be a replacement for
6780 learning Tcl, the intent of this chapter is to give you some idea of
6781 how the Tcl scripts work.
6783 This chapter is written with two audiences in mind. (1) OpenOCD users
6784 who need to understand a bit more of how JIM-Tcl works so they can do
6785 something useful, and (2) those that want to add a new command to
6788 @section Tcl Rule #1
6789 There is a famous joke, it goes like this:
6791 @item Rule #1: The wife is always correct
6792 @item Rule #2: If you think otherwise, See Rule #1
6795 The Tcl equal is this:
6798 @item Rule #1: Everything is a string
6799 @item Rule #2: If you think otherwise, See Rule #1
6802 As in the famous joke, the consequences of Rule #1 are profound. Once
6803 you understand Rule #1, you will understand Tcl.
6805 @section Tcl Rule #1b
6806 There is a second pair of rules.
6808 @item Rule #1: Control flow does not exist. Only commands
6809 @* For example: the classic FOR loop or IF statement is not a control
6810 flow item, they are commands, there is no such thing as control flow
6812 @item Rule #2: If you think otherwise, See Rule #1
6813 @* Actually what happens is this: There are commands that by
6814 convention, act like control flow key words in other languages. One of
6815 those commands is the word ``for'', another command is ``if''.
6818 @section Per Rule #1 - All Results are strings
6819 Every Tcl command results in a string. The word ``result'' is used
6820 deliberatly. No result is just an empty string. Remember: @i{Rule #1 -
6821 Everything is a string}
6823 @section Tcl Quoting Operators
6824 In life of a Tcl script, there are two important periods of time, the
6825 difference is subtle.
6828 @item Evaluation Time
6831 The two key items here are how ``quoted things'' work in Tcl. Tcl has
6832 three primary quoting constructs, the [square-brackets] the
6833 @{curly-braces@} and ``double-quotes''
6835 By now you should know $VARIABLES always start with a $DOLLAR
6836 sign. BTW: To set a variable, you actually use the command ``set'', as
6837 in ``set VARNAME VALUE'' much like the ancient BASIC langauge ``let x
6838 = 1'' statement, but without the equal sign.
6841 @item @b{[square-brackets]}
6842 @* @b{[square-brackets]} are command substitutions. It operates much
6843 like Unix Shell `back-ticks`. The result of a [square-bracket]
6844 operation is exactly 1 string. @i{Remember Rule #1 - Everything is a
6845 string}. These two statements are roughly identical:
6849 echo "The Date is: $X"
6852 puts "The Date is: $X"
6854 @item @b{``double-quoted-things''}
6855 @* @b{``double-quoted-things''} are just simply quoted
6856 text. $VARIABLES and [square-brackets] are expanded in place - the
6857 result however is exactly 1 string. @i{Remember Rule #1 - Everything
6861 puts "It is now \"[date]\", $x is in 1 hour"
6863 @item @b{@{Curly-Braces@}}
6864 @*@b{@{Curly-Braces@}} are magic: $VARIABLES and [square-brackets] are
6865 parsed, but are NOT expanded or executed. @{Curly-Braces@} are like
6866 'single-quote' operators in BASH shell scripts, with the added
6867 feature: @{curly-braces@} can be nested, single quotes can not. @{@{@{this is
6868 nested 3 times@}@}@} NOTE: [date] is a bad example;
6869 at this writing, Jim/OpenOCD does not have a date command.
6872 @section Consequences of Rule 1/2/3/4
6874 The consequences of Rule 1 are profound.
6876 @subsection Tokenisation & Execution.
6878 Of course, whitespace, blank lines and #comment lines are handled in
6881 As a script is parsed, each (multi) line in the script file is
6882 tokenised and according to the quoting rules. After tokenisation, that
6883 line is immedatly executed.
6885 Multi line statements end with one or more ``still-open''
6886 @{curly-braces@} which - eventually - closes a few lines later.
6888 @subsection Command Execution
6890 Remember earlier: There are no ``control flow''
6891 statements in Tcl. Instead there are COMMANDS that simply act like
6892 control flow operators.
6894 Commands are executed like this:
6897 @item Parse the next line into (argc) and (argv[]).
6898 @item Look up (argv[0]) in a table and call its function.
6899 @item Repeat until End Of File.
6902 It sort of works like this:
6905 ReadAndParse( &argc, &argv );
6907 cmdPtr = LookupCommand( argv[0] );
6909 (*cmdPtr->Execute)( argc, argv );
6913 When the command ``proc'' is parsed (which creates a procedure
6914 function) it gets 3 parameters on the command line. @b{1} the name of
6915 the proc (function), @b{2} the list of parameters, and @b{3} the body
6916 of the function. Not the choice of words: LIST and BODY. The PROC
6917 command stores these items in a table somewhere so it can be found by
6920 @subsection The FOR command
6922 The most interesting command to look at is the FOR command. In Tcl,
6923 the FOR command is normally implemented in C. Remember, FOR is a
6924 command just like any other command.
6926 When the ascii text containing the FOR command is parsed, the parser
6927 produces 5 parameter strings, @i{(If in doubt: Refer to Rule #1)} they
6931 @item The ascii text 'for'
6932 @item The start text
6933 @item The test expression
6938 Sort of reminds you of ``main( int argc, char **argv )'' does it not?
6939 Remember @i{Rule #1 - Everything is a string.} The key point is this:
6940 Often many of those parameters are in @{curly-braces@} - thus the
6941 variables inside are not expanded or replaced until later.
6943 Remember that every Tcl command looks like the classic ``main( argc,
6944 argv )'' function in C. In JimTCL - they actually look like this:
6948 MyCommand( Jim_Interp *interp,
6950 Jim_Obj * const *argvs );
6953 Real Tcl is nearly identical. Although the newer versions have
6954 introduced a byte-code parser and intepreter, but at the core, it
6955 still operates in the same basic way.
6957 @subsection FOR command implementation
6959 To understand Tcl it is perhaps most helpful to see the FOR
6960 command. Remember, it is a COMMAND not a control flow structure.
6962 In Tcl there are two underlying C helper functions.
6964 Remember Rule #1 - You are a string.
6966 The @b{first} helper parses and executes commands found in an ascii
6967 string. Commands can be seperated by semicolons, or newlines. While
6968 parsing, variables are expanded via the quoting rules.
6970 The @b{second} helper evaluates an ascii string as a numerical
6971 expression and returns a value.
6973 Here is an example of how the @b{FOR} command could be
6974 implemented. The pseudo code below does not show error handling.
6976 void Execute_AsciiString( void *interp, const char *string );
6978 int Evaluate_AsciiExpression( void *interp, const char *string );
6981 MyForCommand( void *interp,
6986 SetResult( interp, "WRONG number of parameters");
6990 // argv[0] = the ascii string just like C
6992 // Execute the start statement.
6993 Execute_AsciiString( interp, argv[1] );
6997 i = Evaluate_AsciiExpression(interp, argv[2]);
7002 Execute_AsciiString( interp, argv[3] );
7004 // Execute the LOOP part
7005 Execute_AsciiString( interp, argv[4] );
7009 SetResult( interp, "" );
7014 Every other command IF, WHILE, FORMAT, PUTS, EXPR, everything works
7015 in the same basic way.
7017 @section OpenOCD Tcl Usage
7019 @subsection source and find commands
7020 @b{Where:} In many configuration files
7021 @* Example: @b{ source [find FILENAME] }
7022 @*Remember the parsing rules
7024 @item The FIND command is in square brackets.
7025 @* The FIND command is executed with the parameter FILENAME. It should
7026 find the full path to the named file. The RESULT is a string, which is
7027 substituted on the orginal command line.
7028 @item The command source is executed with the resulting filename.
7029 @* SOURCE reads a file and executes as a script.
7031 @subsection format command
7032 @b{Where:} Generally occurs in numerous places.
7033 @* Tcl has no command like @b{printf()}, instead it has @b{format}, which is really more like
7039 puts [format "The answer: %d" [expr $x * $y]]
7042 @item The SET command creates 2 variables, X and Y.
7043 @item The double [nested] EXPR command performs math
7044 @* The EXPR command produces numerical result as a string.
7046 @item The format command is executed, producing a single string
7047 @* Refer to Rule #1.
7048 @item The PUTS command outputs the text.
7050 @subsection Body or Inlined Text
7051 @b{Where:} Various TARGET scripts.
7054 proc someproc @{@} @{
7055 ... multiple lines of stuff ...
7057 $_TARGETNAME configure -event FOO someproc
7058 #2 Good - no variables
7059 $_TARGETNAME confgure -event foo "this ; that;"
7060 #3 Good Curly Braces
7061 $_TARGETNAME configure -event FOO @{
7064 #4 DANGER DANGER DANGER
7065 $_TARGETNAME configure -event foo "puts \"Time: [date]\""
7068 @item The $_TARGETNAME is an OpenOCD variable convention.
7069 @*@b{$_TARGETNAME} represents the last target created, the value changes
7070 each time a new target is created. Remember the parsing rules. When
7071 the ascii text is parsed, the @b{$_TARGETNAME} becomes a simple string,
7072 the name of the target which happens to be a TARGET (object)
7074 @item The 2nd parameter to the @option{-event} parameter is a TCBODY
7075 @*There are 4 examples:
7077 @item The TCLBODY is a simple string that happens to be a proc name
7078 @item The TCLBODY is several simple commands seperated by semicolons
7079 @item The TCLBODY is a multi-line @{curly-brace@} quoted string
7080 @item The TCLBODY is a string with variables that get expanded.
7083 In the end, when the target event FOO occurs the TCLBODY is
7084 evaluated. Method @b{#1} and @b{#2} are functionally identical. For
7085 Method @b{#3} and @b{#4} it is more interesting. What is the TCLBODY?
7087 Remember the parsing rules. In case #3, @{curly-braces@} mean the
7088 $VARS and [square-brackets] are expanded later, when the EVENT occurs,
7089 and the text is evaluated. In case #4, they are replaced before the
7090 ``Target Object Command'' is executed. This occurs at the same time
7091 $_TARGETNAME is replaced. In case #4 the date will never
7092 change. @{BTW: [date] is a bad example; at this writing,
7093 Jim/OpenOCD does not have a date command@}
7095 @subsection Global Variables
7096 @b{Where:} You might discover this when writing your own procs @* In
7097 simple terms: Inside a PROC, if you need to access a global variable
7098 you must say so. See also ``upvar''. Example:
7100 proc myproc @{ @} @{
7101 set y 0 #Local variable Y
7102 global x #Global variable X
7103 puts [format "X=%d, Y=%d" $x $y]
7106 @section Other Tcl Hacks
7107 @b{Dynamic variable creation}
7109 # Dynamically create a bunch of variables.
7110 for @{ set x 0 @} @{ $x < 32 @} @{ set x [expr $x + 1]@} @{
7112 set vn [format "BIT%d" $x]
7116 set $vn [expr (1 << $x)]
7119 @b{Dynamic proc/command creation}
7121 # One "X" function - 5 uart functions.
7122 foreach who @{A B C D E@}
7123 proc [format "show_uart%c" $who] @{ @} "show_UARTx $who"
7129 @node OpenOCD Concept Index
7130 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
7131 @comment case issue with ``Index.html'' and ``index.html''
7132 @comment Occurs when creating ``--html --no-split'' output
7133 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
7134 @unnumbered OpenOCD Concept Index
7138 @node Command and Driver Index
7139 @unnumbered Command and Driver Index