1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle Open On-Chip Debugger (openocd)
5 @dircategory Development
7 * OpenOCD: (openocd). Open On-Chip Debugger.
14 Copyright @copyright{} 2007-2008 Spen @email{spen@@spen-soft.co.uk}
16 Permission is granted to copy, distribute and/or modify this document
17 under the terms of the GNU Free Documentation License, Version 1.2 or
18 any later version published by the Free Software Foundation; with no
19 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
20 Texts. A copy of the license is included in the section entitled ``GNU
21 Free Documentation License''.
26 @title Open On-Chip Debugger (openocd)
27 @subtitle Edition @value{EDITION} for openocd version @value{VERSION}
28 @subtitle @value{UPDATED}
30 @vskip 0pt plus 1filll
36 @node Top, About, , (dir)
39 This manual documents edition @value{EDITION} of the Open On-Chip Debugger
40 (openocd) version @value{VERSION}, @value{UPDATED}.
45 * About:: About Openocd.
46 * Developers:: Openocd developers
47 * Building:: Building Openocd
48 * Running:: Running Openocd
49 * Configuration:: Openocd Configuration.
50 * Commands:: Openocd Commands
51 * Sample Scripts:: Sample Target Scripts
52 * GDB and Openocd:: Using GDB and Openocd
53 * FAQ:: Frequently Asked Questions
54 * License:: GNU Free Documentation License
62 The Open On-Chip Debugger (openocd) aims to provide debugging, in-system programming
63 and boundary-scan testing for embedded target devices. The targets are interfaced
64 using JTAG (IEEE 1149.1) compliant hardware, but this may be extended to other
65 connection types in the future.
67 Openocd currently supports Wiggler (clones), FTDI FT2232 based JTAG interfaces, the
68 Amontec JTAG Accelerator, and the Gateworks GW1602. It allows ARM7 (ARM7TDMI and ARM720t),
69 ARM9 (ARM920t, ARM922t, ARM926ej--s, ARM966e--s), XScale (PXA25x, IXP42x) and
70 Cortex-M3 (Luminary Stellaris LM3 and ST STM32) based cores to be debugged.
72 Flash writing is supported for external CFI compatible flashes (Intel and AMD/Spansion
73 command set) and several internal flashes (LPC2000, AT91SAM7, STR7x, STR9x, LM3
74 and STM32x). Preliminary support for using the LPC3180's NAND flash controller is included.
80 Openocd has been created by Dominic Rath as part of a diploma thesis written at the
81 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
82 Others interested in improving the state of free and open debug and testing technology
83 are welcome to participate.
85 Other developers have contributed support for additional targets and flashes as well
86 as numerous bugfixes and enhancements. See the AUTHORS file for regular contributors.
90 @cindex building openocd
92 You can download the current SVN version with SVN client of your choice from the
93 following repositories:
95 (@uref{svn://svn.berlios.de/openocd/trunk})
99 (@uref{http://svn.berlios.de/svnroot/repos/openocd/trunk})
101 Using the SVN command line client, you could use the following command to fetch the
102 latest version (make sure there is no (non-svn) directory called "openocd" in the
106 svn checkout svn://svn.berlios.de/openocd/trunk openocd
109 Building the OpenOCD requires a recent version of the GNU autotools.
110 On my build system, I'm using autoconf 2.13 and automake 1.9. For building on Windows,
111 you have to use Cygwin. Make sure that your @env{PATH} environment variable contains no
112 other locations with Unix utils (like UnxUtils) - these can't handle the Cygwin
113 paths, resulting in obscure dependency errors (This is an observation I've gathered
114 from the logs of one user - correct me if I'm wrong).
116 You further need the appropriate driver files, if you want to build support for
117 a FTDI FT2232 based interface:
119 @item @b{ftdi2232} libftdi (@uref{http://www.intra2net.com/opensource/ftdi/})
120 @item @b{ftd2xx} libftd2xx (@uref{http://www.ftdichip.com/Drivers/D2XX.htm})
121 @item When using the Amontec JTAGkey, you have to get the drivers from the Amontec
122 homepage (@uref{www.amontec.com}), as the JTAGkey uses a non-standard VID/PID.
125 Please note that the ftdi2232 variant (using libftdi) isn't supported under Cygwin.
126 You have to use the ftd2xx variant (using FTDI's D2XX) on Cygwin.
128 In general, the D2XX driver provides superior performance (several times as fast),
129 but has the draw-back of being binary-only - though that isn't as worse, as it isn't
130 a kernel module, only a user space library.
132 To build OpenOCD (on both Linux and Cygwin), use the following commands:
136 Bootstrap generates the configure script, and prepares building on your system.
140 Configure generates the Makefiles used to build OpenOCD.
144 Make builds the OpenOCD, and places the final executable in ./src/.
146 The configure script takes several options, specifying which JTAG interfaces
151 @option{--enable-parport}
153 @option{--enable-parport_ppdev}
155 @option{--enable-amtjtagaccel}
157 @option{--enable-ft2232_ftd2xx}
158 @footnote{Using the latest D2XX drivers from FTDI and following their installation
159 instructions, I had to use @option{--enable-ft2232_libftd2xx} for the OpenOCD to
162 @option{--enable-ft2232_libftdi}
164 @option{--with-ftd2xx=/path/to/d2xx/}
167 If you want to access the parallel port using the PPDEV interface you have to specify
168 both the @option{--enable-parport} AND the @option{--enable-parport_ppdev} option since
169 the @option{--enable-parport_ppdev} option actually is an option to the parport driver
170 (see @uref{http://forum.sparkfun.com/viewtopic.php?t=3795} for more info).
172 Cygwin users have to specify the location of the FTDI D2XX package. This should be an
173 absolute path containing no spaces.
175 Linux users should copy the various parts of the D2XX package to the appropriate
176 locations, i.e. /usr/include, /usr/lib.
180 @cindex running openocd
182 @cindex --debug_level
185 The OpenOCD runs as a daemon, waiting for connections from clients (Telnet or GDB).
186 Run with @option{--help} or @option{-h} to view the available command line arguments.
188 It reads its configuration by default from the file openocd.cfg located in the current
189 working directory. This may be overwritten with the @option{-f <configfile>} command line
192 To enable debug output (when reporting problems or working on OpenOCD itself), use
193 the @option{-d} command line switch. This sets the debug_level to "3", outputting
194 the most information, including debug messages. The default setting is "2", outputting
195 only informational messages, warnings and errors. You can also change this setting
196 from within a telnet or gdb session (@option{debug_level <n>}).
198 You can redirect all output from the daemon to a file using the @option{-l <logfile>} switch.
200 Search paths for config/script files can be added to openocd by using
201 the @option{-s <search>} switch.
204 @chapter Configuration
205 @cindex configuration
206 The Open On-Chip Debugger (OpenOCD) runs as a daemon, and reads it current configuration
207 by default from the file openocd.cfg in the current directory. A different configuration
208 file can be specified with the @option{-f <conf.file>} given at the openocd command line.
210 The configuration file is used to specify on which ports the daemon listens for new
211 connections, the JTAG interface used to connect to the target, the layout of the JTAG
212 chain, the targets that should be debugged, and connected flashes.
214 @section Daemon configuration
217 @item @b{telnet_port} <@var{number}>
219 Port on which to listen for incoming telnet connections
220 @item @b{gdb_port} <@var{number}>
222 First port on which to listen for incoming GDB connections. The GDB port for the
223 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
224 @item @b{gdb_detach} <@var{resume|reset|halt|nothing}>
226 Configures what openocd will do when gdb detaches from the daeman.
227 Default behaviour is <@var{resume}>
228 @item @b{gdb_memory_map} <@var{enable|disable}>
229 @cindex gdb_memory_map
230 Set to <@var{enable}> so that openocd will send the memory configuration to gdb when
231 requested. gdb will then know when to set hardware breakpoints, and program flash
232 using the gdb load command. @option{gdb_flash_program enable} will also need enabling
233 for flash programming to work.
234 Default behaviour is <@var{disable}>
235 @item @b{gdb_flash_program} <@var{enable|disable}>
236 @cindex gdb_flash_program
237 Set to <@var{enable}> so that openocd will program the flash memory when a
238 vFlash packet is received.
239 Default behaviour is <@var{disable}>
240 @item @b{daemon_startup} <@var{mode}> either @samp{attach} or @samp{reset}
241 @cindex daemon_startup
242 Tells the OpenOCD whether it should reset the target when the daemon is launched, or
243 if it should just attach to the target.
246 @section JTAG interface configuration
249 @item @b{interface} <@var{name}>
251 Use the interface driver <@var{name}> to connect to the target. Currently supported
255 PC parallel port bit-banging (Wigglers, PLD download cable, ...)
259 Amontec Chameleon in its JTAG Accelerator configuration connected to a PC's EPP
264 FTDI FT2232 based devices using either the open-source libftdi or the binary only
265 FTD2XX driver. The FTD2XX is superior in performance, but not available on every
266 platform. The libftdi uses libusb, and should be portable to all systems that provide
271 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
276 @item @b{jtag_speed} <@var{reset speed}> <@var{post reset speed}>
278 Limit the maximum speed of the JTAG interface. Usually, a value of zero means maximum
279 speed. The actual effect of this option depends on the JTAG interface used. Reset
280 speed is used during reset and post reset speed after reset. post reset speed
281 is optional, in which case the reset speed is used.
288 @item wiggler: maximum speed / @var{number}
289 @item ft2232: 6MHz / (@var{number}+1)
290 @item amt jtagaccel: 8 / 2**@var{number}
293 Note: Make sure the jtag clock is no more than @math{1/6th × CPU-Clock}. This is
294 especially true for synthesized cores (-S).
296 @item @b{jtag_khz} <@var{reset speed kHz}> <@var{post reset speed kHz}>
298 Same as jtag_speed, except that the speed is specified in maximum kHz. If
299 the device can not support the rate asked for, or can not translate from
300 kHz to jtag_speed, then an error is returned. 0 means RTCK. If RTCK
301 is not supported, then an error is reported.
303 @item @b{reset_config} <@var{signals}> [@var{combination}] [@var{trst_type}] [@var{srst_type}]
305 The configuration of the reset signals available on the JTAG interface AND the target.
306 If the JTAG interface provides SRST, but the target doesn't connect that signal properly,
307 then OpenOCD can't use it. <@var{signals}> can be @samp{none}, @samp{trst_only},
308 @samp{srst_only} or @samp{trst_and_srst}.
309 [@var{combination}] is an optional value specifying broken reset signal implementations.
310 @samp{srst_pulls_trst} states that the testlogic is reset together with the reset of
311 the system (e.g. Philips LPC2000, "broken" board layout), @samp{trst_pulls_srst} says
312 that the system is reset together with the test logic (only hypothetical, I haven't
313 seen hardware with such a bug, and can be worked around).
315 The [@var{trst_type}] and [@var{srst_type}] parameters allow the driver type of the
316 reset lines to be specified. Possible values are @samp{trst_push_pull} (default)
317 and @samp{trst_open_drain} for the test reset signal, and @samp{srst_open_drain}
318 (default) and @samp{srst_push_pull} for the system reset. These values only affect
319 JTAG interfaces with support for different drivers, like the Amontec JTAGkey and JTAGAccelerator.
321 @item @b{jtag_device} <@var{IR length}> <@var{IR capture}> <@var{IR mask}> <@var{IDCODE instruction}>
323 Describes the devices that form the JTAG daisy chain, with the first device being
324 the one closest to TDO. The parameters are the length of the instruction register
325 (4 for all ARM7/9s), the value captured during Capture-IR (0x1 for ARM7/9), and a mask
326 of bits that should be validated when doing IR scans (all four bits (0xf) for ARM7/9).
327 The IDCODE instruction will in future be used to query devices for their JTAG
328 identification code. This line is the same for all ARM7 and ARM9 devices.
329 Other devices, like CPLDs, require different parameters. An example configuration
330 line for a Xilinx XC9500 CPLD would look like this:
332 jtag_device 8 0x01 0x0e3 0xfe
334 The instruction register (IR) is 8 bits long, during Capture-IR 0x01 is loaded into
335 the IR, but only bits 0-1 and 5-7 should be checked, the others (2-4) might vary.
336 The IDCODE instruction is 0xfe.
338 @item @b{jtag_nsrst_delay} <@var{ms}>
339 @cindex jtag_nsrst_delay
340 How long (in miliseconds) the OpenOCD should wait after deasserting nSRST before
341 starting new JTAG operations.
342 @item @b{jtag_ntrst_delay} <@var{ms}>
343 @cindex jtag_ntrst_delay
344 How long (in miliseconds) the OpenOCD should wait after deasserting nTRST before
345 starting new JTAG operations.
347 The jtag_n[st]rst_delay options are useful if reset circuitry (like a reset supervisor,
348 or on-chip features) keep a reset line asserted for some time after the external reset
352 @section parport options
355 @item @b{parport_port} <@var{number}>
357 Either the address of the I/O port (default: 0x378 for LPT1) or the number of
358 the @file{/dev/parport} device
360 When using PPDEV to access the parallel port, use the number of the parallel port:
361 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
362 you may encounter a problem.
363 @item @b{parport_cable} <@var{name}>
364 @cindex parport_cable
365 The layout of the parallel port cable used to connect to the target.
366 Currently supported cables are
370 Original Wiggler layout, also supported by several clones, such
371 as the Olimex ARM-JTAG
372 @item old_amt_wiggler
373 @cindex old_amt_wiggler
374 The Wiggler configuration that comes with Amontec's Chameleon Programmer. The new
375 version available from the website uses the original Wiggler layout ('@var{wiggler}')
378 Describes the connection of the Amontec Chameleon's CPLD when operated in
379 configuration mode. This is only used to program the Chameleon itself, not
383 Xilinx Parallel cable III.
386 The parallel port adapter found on the 'Karo Triton 1 Development Board'.
387 This is also the layout used by the HollyGates design
388 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
393 @item @b{parport_write_on_exit} <@var{on|off}>
394 @cindex parport_write_on_exit
395 This will configure the parallel driver to write a known value to the parallel
396 interface on exiting openocd
399 @section amt_jtagaccel options
401 @item @b{parport_port} <@var{number}>
403 Either the address of the I/O port (default: 0x378 for LPT1) or the number of the
404 @file{/dev/parport} device
406 @section ft2232 options
409 @item @b{ft2232_device_desc} <@var{description}>
410 @cindex ft2232_device_desc
411 The USB device description of the FTDI FT2232 device. If not specified, the FTDI
412 default value is used. This setting is only valid if compiled with FTD2XX support.
413 @item @b{ft2232_layout} <@var{name}>
414 @cindex ft2232_layout
415 The layout of the FT2232 GPIO signals used to control output-enables and reset
416 signals. Valid layouts are
419 The "USBJTAG-1" layout described in the original OpenOCD diploma thesis
421 Amontec JTAGkey and JTAGkey-tiny
427 American Microsystems M5960
429 Luminary Micro EVB_LM3S811 as a JTAG interface (not onboard processor), no TRST or
430 SRST signals on external connector
434 Hitex STM32 Performance Stick
436 Tin Can Tools Flyswatter
438 egnite Software turtelizer2
443 @item @b{ft2232_vid_pid} <@var{vid}> <@var{pid}>
444 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
445 default values are used. This command is not available on Windows.
446 @item @b{ft2232_latency} <@var{ms}>
447 On some systems using ft2232 based JTAG interfaces the FT_Read function call in
448 ft2232_read() fails to return the expected number of bytes. This can be caused by
449 USB communication delays and has proved hard to reproduce and debug. Setting the
450 FT2232 latency timer to a larger value increases delays for short USB packages but it
451 also reduces the risk of timeouts before receiving the expected number of bytes.
452 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
455 @section ep93xx options
456 @cindex ep93xx options
457 Currently, there are no options available for the ep93xx interface.
460 @section Target configuration
463 @item @b{target} <@var{type}> <@var{endianess}> <@var{reset_mode}> <@var{JTAG pos}>
466 Defines a target that should be debugged. Currently supported types are:
480 If you want to use a target board that is not on this list, see Adding a new
483 Endianess may be @option{little} or @option{big}.
485 The reset_mode specifies what should happen to the target when a reset occurs:
489 Immediately request a target halt after reset. This allows targets to be debugged
490 from the very first instruction. This is only possible with targets and JTAG
491 interfaces that correctly implement the reset signals.
494 Similar to @option{reset_halt}, but executes the script file defined to handle the
495 'reset' event for the target. Like @option{reset_halt} this only works with
496 correct reset implementations.
499 Simply let the target run after a reset.
502 Let the target run for some time (default: 1s), and then request halt.
505 A combination of @option{reset_init} and @option{run_and_halt}. The target is allowed
506 to run for some time, then halted, and the @option{reset} event script is executed.
509 On JTAG interfaces / targets where system reset and test-logic reset can't be driven
510 completely independent (like the LPC2000 series), or where the JTAG interface is
511 unavailable for some time during startup (like the STR7 series), you can't use
512 @option{reset_halt} or @option{reset_init}.
514 @item @b{target_script} <@var{target#}> <@var{event}> <@var{script_file}>
515 @cindex target_script
516 Event is either @option{reset}, @option{post_halt}, @option{pre_resume} or @option{gdb_program_config}
518 TODO: describe exact semantic of events
519 @item @b{run_and_halt_time} <@var{target#}> <@var{time_in_ms}>
520 @cindex run_and_halt_time
521 The amount of time the debugger should wait after releasing reset before it asserts
522 a debug request. This is used by the @option{run_and_halt} and @option{run_and_init}
524 @item @b{working_area} <@var{target#}> <@var{address}> <@var{size}>
525 <@var{backup}|@var{nobackup}>
527 Specifies a working area for the debugger to use. This may be used to speed-up
528 downloads to target memory and flash operations, or to perform otherwise unavailable
529 operations (some coprocessor operations on ARM7/9 systems, for example). The last
530 parameter decides whether the memory should be preserved <@var{backup}>. If possible, use
531 a working_area that doesn't need to be backed up, as that slows down operation.
534 @subsection arm7tdmi options
535 @cindex arm7tdmi options
536 target arm7tdmi <@var{endianess}> <@var{reset_mode}> <@var{jtag#}>
537 The arm7tdmi target definition requires at least one additional argument, specifying
538 the position of the target in the JTAG daisy-chain. The first JTAG device is number 0.
539 The optional [@var{variant}] parameter has been removed in recent versions.
540 The correct feature set is determined at runtime.
542 @subsection arm720t options
543 @cindex arm720t options
544 ARM720t options are similar to ARM7TDMI options.
546 @subsection arm9tdmi options
547 @cindex arm9tdmi options
548 ARM9TDMI options are similar to ARM7TDMI options. Supported variants are
549 @option{arm920t}, @option{arm922t} and @option{arm940t}.
550 This enables the hardware single-stepping support found on these cores.
552 @subsection arm920t options
553 @cindex arm920t options
554 ARM920t options are similar to ARM9TDMI options.
556 @subsection arm966e options
557 @cindex arm966e options
558 ARM966e options are similar to ARM9TDMI options.
560 @subsection xscale options
561 @cindex xscale options
562 Supported variants are @option{ixp42x}, @option{ixp45x}, @option{ixp46x},
563 @option{pxa250}, @option{pxa255}, @option{pxa26x}.
565 @section Flash configuration
566 @cindex Flash configuration
569 @item @b{flash bank} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}>
570 <@var{bus_width}> <@var{target#}> [@var{driver_options ...}]
572 Configures a flash bank at <@var{base}> of <@var{size}> bytes and <@var{chip_width}>
573 and <@var{bus_width}> bytes using the selected flash <driver>.
575 @item @b{flash auto_erase} <@option{on}|@option{off}>
576 @cindex flash auto_erase
577 auto erase flash banks prior to writing. Currently only works when using
578 @option{flash write_image} command. Default is @option{off}.
581 @subsection lpc2000 options
582 @cindex lpc2000 options
584 @b{flash bank lpc2000} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
585 <@var{clock}> [@var{calc_checksum}]
586 LPC flashes don't require the chip and bus width to be specified. Additional
587 parameters are the <@var{variant}>, which may be @var{lpc2000_v1} (older LPC21xx and LPC22xx)
588 or @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx), the number
589 of the target this flash belongs to (first is 0), the frequency at which the core
590 is currently running (in kHz - must be an integral number), and the optional keyword
591 @var{calc_checksum}, telling the driver to calculate a valid checksum for the exception
594 @subsection cfi options
597 @b{flash bank cfi} <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}>
599 CFI flashes require the number of the target they're connected to as an additional
600 argument. The CFI driver makes use of a working area (specified for the target)
601 to significantly speed up operation.
603 @var{chip_width} and @var{bus_width} are specified in bytes.
605 @subsection at91sam7 options
606 @cindex at91sam7 options
608 @b{flash bank at91sam7} 0 0 0 0 <@var{target#}>
609 AT91SAM7 flashes only require the @var{target#}, all other values are looked up after
610 reading the chip-id and type.
612 @subsection str7 options
615 @b{flash bank str7x} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
616 variant can be either STR71x, STR73x or STR75x.
618 @subsection str9 options
621 @b{flash bank str9x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
622 The str9 needs the flash controller to be configured prior to Flash programming, eg.
624 str9x flash_config 0 4 2 0 0x80000
626 This will setup the BBSR, NBBSR, BBADR and NBBADR registers respectively.
628 @subsection str9 options (str9xpec driver)
630 @b{flash bank str9xpec} <@var{base}> <@var{size}> 0 0 <@var{target#}>
631 Before using the flash commands the turbo mode will need enabling using str9xpec
632 @option{enable_turbo} <@var{num>.}
634 Only use this driver for locking/unlocking the device or configuring the option bytes.
635 Use the standard str9 driver for programming.
637 @subsection stellaris (LM3Sxxx) options
638 @cindex stellaris (LM3Sxxx) options
640 @b{flash bank stellaris} <@var{base}> <@var{size}> 0 0 <@var{target#}>
641 stellaris flash plugin only require the @var{target#}.
643 @subsection stm32x options
644 @cindex stm32x options
646 @b{flash bank stm32x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
647 stm32x flash plugin only require the @var{target#}.
653 The Open On-Chip Debugger (OpenOCD) allows user interaction through a telnet interface
654 (default: port 4444) and a GDB server (default: port 3333). The command line interpreter
655 is available from both the telnet interface and a GDB session. To issue commands to the
656 interpreter from within a GDB session, use the @option{monitor} command, e.g. use
657 @option{monitor poll} to issue the @option{poll} command. All output is relayed through the
663 @item @b{sleep} <@var{msec}>
665 Wait for n milliseconds before resuming. Useful in connection with script files
666 (@var{script} command and @var{target_script} configuration).
670 Close the OpenOCD daemon, disconnecting all clients (GDB, Telnet).
672 @item @b{debug_level} [@var{n}]
674 Display or adjust debug level to n<0-3>
676 @item @b{log_output} <@var{file}>
678 Redirect logging to <file> (default: stderr)
680 @item @b{script} <@var{file}>
682 Execute commands from <file>
686 @subsection Target state handling
688 @item @b{poll} [@option{on}|@option{off}]
690 Poll the target for its current state. If the target is in debug mode, architecture
691 specific information about the current state are printed. An optional parameter
692 allows continuous polling to be enabled and disabled.
694 @item @b{halt} [@option{ms}]
696 Send a halt request to the target and waits for it to halt for [@option{ms}].
697 Default [@option{ms}] is 5 seconds if no arg given.
698 Optional arg @option{ms} is a timeout in milliseconds. Using 0 as the [@option{ms}]
699 will stop openocd from waiting.
701 @item @b{wait_halt} [@option{ms}]
703 Wait for the target to enter debug mode. Optional [@option{ms}] is
704 a timeout in milliseconds. Default [@option{ms}] is 5 seconds if no
707 @item @b{resume} [@var{address}]
709 Resume the target at its current code position, or at an optional address.
710 Openocd will wait 5 seconds for the target to resume.
712 @item @b{step} [@var{address}]
714 Single-step the target at its current code position, or at an optional address.
716 @item @b{reset} [@option{run}|@option{halt}|@option{init}|@option{run_and_halt}
717 |@option{run_and_init}]
719 Do a hard-reset. The optional parameter specifies what should happen after the reset.
720 This optional parameter overwrites the setting specified in the configuration file,
721 making the new behaviour the default for the @option{reset} command.
728 Immediately halt the target (works only with certain configurations).
731 Immediately halt the target, and execute the reset script (works only with certain
734 @cindex reset run_and_halt
735 Let the target run for a certain amount of time, then request a halt.
737 @cindex reset run_and_init
738 Let the target run for a certain amount of time, then request a halt. Execute the
739 reset script once the target entered debug mode.
743 @subsection Memory access commands
744 These commands allow accesses of a specific size to the memory system:
746 @item @b{mdw} <@var{addr}> [@var{count}]
749 @item @b{mdh} <@var{addr}> [@var{count}]
751 display memory half-words
752 @item @b{mdb} <@var{addr}> [@var{count}]
755 @item @b{mww} <@var{addr}> <@var{value}>
758 @item @b{mwh} <@var{addr}> <@var{value}>
760 write memory half-word
761 @item @b{mwb} <@var{addr}> <@var{value}>
765 @item @b{load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
767 Load image <@var{file}> to target memory at <@var{address}>
768 @item @b{dump_image} <@var{file}> <@var{address}> <@var{size}>
770 Dump <@var{size}> bytes of target memory starting at <@var{address}> to a
771 (binary) <@var{file}>.
772 @item @b{verify_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
774 Verify <@var{file}> to target memory starting at <@var{address}>.
775 This will first attempt using a crc checksum, if this fails it will try a binary compare.
776 @item @b{load_binary} <@var{file}> <@var{address}> [DEPRECATED]
778 Load binary <@var{file}> to target memory at <@var{address}>
779 @item @b{dump_binary} <@var{file}> <@var{address}> <@var{size}> [DEPRECATED]
781 Dump <@var{size}> bytes of target memory starting at <@var{address}> to a
782 (binary) <@var{file}>.
785 @subsection Flash commands
786 @cindex Flash commands
788 @item @b{flash banks}
790 List configured flash banks
791 @item @b{flash info} <@var{num}>
793 Print info about flash bank <@option{num}>
794 @item @b{flash probe} <@var{num}>
796 Identify the flash, or validate the parameters of the configured flash. Operation
797 depends on the flash type.
798 @item @b{flash erase_check} <@var{num}>
799 @cindex flash erase_check
800 Check erase state of sectors in flash bank <@var{num}>. This is the only operation that
801 updates the erase state information displayed by @option{flash info}. That means you have
802 to issue an @option{erase_check} command after erasing or programming the device to get
804 @item @b{flash protect_check} <@var{num}>
805 @cindex flash protect_check
806 Check protection state of sectors in flash bank <num>.
808 @item @b{flash erase} <@var{num}> <@var{first}> <@var{last}> [DEPRECATED]
810 Erase sectors at bank <@var{num}>, starting at sector <@var{first}> up to and including
811 <@var{last}>. Sector numbering starts at 0. Depending on the flash type, erasing might
812 require the protection to be disabled first (e.g. Intel Advanced Bootblock flash using
813 the CFI driver). This command was replaced by the new command
814 @option{flash erase_sector} using the same syntax.
815 @item @b{flash erase_sector} <@var{num}> <@var{first}> <@var{last}>
816 @cindex flash erase_sector
817 Erase sectors at bank <@var{num}>, starting at sector <@var{first}> up to and including
818 <@var{last}>. Sector numbering starts at 0. Depending on the flash type, erasing might
819 require the protection to be disabled first (e.g. Intel Advanced Bootblock flash using
821 @item @b{flash erase_address} <@var{address}> <@var{length}>
822 @cindex flash erase_address
823 Erase sectors starting at <@var{address}> for <@var{length}> number of bytes
824 @item @b{flash write} <@var{num}> <@var{file}> <@var{offset}> [DEPRECATED]
826 Write the binary <@var{file}> to flash bank <@var{num}>, starting at <@var{offset}>
827 bytes from the beginning of the bank. This command was replaced by the new command
828 @option{flash write_binary} using the same syntax.
829 @item @b{flash write_binary} <@var{num}> <@var{file}> <@var{offset}>
830 @cindex flash write_binary
831 Write the binary <@var{file}> to flash bank <@var{num}>, starting at
832 <@option{offset}> bytes from the beginning of the bank.
833 @item @b{flash write_image} <@var{file}> [@var{offset}] [@var{type}]
834 @cindex flash write_image
835 Write the image <@var{file}> to the current target's flash bank(s). A relocation
836 [@var{offset}] can be specified and the file [@var{type}] can be specified
837 explicitly as @option{bin} (binary), @option{ihex} (Intel hex), @option{elf}
838 (ELF file) or @option{s19} (Motorola s19).
839 @item @b{flash protect} <@var{num}> <@var{first}> <@var{last}> <@option{on}|@option{off}>
840 @cindex flash protect
841 Enable (@var{on}) or disable (@var{off}) protection of flash sectors <@var{first}> to
842 <@var{last}> of @option{flash bank} <@var{num}>.
843 @item @b{flash auto_erase} <@var{on}|@var{off}>
844 @cindex flash auto_erase
845 Enable (@option{on}) to erase flash banks prior to writing using the flash @option{write_image} command
846 only. Default is (@option{off}), flash banks have to be erased using @option{flash erase} command.
850 @section Target Specific Commands
851 @cindex Target Specific Commands
853 @subsection AT91SAM7 specific commands
854 @cindex AT91SAM7 specific commands
855 The flash configuration is deduced from the chip identification register. The flash
856 controller handles erases automatically on a page (128/265 byte) basis so erase is
857 not necessary for flash programming. AT91SAM7 processors with less than 512K flash
858 only have a single flash bank embedded on chip. AT91SAM7xx512 have two flash planes
859 that can be erased separatly.Only an EraseAll command is supported by the controller
860 for each flash plane and this is called with
862 @item @b{flash erase} <@var{num}> @var{first_plane} @var{last_plane}
863 bulk erase flash planes first_plane to last_plane.
864 @item @b{at91sam7 gpnvm} <@var{num}> <@var{bit}> <@option{set}|@option{clear}>
865 @cindex at91sam7 gpnvm
866 set or clear a gpnvm bit for the processor
869 @subsection STR9 specific commands
870 @cindex STR9 specific commands
871 These are flash specific commands when using the str9xpec driver.
873 @item @b{str9xpec enable_turbo} <@var{num}>
874 @cindex str9xpec enable_turbo
875 enable turbo mode, simply this will remove the str9 from the chain and talk
876 directly to the embedded flash controller.
877 @item @b{str9xpec disable_turbo} <@var{num}>
878 @cindex str9xpec disable_turbo
879 restore the str9 into jtag chain.
880 @item @b{str9xpec lock} <@var{num}>
881 @cindex str9xpec lock
882 lock str9 device. The str9 will only respond to an unlock command that will
884 @item @b{str9xpec unlock} <@var{num}>
885 @cindex str9xpec unlock
887 @item @b{str9xpec options_read} <@var{num}>
888 @cindex str9xpec options_read
889 read str9 option bytes.
890 @item @b{str9xpec options_write} <@var{num}>
891 @cindex str9xpec options_write
892 write str9 option bytes.
895 @subsection STR9 configuration
896 @cindex STR9 configuration
898 @item @b{str9x flash_config} <@var{bank}> <@var{BBSR}> <@var{NBBSR}>
899 <@var{BBADR}> <@var{NBBADR}>
900 @cindex str9x flash_config
901 Configure str9 flash controller.
903 eg. str9x flash_config 0 4 2 0 0x80000
905 BBSR - Boot Bank Size register
906 NBBSR - Non Boot Bank Size register
907 BBADR - Boot Bank Start Address register
908 NBBADR - Boot Bank Start Address register
912 @subsection STR9 option byte configuration
913 @cindex STR9 option byte configuration
915 @item @b{str9xpec options_cmap} <@var{num}> <@option{bank0}|@option{bank1}>
916 @cindex str9xpec options_cmap
917 configure str9 boot bank.
918 @item @b{str9xpec options_lvdthd} <@var{num}> <@option{2.4v}|@option{2.7v}>
919 @cindex str9xpec options_lvdthd
920 configure str9 lvd threshold.
921 @item @b{str9xpec options_lvdsel} <@var{num}> <@option{vdd}|@option{vdd_vddq}>
922 @cindex str9xpec options_lvdsel
923 configure str9 lvd source.
924 @item @b{str9xpec options_lvdwarn} <@var{bank}> <@option{vdd}|@option{vdd_vddq}>
925 @cindex str9xpec options_lvdwarn
926 configure str9 lvd reset warning source.
929 @subsection STM32x specific commands
930 @cindex STM32x specific commands
932 These are flash specific commands when using the stm32x driver.
934 @item @b{stm32x lock} <@var{num}>
937 @item @b{stm32x unlock} <@var{num}>
938 @cindex stm32x unlock
940 @item @b{stm32x options_read} <@var{num}>
941 @cindex stm32x options_read
942 read stm32 option bytes.
943 @item @b{stm32x options_write} <@var{num}> <@option{SWWDG}|@option{HWWDG}>
944 <@option{RSTSTNDBY}|@option{NORSTSTNDBY}> <@option{RSTSTOP}|@option{NORSTSTOP}>
945 @cindex stm32x options_write
946 write stm32 option bytes.
947 @item @b{stm32x mass_erase} <@var{num}>
948 @cindex stm32x mass_erase
949 mass erase flash memory.
953 @section Architecture Specific Commands
954 @cindex Architecture Specific Commands
956 @subsection ARMV4/5 specific commands
957 @cindex ARMV4/5 specific commands
959 These commands are specific to ARM architecture v4 and v5, like all ARM7/9 systems
960 or Intel XScale (XScale isn't supported yet).
962 @item @b{armv4_5 reg}
964 Display a list of all banked core registers, fetching the current value from every
965 core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
967 @item @b{armv4_5 core_mode} [@option{arm}|@option{thumb}]
968 @cindex armv4_5 core_mode
969 Displays the core_mode, optionally changing it to either ARM or Thumb mode.
970 The target is resumed in the currently set @option{core_mode}.
973 @subsection ARM7/9 specific commands
974 @cindex ARM7/9 specific commands
976 These commands are specific to ARM7 and ARM9 targets, like ARM7TDMI, ARM720t,
977 ARM920t or ARM926EJ-S.
979 @item @b{arm7_9 sw_bkpts} <@option{enable}|@option{disable}>
980 @cindex arm7_9 sw_bkpts
981 Enable/disable use of software breakpoints. On ARMv4 systems, this reserves
982 one of the watchpoint registers to implement software breakpoints. Disabling
983 SW Bkpts frees that register again.
984 @item @b{arm7_9 force_hw_bkpts} <@option{enable}|@option{disable}>
985 @cindex arm7_9 force_hw_bkpts
986 When @option{force_hw_bkpts} is enabled, the @option{sw_bkpts} support is disabled, and all
987 breakpoints are turned into hardware breakpoints.
988 @item @b{arm7_9 dbgrq} <@option{enable}|@option{disable}>
990 Enable use of the DBGRQ bit to force entry into debug mode. This should be
991 safe for all but ARM7TDMI--S cores (like Philips LPC).
992 @item @b{arm7_9 fast_writes} <@option{enable}|@option{disable}>
993 @cindex arm7_9 fast_writes [DEPRECATED]
994 See @option{arm7_9 fast_memory_access} instead.
995 @item @b{arm7_9 fast_memory_access} <@option{enable}|@option{disable}>
996 @cindex arm7_9 fast_memory_access
997 Allow the OpenOCD to read and write memory without checking completion of
998 the operation. This provides a huge speed increase, especially with USB JTAG
999 cables (FT2232), but might be unsafe if used with targets running at a very low
1000 speed, like the 32kHz startup clock of an AT91RM9200.
1001 @item @b{arm7_9 dcc_downloads} <@option{enable}|@option{disable}>
1002 @cindex arm7_9 dcc_downloads
1003 Enable the use of the debug communications channel (DCC) to write larger (>128 byte)
1004 amounts of memory. DCC downloads offer a huge speed increase, but might be potentially
1005 unsafe, especially with targets running at a very low speed. This command was introduced
1006 with OpenOCD rev. 60.
1009 @subsection ARM920T specific commands
1010 @cindex ARM920T specific commands
1013 @item @b{arm920t cache_info}
1014 @cindex arm920t cache_info
1015 Print information about the caches found. This allows you to see if your target
1016 is a ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
1017 @item @b{arm920t md<bhw>_phys} <@var{addr}> [@var{count}]
1018 @cindex arm920t md<bhw>_phys
1019 Display memory at physical address addr.
1020 @item @b{arm920t mw<bhw>_phys} <@var{addr}> <@var{value}>
1021 @cindex arm920t mw<bhw>_phys
1022 Write memory at physical address addr.
1023 @item @b{arm920t read_cache} <@var{filename}>
1024 @cindex arm920t read_cache
1025 Dump the content of ICache and DCache to a file.
1026 @item @b{arm920t read_mmu} <@var{filename}>
1027 @cindex arm920t read_mmu
1028 Dump the content of the ITLB and DTLB to a file.
1029 @item @b{arm920t virt2phys} <@var{VA}>
1030 @cindex arm920t virt2phys
1031 Translate a virtual address to a physical address.
1035 @section Debug commands
1036 @cindex Debug commands
1037 The following commands give direct access to the core, and are most likely
1038 only useful while debugging the OpenOCD.
1040 @item @b{arm7_9 write_xpsr} <@var{32-bit value}> <@option{0=cpsr}, @option{1=spsr}>
1041 @cindex arm7_9 write_xpsr
1042 Immediately write either the current program status register (CPSR) or the saved
1043 program status register (SPSR), without changing the register cache (as displayed
1044 by the @option{reg} and @option{armv4_5 reg} commands).
1045 @item @b{arm7_9 write_xpsr_im8} <@var{8-bit value}> <@var{rotate 4-bit}>
1046 <@var{0=cpsr},@var{1=spsr}>
1047 @cindex arm7_9 write_xpsr_im8
1048 Write the 8-bit value rotated right by 2*rotate bits, using an immediate write
1049 operation (similar to @option{write_xpsr}).
1050 @item @b{arm7_9 write_core_reg} <@var{num}> <@var{mode}> <@var{value}>
1051 @cindex arm7_9 write_core_reg
1052 Write a core register, without changing the register cache (as displayed by the
1053 @option{reg} and @option{armv4_5 reg} commands). The <@var{mode}> argument takes the
1054 encoding of the [M4:M0] bits of the PSR.
1058 @section JTAG commands
1059 @cindex JTAG commands
1061 @item @b{scan_chain}
1063 Print current scan chain configuration.
1064 @item @b{jtag_reset}
1066 Toggle reset lines <@var{trst}> <@var{srst}>.
1067 @item @b{endstate} <@var{tap_state}>
1069 Finish JTAG operations in <@var{tap_state}>.
1070 @item @b{runtest} <@var{num_cycles}>
1072 Move to Run-Test/Idle, and execute <@var{num_cycles}>
1073 @item @b{statemove} [@var{tap_state}]
1075 Move to current endstate or [@var{tap_state}]
1078 Execute IR scan <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
1081 Execute DR scan <@var{device}> [@var{dev2}] [@var{var2}] ...
1082 @item @b{verify_ircapture}
1083 @cindex verify_ircapture
1084 Verify value captured during Capture-IR <@option{enable}|@option{disable}>
1087 Allocate, display or delete variable <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
1090 Display/modify variable field <@var{var}> <@var{field}> [@var{value}|@var{flip}]
1093 @node Sample Scripts
1094 @chapter Sample Scripts
1097 This page will collect some script examples for different CPUs.
1099 The configuration script can be divided in the following section:
1101 @item daemon configuration
1103 @item jtag scan chain
1104 @item target configuration
1105 @item flash configuration
1108 Detailed information about each section can be found at OpenOCD configuration
1110 @section OMAP5912 Flash Debug
1111 @cindex OMAP5912 Flash Debug
1112 The following two scripts were used with a wiggler PP and and a TI OMAP5912
1113 dual core processor - (@uref{http://www.ti.com}), on a OMAP5912 OSK board
1114 - (@uref{http://www.spectrumdigital.com}).
1115 @subsection Openocd config
1117 #daemon configuration
1124 parport_cable wiggler
1127 #use combined on interfaces or targets that can't set TRST/SRST separately
1128 reset_config trst_and_srst
1131 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1132 jtag_device 38 0x0 0x0 0x0
1133 jtag_device 4 0x1 0x0 0xe
1134 jtag_device 8 0x0 0x0 0x0
1136 #target configuration
1137 daemon_startup reset
1139 #target <type> <endianness> <reset mode> <chainpos> <variant>
1140 target arm926ejs little run_and_init 1 arm926ejs
1141 target_script 0 reset omap5912_osk.init
1142 run_and_halt_time 0 30
1144 # omap5912 lcd frame buffer as working area
1145 working_area 0 0x20000000 0x3e800 nobackup
1147 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1148 flash bank cfi 0x00000000 0x1000000 2 2 0
1151 @subsection Openocd init
1163 mww 0xfffec808 0x000000f5
1164 mww 0xfffec808 0x000000a0
1166 mww 0xfffeb048 0x0000aaaa
1168 mww 0xfffeb048 0x00005555
1177 @section STR71x Script
1178 @cindex STR71x Script
1179 The following script was used with an Amontec JTAGkey and a STR710 / STR711 CPU:
1181 #daemon configuration
1187 ft2232_device_desc "Amontec JTAGkey A"
1188 ft2232_layout jtagkey
1189 ft2232_vid_pid 0x0403 0xcff8
1192 #use combined on interfaces or targets that can't set TRST/SRST separately
1193 reset_config trst_and_srst srst_pulls_trst
1196 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1197 jtag_device 4 0x1 0xf 0xe
1199 #target configuration
1200 daemon_startup reset
1202 #target <type> <startup mode>
1203 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1204 target arm7tdmi little run_and_halt 0 arm7tdmi
1205 run_and_halt_time 0 30
1207 working_area 0 0x2000C000 0x4000 nobackup
1209 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1210 flash bank str7x 0x40000000 0x00040000 0 0 0 STR71x
1213 @section STR750 Script
1214 @cindex STR750 Script
1215 The following script was used with an Amontec JTAGkey and a STR750 CPU:
1217 #daemon configuration
1223 ft2232_device_desc "Amontec JTAGkey A"
1224 ft2232_layout jtagkey
1225 ft2232_vid_pid 0x0403 0xcff8
1228 #use combined on interfaces or targets that can't set TRST/SRST separately
1229 #reset_config trst_and_srst srst_pulls_trst
1230 reset_config trst_and_srst srst_pulls_trst
1233 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1234 jtag_device 4 0x1 0xf 0xe
1236 #jtag nTRST and nSRST delay
1237 jtag_nsrst_delay 500
1238 jtag_ntrst_delay 500
1240 #target configuration
1241 daemon_startup reset
1243 #target <type> <startup mode>
1244 #target arm7tdmi <reset mode> <chainpos> <endianness> <variant>
1245 target arm7tdmi little run_and_halt 0 arm7tdmi
1246 run_and_halt_time 0 30
1248 working_area 0 0x40000000 0x4000 nobackup
1250 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1251 flash bank str7x 0x20000000 0x000040000 0 0 0 STR75x
1254 @section STR912 Script
1255 @cindex STR912 Script
1256 The following script was used with an Amontec JTAGkey and a STR912 CPU:
1258 #daemon configuration
1264 ft2232_device_desc "Amontec JTAGkey A"
1265 ft2232_layout jtagkey
1268 #use combined on interfaces or targets that can't set TRST/SRST separately
1269 reset_config trst_and_srst
1272 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1273 jtag_device 8 0x1 0x1 0xfe
1274 jtag_device 4 0x1 0xf 0xe
1275 jtag_device 5 0x1 0x1 0x1e
1277 #target configuration
1278 daemon_startup reset
1280 #target <type> <startup mode>
1281 #target arm966e <endianness> <reset mode> <chainpos> <variant>
1282 target arm966e little reset_halt 1 arm966e
1283 run_and_halt_time 0 30
1285 working_area 0 0x50000000 16384 nobackup
1287 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1288 flash bank str9x 0x00000000 0x00080000 0 0 0
1291 @section STR912 comstick
1292 @cindex STR912 comstick Script
1293 The following script was used with a Hitex STR9 Comstick:
1295 #daemon configuration
1301 ft2232_device_desc "STR9-comStick A"
1302 ft2232_layout comstick
1305 jtag_nsrst_delay 100
1306 jtag_ntrst_delay 100
1308 #use combined on interfaces or targets that can't set TRST/SRST separately
1309 reset_config trst_and_srst
1312 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1313 jtag_device 8 0x1 0x1 0xfe
1314 jtag_device 4 0x1 0xf 0xe
1315 jtag_device 5 0x1 0x1 0x1e
1317 #target configuration
1318 daemon_startup reset
1320 #target <type> <startup mode>
1321 #target arm966e <endianness> <reset mode> <chainpos> <variant>
1322 target arm966e little reset_halt 1 arm966e
1323 run_and_halt_time 0 30
1325 working_area 0 0x50000000 16384 nobackup
1327 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1328 flash bank str9x 0x00000000 0x00080000 0 0 0
1331 @section STM32x Script
1332 @cindex STM32x Script
1333 The following script was used with an Amontec JTAGkey and a STM32x CPU:
1335 #daemon configuration
1341 ft2232_device_desc "Amontec JTAGkey A"
1342 ft2232_layout jtagkey
1345 jtag_nsrst_delay 100
1346 jtag_ntrst_delay 100
1348 #use combined on interfaces or targets that can't set TRST/SRST separately
1349 reset_config trst_and_srst
1352 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1353 jtag_device 4 0x1 0xf 0xe
1354 jtag_device 5 0x1 0x1 0x1e
1356 #target configuration
1357 daemon_startup reset
1359 #target <type> <startup mode>
1360 #target cortex_m3 <endianness> <reset mode> <chainpos> <variant>
1361 target cortex_m3 little run_and_halt 0
1362 run_and_halt_time 0 30
1364 working_area 0 0x20000000 16384 nobackup
1366 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1367 flash bank stm32x 0x08000000 0x00020000 0 0 0
1370 @section STM32x Performance Stick
1371 @cindex STM32x Performance Stick Script
1372 The following script was used with the Hitex STM32 Performance Stick
1374 #daemon configuration
1380 ft2232_device_desc "STM32-PerformanceStick A"
1381 ft2232_layout stm32stick
1384 jtag_nsrst_delay 100
1385 jtag_ntrst_delay 100
1387 #use combined on interfaces or targets that can't set TRST/SRST separately
1388 reset_config trst_and_srst
1391 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1392 jtag_device 4 0x1 0xf 0xe
1393 jtag_device 5 0x1 0x1 0x1e
1394 jtag_device 4 0x1 0xf 0xe
1396 #target configuration
1397 daemon_startup reset
1399 #target <type> <startup mode>
1400 #target cortex_m3 <endianness> <reset mode> <chainpos> <variant>
1401 target cortex_m3 little run_and_halt 0
1402 run_and_halt_time 0 30
1404 working_area 0 0x20000000 16384 nobackup
1406 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1407 flash bank stm32x 0x08000000 0x00020000 0 0 0
1410 @section LPC2129 Script
1411 @cindex LPC2129 Script
1412 The following script was used with an wiggler PP and a LPC-2129 CPU:
1414 #daemon configuration
1421 parport_cable wiggler
1424 #use combined on interfaces or targets that can't set TRST/SRST separately
1425 reset_config trst_and_srst srst_pulls_trst
1428 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1429 jtag_device 4 0x1 0xf 0xe
1431 #target configuration
1432 daemon_startup reset
1434 #target <type> <startup mode>
1435 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1436 target arm7tdmi little run_and_halt 0 arm7tdmi-s_r4
1437 run_and_halt_time 0 30
1439 working_area 0 0x40000000 0x4000 nobackup
1441 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1442 flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14765 calc_checksum
1445 @section LPC2148 Script
1446 @cindex LPC2148 Script
1447 The following script was used with an Amontec JTAGkey and a LPC2148 CPU:
1449 #daemon configuration
1455 ft2232_device_desc "Amontec JTAGkey A"
1456 ft2232_layout jtagkey
1457 ft2232_vid_pid 0x0403 0xcff8
1460 #use combined on interfaces or targets that can't set TRST/SRST separately
1461 reset_config trst_and_srst srst_pulls_trst
1464 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1465 jtag_device 4 0x1 0xf 0xe
1467 #target configuration
1468 daemon_startup reset
1470 #target <type> <startup mode>
1471 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1472 target arm7tdmi little run_and_halt 0 arm7tdmi-s_r4
1473 run_and_halt_time 0 30
1475 working_area 0 0x40000000 0x8000 nobackup
1477 #flash configuration
1478 flash bank lpc2000 0x0 0x7d000 0 0 0 lpc2000_v1 14765 calc_checksum
1481 @section LPC2294 Script
1482 @cindex LPC2294 Script
1483 The following script was used with an Amontec JTAGkey and a LPC2294 CPU:
1485 #daemon configuration
1491 ft2232_device_desc "Amontec JTAGkey A"
1492 ft2232_layout jtagkey
1493 ft2232_vid_pid 0x0403 0xcff8
1496 #use combined on interfaces or targets that can't set TRST/SRST separately
1497 reset_config trst_and_srst srst_pulls_trst
1500 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1501 jtag_device 4 0x1 0xf 0xe
1503 #target configuration
1504 daemon_startup reset
1506 #target <type> <startup mode>
1507 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1508 target arm7tdmi little run_and_halt 0 arm7tdmi-s_r4
1509 run_and_halt_time 0 30
1511 working_area 0 0x40000000 0x4000 nobackup
1513 #flash configuration
1514 flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14765 calc_checksum
1517 @section AT91R40008 Script
1518 @cindex AT91R40008 Script
1519 The following script was used with an Amontec JTAGkey and a AT91R40008 CPU:
1521 #daemon configuration
1527 ft2232_device_desc "Amontec JTAGkey A"
1528 ft2232_layout jtagkey
1529 ft2232_vid_pid 0x0403 0xcff8
1531 jtag_nsrst_delay 200
1532 jtag_ntrst_delay 200
1534 #use combined on interfaces or targets that can't set TRST/SRST separately
1535 reset_config srst_only srst_pulls_trst
1538 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1539 jtag_device 4 0x1 0xf 0xe
1541 #target configuration
1542 daemon_startup reset
1544 #target <type> <startup mode>
1545 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1546 target arm7tdmi little run_and_halt 0 arm7tdmi
1547 run_and_halt_time 0 30
1550 @section AT91SAM7s Script
1551 @cindex AT91SAM7s Script
1552 The following script was used with an Olimex ARM-JTAG-OCD and a AT91SAM7S64 CPU:
1554 #daemon configuration
1560 ft2232_device_desc "Olimex OpenOCD JTAG A"
1561 ft2232_layout olimex-jtag
1562 ft2232_vid_pid 0x15BA 0x0003
1564 jtag_nsrst_delay 200
1565 jtag_ntrst_delay 200
1567 #use combined on interfaces or targets that can't set TRST/SRST separately
1568 reset_config srst_only srst_pulls_trst
1571 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1572 jtag_device 4 0x1 0xf 0xe
1574 #target configuration
1575 daemon_startup reset
1577 #target <type> <startup mode>
1578 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1579 target arm7tdmi little run_and_halt 0 arm7tdmi
1580 run_and_halt_time 0 30
1582 # flash-options AT91
1583 working_area 0 0x00200000 0x4000 nobackup
1584 flash bank at91sam7 0 0 0 0 0
1587 # erase command (telnet-interface) for complete flash:
1588 # flash erase <num> 0 numlockbits-1 (can be seen from output of flash info 0)
1589 # SAM7S64 with 16 lockbits and bank 0: flash erase 0 0 15
1590 # set/clear NVM-Bits:
1591 # at91sam7 gpnvm <num> <bit> <set|clear>
1592 # disable locking from SAM-BA:
1593 # flash protect 0 0 1 off
1596 @section XSCALE IXP42x Script
1597 @cindex XSCALE IXP42x Script
1598 The following script was used with an Amontec JTAGkey-Tiny and a xscale ixp42x CPU:
1600 #daemon configuration
1606 ft2232_device_desc "Amontec JTAGkey A"
1607 ft2232_layout jtagkey
1608 ft2232_vid_pid 0x0403 0xcff8
1610 jtag_nsrst_delay 200
1611 jtag_ntrst_delay 200
1613 #use combined on interfaces or targets that can't set TRST/SRST separately
1614 reset_config srst_only srst_pulls_trst
1617 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1618 jtag_device 7 0x1 0x7f 0x7e
1620 #target configuration
1621 daemon_startup reset
1623 #target <type> <startup mode>
1624 #target arm7tdmi <reset mode> <chainpos> <endianness> <variant>
1625 target xscale big run_and_halt 0 IXP42x
1626 run_and_halt_time 0 30
1629 @section Cirrus Logic EP9301 Script
1630 @cindex Cirrus Logic EP9301 Script
1631 The following script was used with FT2232 based JTAG interfaces and a
1632 Cirrus Logic EP9301 processor on an Olimex CS-E9301 board.
1634 #daemon configuration
1642 #ft2232_device_desc "Olimex OpenOCD JTAG"
1643 #ft2232_layout olimex-jtag
1644 #ft2232_vid_pid 0x15ba 0x0003
1646 #Amontec JTAGkey (and JTAGkey-Tiny)
1647 #Serial is only necessary if more than one JTAGkey is connected
1648 ft2232_device_desc "Amontec JTAGkey A"
1649 #ft2232_serial AMTJKV31
1650 #ft2232_serial T1P3S2W8
1651 ft2232_layout jtagkey
1652 ft2232_vid_pid 0x0403 0xcff8
1654 #wiggler/parallel port interface
1657 #parport_cable wiggler
1660 reset_config trst_and_srst
1663 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1664 jtag_device 4 0x1 0xf 0xe
1666 jtag_nsrst_delay 100
1667 jtag_ntrst_delay 100
1669 #target configuration
1670 daemon_startup attach
1672 #target <type> <endianess> <reset mode>
1673 target arm920t little reset_halt 0
1674 working_area 0 0x80014000 0x1000 backup
1676 #flash configuration
1677 #flash bank <driver> <base> <size> <chip_width> <bus_width> [driver_options ...]
1678 flash bank cfi 0x60000000 0x1000000 2 2 0
1681 @section Hilscher netX 100 / 500 Script
1682 @cindex Hilscher netX 100 / 500 Script
1683 The following script was used with an Amontec JTAGkey and a Hilscher
1686 #daemon configuration
1692 ft2232_device_desc "Amontec JTAGkey A"
1693 ft2232_layout jtagkey
1694 ft2232_vid_pid 0x0403 0xcff8
1697 #use combined on interfaces or targets that can't set TRST/SRST separately
1698 reset_config trst_and_srst
1701 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1702 jtag_device 4 0x1 0xf 0xe
1704 jtag_nsrst_delay 100
1705 jtag_ntrst_delay 100
1707 #target configuration
1708 daemon_startup reset
1710 #target <type> <endianness> <startup mode> <chainpos> <variant>
1711 target arm926ejs little run_and_halt 0 arm926ejs
1712 run_and_halt_time 0 500
1715 @section Marvell/Intel PXA270 Script
1716 @cindex Marvell/Intel PXA270 Script
1718 # config for Intel PXA270
1719 # not, as of 2007-06-22, openocd only works with the
1720 # libftd2xx library from ftdi. libftdi does not work.
1726 ft2232_layout olimex-jtag
1727 ft2232_vid_pid 0x15BA 0x0003
1728 ft2232_device_desc "Olimex OpenOCD JTAG"
1730 # set jtag_nsrst_delay to the delay introduced by your reset circuit
1731 # the rest of the needed delays are built into the openocd program
1732 jtag_nsrst_delay 260
1733 # set the jtag_ntrst_delay to the delay introduced by a reset circuit
1734 # the rest of the needed delays are built into the openocd program
1737 #use combined on interfaces or targets that can't set TRST/SRST separately
1738 reset_config trst_and_srst separate
1741 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1742 jtag_device 7 0x1 0x7f 0x7e
1744 #target configuration
1745 daemon_startup reset
1747 target xscale little reset_halt 0 pxa27x
1749 # maps to PXA internal RAM. If you are using a PXA255
1750 # you must initialize SDRAM or leave this option off
1751 working_area 0 0x5c000000 0x10000 nobackup
1753 run_and_halt_time 0 30
1755 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1756 # works for P30 flash
1757 flash bank cfi 0x00000000 0x1000000 2 4 0
1760 @node GDB and Openocd
1761 @chapter GDB and Openocd
1762 @cindex GDB and Openocd
1763 Openocd complies with the remote gdbserver protocol, and as such can be used
1764 to debug remote targets.
1766 @section Connecting to gdb
1767 @cindex Connecting to gdb
1768 A connection is typically started as follows:
1770 target remote localhost:3333
1772 This would cause gdb to connect to the gdbserver on the local pc using port 3333.
1774 To see a list of available openocd commands type @option{monitor help} on the
1777 Openocd supports the gdb @option{qSupported} packet, this enables information
1778 to be sent by the gdb server (openocd) to gdb. Typical information includes
1779 packet size and device memory map.
1781 Previous versions of openocd required the following gdb options to increase
1782 the packet size and speed up gdb communication.
1784 set remote memory-write-packet-size 1024
1785 set remote memory-write-packet-size fixed
1786 set remote memory-read-packet-size 1024
1787 set remote memory-read-packet-size fixed
1789 This is now handled in the @option{qSupported} PacketSize.
1791 @section Programming using gdb
1792 @cindex Programming using gdb
1794 By default the target memory map is not sent to gdb, this can be enabled by
1795 the following openocd config option:
1797 gdb_memory_map enable
1799 For this to function correctly a valid flash config must also be configured
1800 in openocd. For speed also configure a valid working area.
1802 Informing gdb of the memory map of the target will enable gdb to protect any
1803 flash area of the target and use hardware breakpoints by default. This means
1804 that the openocd option @option{arm7_9 force_hw_bkpts} is not required when
1807 To view the configured memory map in gdb, use the gdb command @option{info mem}
1808 All other unasigned addresses within gdb are treated as RAM.
1810 If @option{gdb_flash_program enable} is also used, gdb will be able to
1811 program any flash memory using the vFlash interface.
1813 gdb will look at the target memory map when a load command is given, if any
1814 areas to be programmed lie within the target flash area the vFlash packets
1817 Incase the target needs configuring before gdb programming, a script can be executed.
1819 target_script 0 gdb_program_config config.script
1822 To verify any flash programming the gdb command @option{compare-sections}
1829 @item OpenOCD complains about a missing cygwin1.dll.
1831 Make sure you have Cygwin installed, or at least a version of OpenOCD that
1832 claims to come with all the necessary dlls. When using Cygwin, try launching
1833 the OpenOCD from the Cygwin shell.
1835 @item I'm trying to set a breakpoint using GDB (or a frontend like Insight or
1836 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
1837 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
1839 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
1840 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720t or ARM920t,
1841 software breakpoints consume one of the two available hardware breakpoints,
1842 and are therefore disabled by default. If your code is running from RAM, you
1843 can enable software breakpoints with the @option{arm7_9 sw_bkpts enable} command. If
1844 your code resides in Flash, you can't use software breakpoints, but you can force
1845 OpenOCD to use hardware breakpoints instead: @option{arm7_9 force_hw_bkpts enable}.
1847 @item When erasing or writing LPC2000 on-chip flash, the operation fails sometimes
1848 and works sometimes fine.
1850 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
1851 clock at the time you're programming the flash. If you've specified the crystal's
1852 frequency, make sure the PLL is disabled, if you've specified the full core speed
1853 (e.g. 60MHz), make sure the PLL is enabled.
1855 @item When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
1856 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
1857 out while waiting for end of scan, rtck was disabled".
1859 Make sure your PC's parallel port operates in EPP mode. You might have to try several
1860 settings in your PC BIOS (ECP, EPP, and different versions of those).
1862 @item When debugging with the OpenOCD and GDB (plain GDB, Insight, or Eclipse),
1863 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
1864 memory read caused data abort".
1866 The errors are non-fatal, and are the result of GDB trying to trace stack frames
1867 beyond the last valid frame. It might be possible to prevent this by setting up
1868 a proper "initial" stack frame, if you happen to know what exactly has to
1869 be done, feel free to add this here.
1871 @item I get the following message in the OpenOCD console (or log file):
1872 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
1874 This warning doesn't indicate any serious problem, as long as you don't want to
1875 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
1876 trst_and_srst srst_pulls_trst} to tell the OpenOCD that either your board,
1877 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
1878 independently. With this setup, it's not possible to halt the core right out of
1879 reset, everything else should work fine.
1881 @item When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
1882 Toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
1883 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
1884 quit with an error message. Is there a stability issue with OpenOCD?
1886 No, this is not a stability issue concerning OpenOCD. Most users have solved
1887 this issue by simply using a self-powered USB hub, which they connect their
1888 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
1889 supply stable enough for the Amontec JTAGkey to be operated.
1891 @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
1892 following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
1893 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
1894 What does that mean and what might be the reason for this?
1896 First of all, the reason might be the USB power supply. Try using a self-powered
1897 hub instead of a direct connection to your computer. Secondly, the error code 4
1898 corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
1899 chip ran into some sort of error - this points us to a USB problem.
1901 @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
1902 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
1903 What does that mean and what might be the reason for this?
1905 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
1906 has closed the connection to OpenOCD. This might be a GDB issue.
1908 @item In the configuration file in the section where flash device configurations
1909 are described, there is a parameter for specifying the clock frequency for
1910 LPC2000 internal flash devices (e.g.
1911 @option{flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14746 calc_checksum}),
1912 which must be specified in kilohertz. However, I do have a quartz crystal of a
1913 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz, i.e. 14,745.600 kHz).
1914 Is it possible to specify real numbers for the clock frequency?
1916 No. The clock frequency specified here must be given as an integral number.
1917 However, this clock frequency is used by the In-Application-Programming (IAP)
1918 routines of the LPC2000 family only, which seems to be very tolerant concerning
1919 the given clock frequency, so a slight difference between the specified clock
1920 frequency and the actual clock frequency will not cause any trouble.
1922 @item Do I have to keep a specific order for the commands in the configuration file?
1924 Well, yes and no. Commands can be given in arbitrary order, yet the devices
1925 listed for the JTAG scan chain must be given in the right order (jtag_device),
1926 with the device closest to the TDO-Pin being listed first. In general,
1927 whenever objects of the same type exist which require an index number, then
1928 these objects must be given in the right order (jtag_devices, targets and flash
1929 banks - a target references a jtag_device and a flash bank references a target).
1931 @item Sometimes my debugging session terminates with an error. When I look into the
1932 log file, I can see these error messages: Error: arm7_9_common.c:561
1933 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP